1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PCIe driver for Renesas R-Car SoCs
4*4882a593Smuzhiyun * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Phil Edworthy <phil.edworthy@renesas.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "pcie-rcar.h"
13*4882a593Smuzhiyun
rcar_pci_write_reg(struct rcar_pcie * pcie,u32 val,unsigned int reg)14*4882a593Smuzhiyun void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun writel(val, pcie->base + reg);
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
rcar_pci_read_reg(struct rcar_pcie * pcie,unsigned int reg)19*4882a593Smuzhiyun u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun return readl(pcie->base + reg);
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
rcar_rmw32(struct rcar_pcie * pcie,int where,u32 mask,u32 data)24*4882a593Smuzhiyun void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun unsigned int shift = BITS_PER_BYTE * (where & 3);
27*4882a593Smuzhiyun u32 val = rcar_pci_read_reg(pcie, where & ~3);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun val &= ~(mask << shift);
30*4882a593Smuzhiyun val |= data << shift;
31*4882a593Smuzhiyun rcar_pci_write_reg(pcie, val, where & ~3);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
rcar_pcie_wait_for_phyrdy(struct rcar_pcie * pcie)34*4882a593Smuzhiyun int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun unsigned int timeout = 10;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun while (timeout--) {
39*4882a593Smuzhiyun if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun msleep(5);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return -ETIMEDOUT;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
rcar_pcie_wait_for_dl(struct rcar_pcie * pcie)48*4882a593Smuzhiyun int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun unsigned int timeout = 10000;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun while (timeout--) {
53*4882a593Smuzhiyun if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun udelay(5);
57*4882a593Smuzhiyun cpu_relax();
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return -ETIMEDOUT;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
rcar_pcie_set_outbound(struct rcar_pcie * pcie,int win,struct resource_entry * window)63*4882a593Smuzhiyun void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
64*4882a593Smuzhiyun struct resource_entry *window)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun /* Setup PCIe address space mappings for each resource */
67*4882a593Smuzhiyun struct resource *res = window->res;
68*4882a593Smuzhiyun resource_size_t res_start;
69*4882a593Smuzhiyun resource_size_t size;
70*4882a593Smuzhiyun u32 mask;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun * The PAMR mask is calculated in units of 128Bytes, which
76*4882a593Smuzhiyun * keeps things pretty simple.
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun size = resource_size(res);
79*4882a593Smuzhiyun if (size > 128)
80*4882a593Smuzhiyun mask = (roundup_pow_of_two(size) / SZ_128) - 1;
81*4882a593Smuzhiyun else
82*4882a593Smuzhiyun mask = 0x0;
83*4882a593Smuzhiyun rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (res->flags & IORESOURCE_IO)
86*4882a593Smuzhiyun res_start = pci_pio_to_address(res->start) - window->offset;
87*4882a593Smuzhiyun else
88*4882a593Smuzhiyun res_start = res->start - window->offset;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
91*4882a593Smuzhiyun rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
92*4882a593Smuzhiyun PCIEPALR(win));
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* First resource is for IO */
95*4882a593Smuzhiyun mask = PAR_ENABLE;
96*4882a593Smuzhiyun if (res->flags & IORESOURCE_IO)
97*4882a593Smuzhiyun mask |= IO_SPACE;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
rcar_pcie_set_inbound(struct rcar_pcie * pcie,u64 cpu_addr,u64 pci_addr,u64 flags,int idx,bool host)102*4882a593Smuzhiyun void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
103*4882a593Smuzhiyun u64 pci_addr, u64 flags, int idx, bool host)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * Set up 64-bit inbound regions as the range parser doesn't
107*4882a593Smuzhiyun * distinguish between 32 and 64-bit types.
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun if (host)
110*4882a593Smuzhiyun rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
111*4882a593Smuzhiyun PCIEPRAR(idx));
112*4882a593Smuzhiyun rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
113*4882a593Smuzhiyun rcar_pci_write_reg(pcie, flags, PCIELAMR(idx));
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (host)
116*4882a593Smuzhiyun rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
117*4882a593Smuzhiyun PCIEPRAR(idx + 1));
118*4882a593Smuzhiyun rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1));
119*4882a593Smuzhiyun rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
120*4882a593Smuzhiyun }
121