1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) Microsoft Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author:
6*4882a593Smuzhiyun * Jake Oshins <jakeo@microsoft.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This driver acts as a paravirtual front-end for PCI Express root buses.
9*4882a593Smuzhiyun * When a PCI Express function (either an entire device or an SR-IOV
10*4882a593Smuzhiyun * Virtual Function) is being passed through to the VM, this driver exposes
11*4882a593Smuzhiyun * a new bus to the guest VM. This is modeled as a root PCI bus because
12*4882a593Smuzhiyun * no bridges are being exposed to the VM. In fact, with a "Generation 2"
13*4882a593Smuzhiyun * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
14*4882a593Smuzhiyun * until a device as been exposed using this driver.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * Each root PCI bus has its own PCI domain, which is called "Segment" in
17*4882a593Smuzhiyun * the PCI Firmware Specifications. Thus while each device passed through
18*4882a593Smuzhiyun * to the VM using this front-end will appear at "device 0", the domain will
19*4882a593Smuzhiyun * be unique. Typically, each bus will have one PCI function on it, though
20*4882a593Smuzhiyun * this driver does support more than one.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * In order to map the interrupts from the device through to the guest VM,
23*4882a593Smuzhiyun * this driver also implements an IRQ Domain, which handles interrupts (either
24*4882a593Smuzhiyun * MSI or MSI-X) associated with the functions on the bus. As interrupts are
25*4882a593Smuzhiyun * set up, torn down, or reaffined, this driver communicates with the
26*4882a593Smuzhiyun * underlying hypervisor to adjust the mappings in the I/O MMU so that each
27*4882a593Smuzhiyun * interrupt will be delivered to the correct virtual processor at the right
28*4882a593Smuzhiyun * vector. This driver does not support level-triggered (line-based)
29*4882a593Smuzhiyun * interrupts, and will report that the Interrupt Line register in the
30*4882a593Smuzhiyun * function's configuration space is zero.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
33*4882a593Smuzhiyun * facilities. For instance, the configuration space of a function exposed
34*4882a593Smuzhiyun * by Hyper-V is mapped into a single page of memory space, and the
35*4882a593Smuzhiyun * read and write handlers for config space must be aware of this mechanism.
36*4882a593Smuzhiyun * Similarly, device setup and teardown involves messages sent to and from
37*4882a593Smuzhiyun * the PCI back-end driver in Hyper-V.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <linux/kernel.h>
41*4882a593Smuzhiyun #include <linux/module.h>
42*4882a593Smuzhiyun #include <linux/pci.h>
43*4882a593Smuzhiyun #include <linux/delay.h>
44*4882a593Smuzhiyun #include <linux/semaphore.h>
45*4882a593Smuzhiyun #include <linux/irqdomain.h>
46*4882a593Smuzhiyun #include <asm/irqdomain.h>
47*4882a593Smuzhiyun #include <asm/apic.h>
48*4882a593Smuzhiyun #include <linux/irq.h>
49*4882a593Smuzhiyun #include <linux/msi.h>
50*4882a593Smuzhiyun #include <linux/hyperv.h>
51*4882a593Smuzhiyun #include <linux/refcount.h>
52*4882a593Smuzhiyun #include <asm/mshyperv.h>
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Protocol versions. The low word is the minor version, the high word the
56*4882a593Smuzhiyun * major version.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define PCI_MAKE_VERSION(major, minor) ((u32)(((major) << 16) | (minor)))
60*4882a593Smuzhiyun #define PCI_MAJOR_VERSION(version) ((u32)(version) >> 16)
61*4882a593Smuzhiyun #define PCI_MINOR_VERSION(version) ((u32)(version) & 0xff)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun enum pci_protocol_version_t {
64*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1), /* Win10 */
65*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_2 = PCI_MAKE_VERSION(1, 2), /* RS1 */
66*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_3 = PCI_MAKE_VERSION(1, 3), /* Vibranium */
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define CPU_AFFINITY_ALL -1ULL
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * Supported protocol versions in the order of probing - highest go
73*4882a593Smuzhiyun * first.
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun static enum pci_protocol_version_t pci_protocol_versions[] = {
76*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_3,
77*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_2,
78*4882a593Smuzhiyun PCI_PROTOCOL_VERSION_1_1,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define PCI_CONFIG_MMIO_LENGTH 0x2000
82*4882a593Smuzhiyun #define CFG_PAGE_OFFSET 0x1000
83*4882a593Smuzhiyun #define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define MAX_SUPPORTED_MSI_MESSAGES 0x400
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define STATUS_REVISION_MISMATCH 0xC0000059
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* space for 32bit serial number as string */
90*4882a593Smuzhiyun #define SLOT_NAME_SIZE 11
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Message Types
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun enum pci_message_type {
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * Version 1.1
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun PCI_MESSAGE_BASE = 0x42490000,
101*4882a593Smuzhiyun PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
102*4882a593Smuzhiyun PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
103*4882a593Smuzhiyun PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
104*4882a593Smuzhiyun PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
105*4882a593Smuzhiyun PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
106*4882a593Smuzhiyun PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
107*4882a593Smuzhiyun PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
108*4882a593Smuzhiyun PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
109*4882a593Smuzhiyun PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
110*4882a593Smuzhiyun PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
111*4882a593Smuzhiyun PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
112*4882a593Smuzhiyun PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
113*4882a593Smuzhiyun PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
114*4882a593Smuzhiyun PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
115*4882a593Smuzhiyun PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
116*4882a593Smuzhiyun PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
117*4882a593Smuzhiyun PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
118*4882a593Smuzhiyun PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
119*4882a593Smuzhiyun PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
120*4882a593Smuzhiyun PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
121*4882a593Smuzhiyun PCI_RESOURCES_ASSIGNED2 = PCI_MESSAGE_BASE + 0x16,
122*4882a593Smuzhiyun PCI_CREATE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x17,
123*4882a593Smuzhiyun PCI_DELETE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x18, /* unused */
124*4882a593Smuzhiyun PCI_BUS_RELATIONS2 = PCI_MESSAGE_BASE + 0x19,
125*4882a593Smuzhiyun PCI_MESSAGE_MAXIMUM
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /*
129*4882a593Smuzhiyun * Structures defining the virtual PCI Express protocol.
130*4882a593Smuzhiyun */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun union pci_version {
133*4882a593Smuzhiyun struct {
134*4882a593Smuzhiyun u16 minor_version;
135*4882a593Smuzhiyun u16 major_version;
136*4882a593Smuzhiyun } parts;
137*4882a593Smuzhiyun u32 version;
138*4882a593Smuzhiyun } __packed;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * Function numbers are 8-bits wide on Express, as interpreted through ARI,
142*4882a593Smuzhiyun * which is all this driver does. This representation is the one used in
143*4882a593Smuzhiyun * Windows, which is what is expected when sending this back and forth with
144*4882a593Smuzhiyun * the Hyper-V parent partition.
145*4882a593Smuzhiyun */
146*4882a593Smuzhiyun union win_slot_encoding {
147*4882a593Smuzhiyun struct {
148*4882a593Smuzhiyun u32 dev:5;
149*4882a593Smuzhiyun u32 func:3;
150*4882a593Smuzhiyun u32 reserved:24;
151*4882a593Smuzhiyun } bits;
152*4882a593Smuzhiyun u32 slot;
153*4882a593Smuzhiyun } __packed;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun * Pretty much as defined in the PCI Specifications.
157*4882a593Smuzhiyun */
158*4882a593Smuzhiyun struct pci_function_description {
159*4882a593Smuzhiyun u16 v_id; /* vendor ID */
160*4882a593Smuzhiyun u16 d_id; /* device ID */
161*4882a593Smuzhiyun u8 rev;
162*4882a593Smuzhiyun u8 prog_intf;
163*4882a593Smuzhiyun u8 subclass;
164*4882a593Smuzhiyun u8 base_class;
165*4882a593Smuzhiyun u32 subsystem_id;
166*4882a593Smuzhiyun union win_slot_encoding win_slot;
167*4882a593Smuzhiyun u32 ser; /* serial number */
168*4882a593Smuzhiyun } __packed;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun enum pci_device_description_flags {
171*4882a593Smuzhiyun HV_PCI_DEVICE_FLAG_NONE = 0x0,
172*4882a593Smuzhiyun HV_PCI_DEVICE_FLAG_NUMA_AFFINITY = 0x1,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun struct pci_function_description2 {
176*4882a593Smuzhiyun u16 v_id; /* vendor ID */
177*4882a593Smuzhiyun u16 d_id; /* device ID */
178*4882a593Smuzhiyun u8 rev;
179*4882a593Smuzhiyun u8 prog_intf;
180*4882a593Smuzhiyun u8 subclass;
181*4882a593Smuzhiyun u8 base_class;
182*4882a593Smuzhiyun u32 subsystem_id;
183*4882a593Smuzhiyun union win_slot_encoding win_slot;
184*4882a593Smuzhiyun u32 ser; /* serial number */
185*4882a593Smuzhiyun u32 flags;
186*4882a593Smuzhiyun u16 virtual_numa_node;
187*4882a593Smuzhiyun u16 reserved;
188*4882a593Smuzhiyun } __packed;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /**
191*4882a593Smuzhiyun * struct hv_msi_desc
192*4882a593Smuzhiyun * @vector: IDT entry
193*4882a593Smuzhiyun * @delivery_mode: As defined in Intel's Programmer's
194*4882a593Smuzhiyun * Reference Manual, Volume 3, Chapter 8.
195*4882a593Smuzhiyun * @vector_count: Number of contiguous entries in the
196*4882a593Smuzhiyun * Interrupt Descriptor Table that are
197*4882a593Smuzhiyun * occupied by this Message-Signaled
198*4882a593Smuzhiyun * Interrupt. For "MSI", as first defined
199*4882a593Smuzhiyun * in PCI 2.2, this can be between 1 and
200*4882a593Smuzhiyun * 32. For "MSI-X," as first defined in PCI
201*4882a593Smuzhiyun * 3.0, this must be 1, as each MSI-X table
202*4882a593Smuzhiyun * entry would have its own descriptor.
203*4882a593Smuzhiyun * @reserved: Empty space
204*4882a593Smuzhiyun * @cpu_mask: All the target virtual processors.
205*4882a593Smuzhiyun */
206*4882a593Smuzhiyun struct hv_msi_desc {
207*4882a593Smuzhiyun u8 vector;
208*4882a593Smuzhiyun u8 delivery_mode;
209*4882a593Smuzhiyun u16 vector_count;
210*4882a593Smuzhiyun u32 reserved;
211*4882a593Smuzhiyun u64 cpu_mask;
212*4882a593Smuzhiyun } __packed;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /**
215*4882a593Smuzhiyun * struct hv_msi_desc2 - 1.2 version of hv_msi_desc
216*4882a593Smuzhiyun * @vector: IDT entry
217*4882a593Smuzhiyun * @delivery_mode: As defined in Intel's Programmer's
218*4882a593Smuzhiyun * Reference Manual, Volume 3, Chapter 8.
219*4882a593Smuzhiyun * @vector_count: Number of contiguous entries in the
220*4882a593Smuzhiyun * Interrupt Descriptor Table that are
221*4882a593Smuzhiyun * occupied by this Message-Signaled
222*4882a593Smuzhiyun * Interrupt. For "MSI", as first defined
223*4882a593Smuzhiyun * in PCI 2.2, this can be between 1 and
224*4882a593Smuzhiyun * 32. For "MSI-X," as first defined in PCI
225*4882a593Smuzhiyun * 3.0, this must be 1, as each MSI-X table
226*4882a593Smuzhiyun * entry would have its own descriptor.
227*4882a593Smuzhiyun * @processor_count: number of bits enabled in array.
228*4882a593Smuzhiyun * @processor_array: All the target virtual processors.
229*4882a593Smuzhiyun */
230*4882a593Smuzhiyun struct hv_msi_desc2 {
231*4882a593Smuzhiyun u8 vector;
232*4882a593Smuzhiyun u8 delivery_mode;
233*4882a593Smuzhiyun u16 vector_count;
234*4882a593Smuzhiyun u16 processor_count;
235*4882a593Smuzhiyun u16 processor_array[32];
236*4882a593Smuzhiyun } __packed;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /**
239*4882a593Smuzhiyun * struct tran_int_desc
240*4882a593Smuzhiyun * @reserved: unused, padding
241*4882a593Smuzhiyun * @vector_count: same as in hv_msi_desc
242*4882a593Smuzhiyun * @data: This is the "data payload" value that is
243*4882a593Smuzhiyun * written by the device when it generates
244*4882a593Smuzhiyun * a message-signaled interrupt, either MSI
245*4882a593Smuzhiyun * or MSI-X.
246*4882a593Smuzhiyun * @address: This is the address to which the data
247*4882a593Smuzhiyun * payload is written on interrupt
248*4882a593Smuzhiyun * generation.
249*4882a593Smuzhiyun */
250*4882a593Smuzhiyun struct tran_int_desc {
251*4882a593Smuzhiyun u16 reserved;
252*4882a593Smuzhiyun u16 vector_count;
253*4882a593Smuzhiyun u32 data;
254*4882a593Smuzhiyun u64 address;
255*4882a593Smuzhiyun } __packed;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /*
258*4882a593Smuzhiyun * A generic message format for virtual PCI.
259*4882a593Smuzhiyun * Specific message formats are defined later in the file.
260*4882a593Smuzhiyun */
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun struct pci_message {
263*4882a593Smuzhiyun u32 type;
264*4882a593Smuzhiyun } __packed;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun struct pci_child_message {
267*4882a593Smuzhiyun struct pci_message message_type;
268*4882a593Smuzhiyun union win_slot_encoding wslot;
269*4882a593Smuzhiyun } __packed;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun struct pci_incoming_message {
272*4882a593Smuzhiyun struct vmpacket_descriptor hdr;
273*4882a593Smuzhiyun struct pci_message message_type;
274*4882a593Smuzhiyun } __packed;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun struct pci_response {
277*4882a593Smuzhiyun struct vmpacket_descriptor hdr;
278*4882a593Smuzhiyun s32 status; /* negative values are failures */
279*4882a593Smuzhiyun } __packed;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun struct pci_packet {
282*4882a593Smuzhiyun void (*completion_func)(void *context, struct pci_response *resp,
283*4882a593Smuzhiyun int resp_packet_size);
284*4882a593Smuzhiyun void *compl_ctxt;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun struct pci_message message[];
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /*
290*4882a593Smuzhiyun * Specific message types supporting the PCI protocol.
291*4882a593Smuzhiyun */
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /*
294*4882a593Smuzhiyun * Version negotiation message. Sent from the guest to the host.
295*4882a593Smuzhiyun * The guest is free to try different versions until the host
296*4882a593Smuzhiyun * accepts the version.
297*4882a593Smuzhiyun *
298*4882a593Smuzhiyun * pci_version: The protocol version requested.
299*4882a593Smuzhiyun * is_last_attempt: If TRUE, this is the last version guest will request.
300*4882a593Smuzhiyun * reservedz: Reserved field, set to zero.
301*4882a593Smuzhiyun */
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun struct pci_version_request {
304*4882a593Smuzhiyun struct pci_message message_type;
305*4882a593Smuzhiyun u32 protocol_version;
306*4882a593Smuzhiyun } __packed;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /*
309*4882a593Smuzhiyun * Bus D0 Entry. This is sent from the guest to the host when the virtual
310*4882a593Smuzhiyun * bus (PCI Express port) is ready for action.
311*4882a593Smuzhiyun */
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun struct pci_bus_d0_entry {
314*4882a593Smuzhiyun struct pci_message message_type;
315*4882a593Smuzhiyun u32 reserved;
316*4882a593Smuzhiyun u64 mmio_base;
317*4882a593Smuzhiyun } __packed;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun struct pci_bus_relations {
320*4882a593Smuzhiyun struct pci_incoming_message incoming;
321*4882a593Smuzhiyun u32 device_count;
322*4882a593Smuzhiyun struct pci_function_description func[];
323*4882a593Smuzhiyun } __packed;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun struct pci_bus_relations2 {
326*4882a593Smuzhiyun struct pci_incoming_message incoming;
327*4882a593Smuzhiyun u32 device_count;
328*4882a593Smuzhiyun struct pci_function_description2 func[];
329*4882a593Smuzhiyun } __packed;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun struct pci_q_res_req_response {
332*4882a593Smuzhiyun struct vmpacket_descriptor hdr;
333*4882a593Smuzhiyun s32 status; /* negative values are failures */
334*4882a593Smuzhiyun u32 probed_bar[PCI_STD_NUM_BARS];
335*4882a593Smuzhiyun } __packed;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun struct pci_set_power {
338*4882a593Smuzhiyun struct pci_message message_type;
339*4882a593Smuzhiyun union win_slot_encoding wslot;
340*4882a593Smuzhiyun u32 power_state; /* In Windows terms */
341*4882a593Smuzhiyun u32 reserved;
342*4882a593Smuzhiyun } __packed;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun struct pci_set_power_response {
345*4882a593Smuzhiyun struct vmpacket_descriptor hdr;
346*4882a593Smuzhiyun s32 status; /* negative values are failures */
347*4882a593Smuzhiyun union win_slot_encoding wslot;
348*4882a593Smuzhiyun u32 resultant_state; /* In Windows terms */
349*4882a593Smuzhiyun u32 reserved;
350*4882a593Smuzhiyun } __packed;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun struct pci_resources_assigned {
353*4882a593Smuzhiyun struct pci_message message_type;
354*4882a593Smuzhiyun union win_slot_encoding wslot;
355*4882a593Smuzhiyun u8 memory_range[0x14][6]; /* not used here */
356*4882a593Smuzhiyun u32 msi_descriptors;
357*4882a593Smuzhiyun u32 reserved[4];
358*4882a593Smuzhiyun } __packed;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun struct pci_resources_assigned2 {
361*4882a593Smuzhiyun struct pci_message message_type;
362*4882a593Smuzhiyun union win_slot_encoding wslot;
363*4882a593Smuzhiyun u8 memory_range[0x14][6]; /* not used here */
364*4882a593Smuzhiyun u32 msi_descriptor_count;
365*4882a593Smuzhiyun u8 reserved[70];
366*4882a593Smuzhiyun } __packed;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun struct pci_create_interrupt {
369*4882a593Smuzhiyun struct pci_message message_type;
370*4882a593Smuzhiyun union win_slot_encoding wslot;
371*4882a593Smuzhiyun struct hv_msi_desc int_desc;
372*4882a593Smuzhiyun } __packed;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun struct pci_create_int_response {
375*4882a593Smuzhiyun struct pci_response response;
376*4882a593Smuzhiyun u32 reserved;
377*4882a593Smuzhiyun struct tran_int_desc int_desc;
378*4882a593Smuzhiyun } __packed;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun struct pci_create_interrupt2 {
381*4882a593Smuzhiyun struct pci_message message_type;
382*4882a593Smuzhiyun union win_slot_encoding wslot;
383*4882a593Smuzhiyun struct hv_msi_desc2 int_desc;
384*4882a593Smuzhiyun } __packed;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun struct pci_delete_interrupt {
387*4882a593Smuzhiyun struct pci_message message_type;
388*4882a593Smuzhiyun union win_slot_encoding wslot;
389*4882a593Smuzhiyun struct tran_int_desc int_desc;
390*4882a593Smuzhiyun } __packed;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /*
393*4882a593Smuzhiyun * Note: the VM must pass a valid block id, wslot and bytes_requested.
394*4882a593Smuzhiyun */
395*4882a593Smuzhiyun struct pci_read_block {
396*4882a593Smuzhiyun struct pci_message message_type;
397*4882a593Smuzhiyun u32 block_id;
398*4882a593Smuzhiyun union win_slot_encoding wslot;
399*4882a593Smuzhiyun u32 bytes_requested;
400*4882a593Smuzhiyun } __packed;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun struct pci_read_block_response {
403*4882a593Smuzhiyun struct vmpacket_descriptor hdr;
404*4882a593Smuzhiyun u32 status;
405*4882a593Smuzhiyun u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
406*4882a593Smuzhiyun } __packed;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /*
409*4882a593Smuzhiyun * Note: the VM must pass a valid block id, wslot and byte_count.
410*4882a593Smuzhiyun */
411*4882a593Smuzhiyun struct pci_write_block {
412*4882a593Smuzhiyun struct pci_message message_type;
413*4882a593Smuzhiyun u32 block_id;
414*4882a593Smuzhiyun union win_slot_encoding wslot;
415*4882a593Smuzhiyun u32 byte_count;
416*4882a593Smuzhiyun u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
417*4882a593Smuzhiyun } __packed;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun struct pci_dev_inval_block {
420*4882a593Smuzhiyun struct pci_incoming_message incoming;
421*4882a593Smuzhiyun union win_slot_encoding wslot;
422*4882a593Smuzhiyun u64 block_mask;
423*4882a593Smuzhiyun } __packed;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun struct pci_dev_incoming {
426*4882a593Smuzhiyun struct pci_incoming_message incoming;
427*4882a593Smuzhiyun union win_slot_encoding wslot;
428*4882a593Smuzhiyun } __packed;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun struct pci_eject_response {
431*4882a593Smuzhiyun struct pci_message message_type;
432*4882a593Smuzhiyun union win_slot_encoding wslot;
433*4882a593Smuzhiyun u32 status;
434*4882a593Smuzhiyun } __packed;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun static int pci_ring_size = (4 * PAGE_SIZE);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun /*
439*4882a593Smuzhiyun * Driver specific state.
440*4882a593Smuzhiyun */
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun enum hv_pcibus_state {
443*4882a593Smuzhiyun hv_pcibus_init = 0,
444*4882a593Smuzhiyun hv_pcibus_probed,
445*4882a593Smuzhiyun hv_pcibus_installed,
446*4882a593Smuzhiyun hv_pcibus_removing,
447*4882a593Smuzhiyun hv_pcibus_maximum
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun struct hv_pcibus_device {
451*4882a593Smuzhiyun struct pci_sysdata sysdata;
452*4882a593Smuzhiyun /* Protocol version negotiated with the host */
453*4882a593Smuzhiyun enum pci_protocol_version_t protocol_version;
454*4882a593Smuzhiyun enum hv_pcibus_state state;
455*4882a593Smuzhiyun refcount_t remove_lock;
456*4882a593Smuzhiyun struct hv_device *hdev;
457*4882a593Smuzhiyun resource_size_t low_mmio_space;
458*4882a593Smuzhiyun resource_size_t high_mmio_space;
459*4882a593Smuzhiyun struct resource *mem_config;
460*4882a593Smuzhiyun struct resource *low_mmio_res;
461*4882a593Smuzhiyun struct resource *high_mmio_res;
462*4882a593Smuzhiyun struct completion *survey_event;
463*4882a593Smuzhiyun struct completion remove_event;
464*4882a593Smuzhiyun struct pci_bus *pci_bus;
465*4882a593Smuzhiyun spinlock_t config_lock; /* Avoid two threads writing index page */
466*4882a593Smuzhiyun spinlock_t device_list_lock; /* Protect lists below */
467*4882a593Smuzhiyun void __iomem *cfg_addr;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun struct list_head resources_for_children;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun struct list_head children;
472*4882a593Smuzhiyun struct list_head dr_list;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun struct msi_domain_info msi_info;
475*4882a593Smuzhiyun struct msi_controller msi_chip;
476*4882a593Smuzhiyun struct irq_domain *irq_domain;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun spinlock_t retarget_msi_interrupt_lock;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun struct workqueue_struct *wq;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /* Highest slot of child device with resources allocated */
483*4882a593Smuzhiyun int wslot_res_allocated;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* hypercall arg, must not cross page boundary */
486*4882a593Smuzhiyun struct hv_retarget_device_interrupt retarget_msi_interrupt_params;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /*
489*4882a593Smuzhiyun * Don't put anything here: retarget_msi_interrupt_params must be last
490*4882a593Smuzhiyun */
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /*
494*4882a593Smuzhiyun * Tracks "Device Relations" messages from the host, which must be both
495*4882a593Smuzhiyun * processed in order and deferred so that they don't run in the context
496*4882a593Smuzhiyun * of the incoming packet callback.
497*4882a593Smuzhiyun */
498*4882a593Smuzhiyun struct hv_dr_work {
499*4882a593Smuzhiyun struct work_struct wrk;
500*4882a593Smuzhiyun struct hv_pcibus_device *bus;
501*4882a593Smuzhiyun };
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun struct hv_pcidev_description {
504*4882a593Smuzhiyun u16 v_id; /* vendor ID */
505*4882a593Smuzhiyun u16 d_id; /* device ID */
506*4882a593Smuzhiyun u8 rev;
507*4882a593Smuzhiyun u8 prog_intf;
508*4882a593Smuzhiyun u8 subclass;
509*4882a593Smuzhiyun u8 base_class;
510*4882a593Smuzhiyun u32 subsystem_id;
511*4882a593Smuzhiyun union win_slot_encoding win_slot;
512*4882a593Smuzhiyun u32 ser; /* serial number */
513*4882a593Smuzhiyun u32 flags;
514*4882a593Smuzhiyun u16 virtual_numa_node;
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun struct hv_dr_state {
518*4882a593Smuzhiyun struct list_head list_entry;
519*4882a593Smuzhiyun u32 device_count;
520*4882a593Smuzhiyun struct hv_pcidev_description func[];
521*4882a593Smuzhiyun };
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun enum hv_pcichild_state {
524*4882a593Smuzhiyun hv_pcichild_init = 0,
525*4882a593Smuzhiyun hv_pcichild_requirements,
526*4882a593Smuzhiyun hv_pcichild_resourced,
527*4882a593Smuzhiyun hv_pcichild_ejecting,
528*4882a593Smuzhiyun hv_pcichild_maximum
529*4882a593Smuzhiyun };
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun struct hv_pci_dev {
532*4882a593Smuzhiyun /* List protected by pci_rescan_remove_lock */
533*4882a593Smuzhiyun struct list_head list_entry;
534*4882a593Smuzhiyun refcount_t refs;
535*4882a593Smuzhiyun enum hv_pcichild_state state;
536*4882a593Smuzhiyun struct pci_slot *pci_slot;
537*4882a593Smuzhiyun struct hv_pcidev_description desc;
538*4882a593Smuzhiyun bool reported_missing;
539*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
540*4882a593Smuzhiyun struct work_struct wrk;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun void (*block_invalidate)(void *context, u64 block_mask);
543*4882a593Smuzhiyun void *invalidate_context;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /*
546*4882a593Smuzhiyun * What would be observed if one wrote 0xFFFFFFFF to a BAR and then
547*4882a593Smuzhiyun * read it back, for each of the BAR offsets within config space.
548*4882a593Smuzhiyun */
549*4882a593Smuzhiyun u32 probed_bar[PCI_STD_NUM_BARS];
550*4882a593Smuzhiyun };
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun struct hv_pci_compl {
553*4882a593Smuzhiyun struct completion host_event;
554*4882a593Smuzhiyun s32 completion_status;
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun static void hv_pci_onchannelcallback(void *context);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun /**
560*4882a593Smuzhiyun * hv_pci_generic_compl() - Invoked for a completion packet
561*4882a593Smuzhiyun * @context: Set up by the sender of the packet.
562*4882a593Smuzhiyun * @resp: The response packet
563*4882a593Smuzhiyun * @resp_packet_size: Size in bytes of the packet
564*4882a593Smuzhiyun *
565*4882a593Smuzhiyun * This function is used to trigger an event and report status
566*4882a593Smuzhiyun * for any message for which the completion packet contains a
567*4882a593Smuzhiyun * status and nothing else.
568*4882a593Smuzhiyun */
hv_pci_generic_compl(void * context,struct pci_response * resp,int resp_packet_size)569*4882a593Smuzhiyun static void hv_pci_generic_compl(void *context, struct pci_response *resp,
570*4882a593Smuzhiyun int resp_packet_size)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun struct hv_pci_compl *comp_pkt = context;
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun if (resp_packet_size >= offsetofend(struct pci_response, status))
575*4882a593Smuzhiyun comp_pkt->completion_status = resp->status;
576*4882a593Smuzhiyun else
577*4882a593Smuzhiyun comp_pkt->completion_status = -1;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun complete(&comp_pkt->host_event);
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
583*4882a593Smuzhiyun u32 wslot);
584*4882a593Smuzhiyun
get_pcichild(struct hv_pci_dev * hpdev)585*4882a593Smuzhiyun static void get_pcichild(struct hv_pci_dev *hpdev)
586*4882a593Smuzhiyun {
587*4882a593Smuzhiyun refcount_inc(&hpdev->refs);
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun
put_pcichild(struct hv_pci_dev * hpdev)590*4882a593Smuzhiyun static void put_pcichild(struct hv_pci_dev *hpdev)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun if (refcount_dec_and_test(&hpdev->refs))
593*4882a593Smuzhiyun kfree(hpdev);
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun static void get_hvpcibus(struct hv_pcibus_device *hv_pcibus);
597*4882a593Smuzhiyun static void put_hvpcibus(struct hv_pcibus_device *hv_pcibus);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /*
600*4882a593Smuzhiyun * There is no good way to get notified from vmbus_onoffer_rescind(),
601*4882a593Smuzhiyun * so let's use polling here, since this is not a hot path.
602*4882a593Smuzhiyun */
wait_for_response(struct hv_device * hdev,struct completion * comp)603*4882a593Smuzhiyun static int wait_for_response(struct hv_device *hdev,
604*4882a593Smuzhiyun struct completion *comp)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun while (true) {
607*4882a593Smuzhiyun if (hdev->channel->rescind) {
608*4882a593Smuzhiyun dev_warn_once(&hdev->device, "The device is gone.\n");
609*4882a593Smuzhiyun return -ENODEV;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun if (wait_for_completion_timeout(comp, HZ / 10))
613*4882a593Smuzhiyun break;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun /**
620*4882a593Smuzhiyun * devfn_to_wslot() - Convert from Linux PCI slot to Windows
621*4882a593Smuzhiyun * @devfn: The Linux representation of PCI slot
622*4882a593Smuzhiyun *
623*4882a593Smuzhiyun * Windows uses a slightly different representation of PCI slot.
624*4882a593Smuzhiyun *
625*4882a593Smuzhiyun * Return: The Windows representation
626*4882a593Smuzhiyun */
devfn_to_wslot(int devfn)627*4882a593Smuzhiyun static u32 devfn_to_wslot(int devfn)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun union win_slot_encoding wslot;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun wslot.slot = 0;
632*4882a593Smuzhiyun wslot.bits.dev = PCI_SLOT(devfn);
633*4882a593Smuzhiyun wslot.bits.func = PCI_FUNC(devfn);
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun return wslot.slot;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /**
639*4882a593Smuzhiyun * wslot_to_devfn() - Convert from Windows PCI slot to Linux
640*4882a593Smuzhiyun * @wslot: The Windows representation of PCI slot
641*4882a593Smuzhiyun *
642*4882a593Smuzhiyun * Windows uses a slightly different representation of PCI slot.
643*4882a593Smuzhiyun *
644*4882a593Smuzhiyun * Return: The Linux representation
645*4882a593Smuzhiyun */
wslot_to_devfn(u32 wslot)646*4882a593Smuzhiyun static int wslot_to_devfn(u32 wslot)
647*4882a593Smuzhiyun {
648*4882a593Smuzhiyun union win_slot_encoding slot_no;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun slot_no.slot = wslot;
651*4882a593Smuzhiyun return PCI_DEVFN(slot_no.bits.dev, slot_no.bits.func);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun /*
655*4882a593Smuzhiyun * PCI Configuration Space for these root PCI buses is implemented as a pair
656*4882a593Smuzhiyun * of pages in memory-mapped I/O space. Writing to the first page chooses
657*4882a593Smuzhiyun * the PCI function being written or read. Once the first page has been
658*4882a593Smuzhiyun * written to, the following page maps in the entire configuration space of
659*4882a593Smuzhiyun * the function.
660*4882a593Smuzhiyun */
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun /**
663*4882a593Smuzhiyun * _hv_pcifront_read_config() - Internal PCI config read
664*4882a593Smuzhiyun * @hpdev: The PCI driver's representation of the device
665*4882a593Smuzhiyun * @where: Offset within config space
666*4882a593Smuzhiyun * @size: Size of the transfer
667*4882a593Smuzhiyun * @val: Pointer to the buffer receiving the data
668*4882a593Smuzhiyun */
_hv_pcifront_read_config(struct hv_pci_dev * hpdev,int where,int size,u32 * val)669*4882a593Smuzhiyun static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where,
670*4882a593Smuzhiyun int size, u32 *val)
671*4882a593Smuzhiyun {
672*4882a593Smuzhiyun unsigned long flags;
673*4882a593Smuzhiyun void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /*
676*4882a593Smuzhiyun * If the attempt is to read the IDs or the ROM BAR, simulate that.
677*4882a593Smuzhiyun */
678*4882a593Smuzhiyun if (where + size <= PCI_COMMAND) {
679*4882a593Smuzhiyun memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size);
680*4882a593Smuzhiyun } else if (where >= PCI_CLASS_REVISION && where + size <=
681*4882a593Smuzhiyun PCI_CACHE_LINE_SIZE) {
682*4882a593Smuzhiyun memcpy(val, ((u8 *)&hpdev->desc.rev) + where -
683*4882a593Smuzhiyun PCI_CLASS_REVISION, size);
684*4882a593Smuzhiyun } else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where + size <=
685*4882a593Smuzhiyun PCI_ROM_ADDRESS) {
686*4882a593Smuzhiyun memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where -
687*4882a593Smuzhiyun PCI_SUBSYSTEM_VENDOR_ID, size);
688*4882a593Smuzhiyun } else if (where >= PCI_ROM_ADDRESS && where + size <=
689*4882a593Smuzhiyun PCI_CAPABILITY_LIST) {
690*4882a593Smuzhiyun /* ROM BARs are unimplemented */
691*4882a593Smuzhiyun *val = 0;
692*4882a593Smuzhiyun } else if (where >= PCI_INTERRUPT_LINE && where + size <=
693*4882a593Smuzhiyun PCI_INTERRUPT_PIN) {
694*4882a593Smuzhiyun /*
695*4882a593Smuzhiyun * Interrupt Line and Interrupt PIN are hard-wired to zero
696*4882a593Smuzhiyun * because this front-end only supports message-signaled
697*4882a593Smuzhiyun * interrupts.
698*4882a593Smuzhiyun */
699*4882a593Smuzhiyun *val = 0;
700*4882a593Smuzhiyun } else if (where + size <= CFG_PAGE_SIZE) {
701*4882a593Smuzhiyun spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
702*4882a593Smuzhiyun /* Choose the function to be read. (See comment above) */
703*4882a593Smuzhiyun writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
704*4882a593Smuzhiyun /* Make sure the function was chosen before we start reading. */
705*4882a593Smuzhiyun mb();
706*4882a593Smuzhiyun /* Read from that function's config space. */
707*4882a593Smuzhiyun switch (size) {
708*4882a593Smuzhiyun case 1:
709*4882a593Smuzhiyun *val = readb(addr);
710*4882a593Smuzhiyun break;
711*4882a593Smuzhiyun case 2:
712*4882a593Smuzhiyun *val = readw(addr);
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun default:
715*4882a593Smuzhiyun *val = readl(addr);
716*4882a593Smuzhiyun break;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun /*
719*4882a593Smuzhiyun * Make sure the read was done before we release the spinlock
720*4882a593Smuzhiyun * allowing consecutive reads/writes.
721*4882a593Smuzhiyun */
722*4882a593Smuzhiyun mb();
723*4882a593Smuzhiyun spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
724*4882a593Smuzhiyun } else {
725*4882a593Smuzhiyun dev_err(&hpdev->hbus->hdev->device,
726*4882a593Smuzhiyun "Attempt to read beyond a function's config space.\n");
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun
hv_pcifront_get_vendor_id(struct hv_pci_dev * hpdev)730*4882a593Smuzhiyun static u16 hv_pcifront_get_vendor_id(struct hv_pci_dev *hpdev)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun u16 ret;
733*4882a593Smuzhiyun unsigned long flags;
734*4882a593Smuzhiyun void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET +
735*4882a593Smuzhiyun PCI_VENDOR_ID;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun /* Choose the function to be read. (See comment above) */
740*4882a593Smuzhiyun writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
741*4882a593Smuzhiyun /* Make sure the function was chosen before we start reading. */
742*4882a593Smuzhiyun mb();
743*4882a593Smuzhiyun /* Read from that function's config space. */
744*4882a593Smuzhiyun ret = readw(addr);
745*4882a593Smuzhiyun /*
746*4882a593Smuzhiyun * mb() is not required here, because the spin_unlock_irqrestore()
747*4882a593Smuzhiyun * is a barrier.
748*4882a593Smuzhiyun */
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun return ret;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun /**
756*4882a593Smuzhiyun * _hv_pcifront_write_config() - Internal PCI config write
757*4882a593Smuzhiyun * @hpdev: The PCI driver's representation of the device
758*4882a593Smuzhiyun * @where: Offset within config space
759*4882a593Smuzhiyun * @size: Size of the transfer
760*4882a593Smuzhiyun * @val: The data being transferred
761*4882a593Smuzhiyun */
_hv_pcifront_write_config(struct hv_pci_dev * hpdev,int where,int size,u32 val)762*4882a593Smuzhiyun static void _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where,
763*4882a593Smuzhiyun int size, u32 val)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun unsigned long flags;
766*4882a593Smuzhiyun void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun if (where >= PCI_SUBSYSTEM_VENDOR_ID &&
769*4882a593Smuzhiyun where + size <= PCI_CAPABILITY_LIST) {
770*4882a593Smuzhiyun /* SSIDs and ROM BARs are read-only */
771*4882a593Smuzhiyun } else if (where >= PCI_COMMAND && where + size <= CFG_PAGE_SIZE) {
772*4882a593Smuzhiyun spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
773*4882a593Smuzhiyun /* Choose the function to be written. (See comment above) */
774*4882a593Smuzhiyun writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
775*4882a593Smuzhiyun /* Make sure the function was chosen before we start writing. */
776*4882a593Smuzhiyun wmb();
777*4882a593Smuzhiyun /* Write to that function's config space. */
778*4882a593Smuzhiyun switch (size) {
779*4882a593Smuzhiyun case 1:
780*4882a593Smuzhiyun writeb(val, addr);
781*4882a593Smuzhiyun break;
782*4882a593Smuzhiyun case 2:
783*4882a593Smuzhiyun writew(val, addr);
784*4882a593Smuzhiyun break;
785*4882a593Smuzhiyun default:
786*4882a593Smuzhiyun writel(val, addr);
787*4882a593Smuzhiyun break;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun /*
790*4882a593Smuzhiyun * Make sure the write was done before we release the spinlock
791*4882a593Smuzhiyun * allowing consecutive reads/writes.
792*4882a593Smuzhiyun */
793*4882a593Smuzhiyun mb();
794*4882a593Smuzhiyun spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
795*4882a593Smuzhiyun } else {
796*4882a593Smuzhiyun dev_err(&hpdev->hbus->hdev->device,
797*4882a593Smuzhiyun "Attempt to write beyond a function's config space.\n");
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun /**
802*4882a593Smuzhiyun * hv_pcifront_read_config() - Read configuration space
803*4882a593Smuzhiyun * @bus: PCI Bus structure
804*4882a593Smuzhiyun * @devfn: Device/function
805*4882a593Smuzhiyun * @where: Offset from base
806*4882a593Smuzhiyun * @size: Byte/word/dword
807*4882a593Smuzhiyun * @val: Value to be read
808*4882a593Smuzhiyun *
809*4882a593Smuzhiyun * Return: PCIBIOS_SUCCESSFUL on success
810*4882a593Smuzhiyun * PCIBIOS_DEVICE_NOT_FOUND on failure
811*4882a593Smuzhiyun */
hv_pcifront_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)812*4882a593Smuzhiyun static int hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn,
813*4882a593Smuzhiyun int where, int size, u32 *val)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun struct hv_pcibus_device *hbus =
816*4882a593Smuzhiyun container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
817*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
820*4882a593Smuzhiyun if (!hpdev)
821*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun _hv_pcifront_read_config(hpdev, where, size, val);
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun put_pcichild(hpdev);
826*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /**
830*4882a593Smuzhiyun * hv_pcifront_write_config() - Write configuration space
831*4882a593Smuzhiyun * @bus: PCI Bus structure
832*4882a593Smuzhiyun * @devfn: Device/function
833*4882a593Smuzhiyun * @where: Offset from base
834*4882a593Smuzhiyun * @size: Byte/word/dword
835*4882a593Smuzhiyun * @val: Value to be written to device
836*4882a593Smuzhiyun *
837*4882a593Smuzhiyun * Return: PCIBIOS_SUCCESSFUL on success
838*4882a593Smuzhiyun * PCIBIOS_DEVICE_NOT_FOUND on failure
839*4882a593Smuzhiyun */
hv_pcifront_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)840*4882a593Smuzhiyun static int hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn,
841*4882a593Smuzhiyun int where, int size, u32 val)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun struct hv_pcibus_device *hbus =
844*4882a593Smuzhiyun container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
845*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
848*4882a593Smuzhiyun if (!hpdev)
849*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev, where, size, val);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun put_pcichild(hpdev);
854*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun /* PCIe operations */
858*4882a593Smuzhiyun static struct pci_ops hv_pcifront_ops = {
859*4882a593Smuzhiyun .read = hv_pcifront_read_config,
860*4882a593Smuzhiyun .write = hv_pcifront_write_config,
861*4882a593Smuzhiyun };
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /*
864*4882a593Smuzhiyun * Paravirtual backchannel
865*4882a593Smuzhiyun *
866*4882a593Smuzhiyun * Hyper-V SR-IOV provides a backchannel mechanism in software for
867*4882a593Smuzhiyun * communication between a VF driver and a PF driver. These
868*4882a593Smuzhiyun * "configuration blocks" are similar in concept to PCI configuration space,
869*4882a593Smuzhiyun * but instead of doing reads and writes in 32-bit chunks through a very slow
870*4882a593Smuzhiyun * path, packets of up to 128 bytes can be sent or received asynchronously.
871*4882a593Smuzhiyun *
872*4882a593Smuzhiyun * Nearly every SR-IOV device contains just such a communications channel in
873*4882a593Smuzhiyun * hardware, so using this one in software is usually optional. Using the
874*4882a593Smuzhiyun * software channel, however, allows driver implementers to leverage software
875*4882a593Smuzhiyun * tools that fuzz the communications channel looking for vulnerabilities.
876*4882a593Smuzhiyun *
877*4882a593Smuzhiyun * The usage model for these packets puts the responsibility for reading or
878*4882a593Smuzhiyun * writing on the VF driver. The VF driver sends a read or a write packet,
879*4882a593Smuzhiyun * indicating which "block" is being referred to by number.
880*4882a593Smuzhiyun *
881*4882a593Smuzhiyun * If the PF driver wishes to initiate communication, it can "invalidate" one or
882*4882a593Smuzhiyun * more of the first 64 blocks. This invalidation is delivered via a callback
883*4882a593Smuzhiyun * supplied by the VF driver by this driver.
884*4882a593Smuzhiyun *
885*4882a593Smuzhiyun * No protocol is implied, except that supplied by the PF and VF drivers.
886*4882a593Smuzhiyun */
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun struct hv_read_config_compl {
889*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
890*4882a593Smuzhiyun void *buf;
891*4882a593Smuzhiyun unsigned int len;
892*4882a593Smuzhiyun unsigned int bytes_returned;
893*4882a593Smuzhiyun };
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun /**
896*4882a593Smuzhiyun * hv_pci_read_config_compl() - Invoked when a response packet
897*4882a593Smuzhiyun * for a read config block operation arrives.
898*4882a593Smuzhiyun * @context: Identifies the read config operation
899*4882a593Smuzhiyun * @resp: The response packet itself
900*4882a593Smuzhiyun * @resp_packet_size: Size in bytes of the response packet
901*4882a593Smuzhiyun */
hv_pci_read_config_compl(void * context,struct pci_response * resp,int resp_packet_size)902*4882a593Smuzhiyun static void hv_pci_read_config_compl(void *context, struct pci_response *resp,
903*4882a593Smuzhiyun int resp_packet_size)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun struct hv_read_config_compl *comp = context;
906*4882a593Smuzhiyun struct pci_read_block_response *read_resp =
907*4882a593Smuzhiyun (struct pci_read_block_response *)resp;
908*4882a593Smuzhiyun unsigned int data_len, hdr_len;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun hdr_len = offsetof(struct pci_read_block_response, bytes);
911*4882a593Smuzhiyun if (resp_packet_size < hdr_len) {
912*4882a593Smuzhiyun comp->comp_pkt.completion_status = -1;
913*4882a593Smuzhiyun goto out;
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun data_len = resp_packet_size - hdr_len;
917*4882a593Smuzhiyun if (data_len > 0 && read_resp->status == 0) {
918*4882a593Smuzhiyun comp->bytes_returned = min(comp->len, data_len);
919*4882a593Smuzhiyun memcpy(comp->buf, read_resp->bytes, comp->bytes_returned);
920*4882a593Smuzhiyun } else {
921*4882a593Smuzhiyun comp->bytes_returned = 0;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun comp->comp_pkt.completion_status = read_resp->status;
925*4882a593Smuzhiyun out:
926*4882a593Smuzhiyun complete(&comp->comp_pkt.host_event);
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun /**
930*4882a593Smuzhiyun * hv_read_config_block() - Sends a read config block request to
931*4882a593Smuzhiyun * the back-end driver running in the Hyper-V parent partition.
932*4882a593Smuzhiyun * @pdev: The PCI driver's representation for this device.
933*4882a593Smuzhiyun * @buf: Buffer into which the config block will be copied.
934*4882a593Smuzhiyun * @len: Size in bytes of buf.
935*4882a593Smuzhiyun * @block_id: Identifies the config block which has been requested.
936*4882a593Smuzhiyun * @bytes_returned: Size which came back from the back-end driver.
937*4882a593Smuzhiyun *
938*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
939*4882a593Smuzhiyun */
hv_read_config_block(struct pci_dev * pdev,void * buf,unsigned int len,unsigned int block_id,unsigned int * bytes_returned)940*4882a593Smuzhiyun static int hv_read_config_block(struct pci_dev *pdev, void *buf,
941*4882a593Smuzhiyun unsigned int len, unsigned int block_id,
942*4882a593Smuzhiyun unsigned int *bytes_returned)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun struct hv_pcibus_device *hbus =
945*4882a593Smuzhiyun container_of(pdev->bus->sysdata, struct hv_pcibus_device,
946*4882a593Smuzhiyun sysdata);
947*4882a593Smuzhiyun struct {
948*4882a593Smuzhiyun struct pci_packet pkt;
949*4882a593Smuzhiyun char buf[sizeof(struct pci_read_block)];
950*4882a593Smuzhiyun } pkt;
951*4882a593Smuzhiyun struct hv_read_config_compl comp_pkt;
952*4882a593Smuzhiyun struct pci_read_block *read_blk;
953*4882a593Smuzhiyun int ret;
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
956*4882a593Smuzhiyun return -EINVAL;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun init_completion(&comp_pkt.comp_pkt.host_event);
959*4882a593Smuzhiyun comp_pkt.buf = buf;
960*4882a593Smuzhiyun comp_pkt.len = len;
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun memset(&pkt, 0, sizeof(pkt));
963*4882a593Smuzhiyun pkt.pkt.completion_func = hv_pci_read_config_compl;
964*4882a593Smuzhiyun pkt.pkt.compl_ctxt = &comp_pkt;
965*4882a593Smuzhiyun read_blk = (struct pci_read_block *)&pkt.pkt.message;
966*4882a593Smuzhiyun read_blk->message_type.type = PCI_READ_BLOCK;
967*4882a593Smuzhiyun read_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
968*4882a593Smuzhiyun read_blk->block_id = block_id;
969*4882a593Smuzhiyun read_blk->bytes_requested = len;
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun ret = vmbus_sendpacket(hbus->hdev->channel, read_blk,
972*4882a593Smuzhiyun sizeof(*read_blk), (unsigned long)&pkt.pkt,
973*4882a593Smuzhiyun VM_PKT_DATA_INBAND,
974*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
975*4882a593Smuzhiyun if (ret)
976*4882a593Smuzhiyun return ret;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun ret = wait_for_response(hbus->hdev, &comp_pkt.comp_pkt.host_event);
979*4882a593Smuzhiyun if (ret)
980*4882a593Smuzhiyun return ret;
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun if (comp_pkt.comp_pkt.completion_status != 0 ||
983*4882a593Smuzhiyun comp_pkt.bytes_returned == 0) {
984*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
985*4882a593Smuzhiyun "Read Config Block failed: 0x%x, bytes_returned=%d\n",
986*4882a593Smuzhiyun comp_pkt.comp_pkt.completion_status,
987*4882a593Smuzhiyun comp_pkt.bytes_returned);
988*4882a593Smuzhiyun return -EIO;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun *bytes_returned = comp_pkt.bytes_returned;
992*4882a593Smuzhiyun return 0;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun /**
996*4882a593Smuzhiyun * hv_pci_write_config_compl() - Invoked when a response packet for a write
997*4882a593Smuzhiyun * config block operation arrives.
998*4882a593Smuzhiyun * @context: Identifies the write config operation
999*4882a593Smuzhiyun * @resp: The response packet itself
1000*4882a593Smuzhiyun * @resp_packet_size: Size in bytes of the response packet
1001*4882a593Smuzhiyun */
hv_pci_write_config_compl(void * context,struct pci_response * resp,int resp_packet_size)1002*4882a593Smuzhiyun static void hv_pci_write_config_compl(void *context, struct pci_response *resp,
1003*4882a593Smuzhiyun int resp_packet_size)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun struct hv_pci_compl *comp_pkt = context;
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun comp_pkt->completion_status = resp->status;
1008*4882a593Smuzhiyun complete(&comp_pkt->host_event);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun /**
1012*4882a593Smuzhiyun * hv_write_config_block() - Sends a write config block request to the
1013*4882a593Smuzhiyun * back-end driver running in the Hyper-V parent partition.
1014*4882a593Smuzhiyun * @pdev: The PCI driver's representation for this device.
1015*4882a593Smuzhiyun * @buf: Buffer from which the config block will be copied.
1016*4882a593Smuzhiyun * @len: Size in bytes of buf.
1017*4882a593Smuzhiyun * @block_id: Identifies the config block which is being written.
1018*4882a593Smuzhiyun *
1019*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
1020*4882a593Smuzhiyun */
hv_write_config_block(struct pci_dev * pdev,void * buf,unsigned int len,unsigned int block_id)1021*4882a593Smuzhiyun static int hv_write_config_block(struct pci_dev *pdev, void *buf,
1022*4882a593Smuzhiyun unsigned int len, unsigned int block_id)
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun struct hv_pcibus_device *hbus =
1025*4882a593Smuzhiyun container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1026*4882a593Smuzhiyun sysdata);
1027*4882a593Smuzhiyun struct {
1028*4882a593Smuzhiyun struct pci_packet pkt;
1029*4882a593Smuzhiyun char buf[sizeof(struct pci_write_block)];
1030*4882a593Smuzhiyun u32 reserved;
1031*4882a593Smuzhiyun } pkt;
1032*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
1033*4882a593Smuzhiyun struct pci_write_block *write_blk;
1034*4882a593Smuzhiyun u32 pkt_size;
1035*4882a593Smuzhiyun int ret;
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
1038*4882a593Smuzhiyun return -EINVAL;
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun memset(&pkt, 0, sizeof(pkt));
1043*4882a593Smuzhiyun pkt.pkt.completion_func = hv_pci_write_config_compl;
1044*4882a593Smuzhiyun pkt.pkt.compl_ctxt = &comp_pkt;
1045*4882a593Smuzhiyun write_blk = (struct pci_write_block *)&pkt.pkt.message;
1046*4882a593Smuzhiyun write_blk->message_type.type = PCI_WRITE_BLOCK;
1047*4882a593Smuzhiyun write_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
1048*4882a593Smuzhiyun write_blk->block_id = block_id;
1049*4882a593Smuzhiyun write_blk->byte_count = len;
1050*4882a593Smuzhiyun memcpy(write_blk->bytes, buf, len);
1051*4882a593Smuzhiyun pkt_size = offsetof(struct pci_write_block, bytes) + len;
1052*4882a593Smuzhiyun /*
1053*4882a593Smuzhiyun * This quirk is required on some hosts shipped around 2018, because
1054*4882a593Smuzhiyun * these hosts don't check the pkt_size correctly (new hosts have been
1055*4882a593Smuzhiyun * fixed since early 2019). The quirk is also safe on very old hosts
1056*4882a593Smuzhiyun * and new hosts, because, on them, what really matters is the length
1057*4882a593Smuzhiyun * specified in write_blk->byte_count.
1058*4882a593Smuzhiyun */
1059*4882a593Smuzhiyun pkt_size += sizeof(pkt.reserved);
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun ret = vmbus_sendpacket(hbus->hdev->channel, write_blk, pkt_size,
1062*4882a593Smuzhiyun (unsigned long)&pkt.pkt, VM_PKT_DATA_INBAND,
1063*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1064*4882a593Smuzhiyun if (ret)
1065*4882a593Smuzhiyun return ret;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun ret = wait_for_response(hbus->hdev, &comp_pkt.host_event);
1068*4882a593Smuzhiyun if (ret)
1069*4882a593Smuzhiyun return ret;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun if (comp_pkt.completion_status != 0) {
1072*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1073*4882a593Smuzhiyun "Write Config Block failed: 0x%x\n",
1074*4882a593Smuzhiyun comp_pkt.completion_status);
1075*4882a593Smuzhiyun return -EIO;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun return 0;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun /**
1082*4882a593Smuzhiyun * hv_register_block_invalidate() - Invoked when a config block invalidation
1083*4882a593Smuzhiyun * arrives from the back-end driver.
1084*4882a593Smuzhiyun * @pdev: The PCI driver's representation for this device.
1085*4882a593Smuzhiyun * @context: Identifies the device.
1086*4882a593Smuzhiyun * @block_invalidate: Identifies all of the blocks being invalidated.
1087*4882a593Smuzhiyun *
1088*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
1089*4882a593Smuzhiyun */
hv_register_block_invalidate(struct pci_dev * pdev,void * context,void (* block_invalidate)(void * context,u64 block_mask))1090*4882a593Smuzhiyun static int hv_register_block_invalidate(struct pci_dev *pdev, void *context,
1091*4882a593Smuzhiyun void (*block_invalidate)(void *context,
1092*4882a593Smuzhiyun u64 block_mask))
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun struct hv_pcibus_device *hbus =
1095*4882a593Smuzhiyun container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1096*4882a593Smuzhiyun sysdata);
1097*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1100*4882a593Smuzhiyun if (!hpdev)
1101*4882a593Smuzhiyun return -ENODEV;
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun hpdev->block_invalidate = block_invalidate;
1104*4882a593Smuzhiyun hpdev->invalidate_context = context;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun put_pcichild(hpdev);
1107*4882a593Smuzhiyun return 0;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun /* Interrupt management hooks */
hv_int_desc_free(struct hv_pci_dev * hpdev,struct tran_int_desc * int_desc)1112*4882a593Smuzhiyun static void hv_int_desc_free(struct hv_pci_dev *hpdev,
1113*4882a593Smuzhiyun struct tran_int_desc *int_desc)
1114*4882a593Smuzhiyun {
1115*4882a593Smuzhiyun struct pci_delete_interrupt *int_pkt;
1116*4882a593Smuzhiyun struct {
1117*4882a593Smuzhiyun struct pci_packet pkt;
1118*4882a593Smuzhiyun u8 buffer[sizeof(struct pci_delete_interrupt)];
1119*4882a593Smuzhiyun } ctxt;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun if (!int_desc->vector_count) {
1122*4882a593Smuzhiyun kfree(int_desc);
1123*4882a593Smuzhiyun return;
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun memset(&ctxt, 0, sizeof(ctxt));
1126*4882a593Smuzhiyun int_pkt = (struct pci_delete_interrupt *)&ctxt.pkt.message;
1127*4882a593Smuzhiyun int_pkt->message_type.type =
1128*4882a593Smuzhiyun PCI_DELETE_INTERRUPT_MESSAGE;
1129*4882a593Smuzhiyun int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
1130*4882a593Smuzhiyun int_pkt->int_desc = *int_desc;
1131*4882a593Smuzhiyun vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt, sizeof(*int_pkt),
1132*4882a593Smuzhiyun (unsigned long)&ctxt.pkt, VM_PKT_DATA_INBAND, 0);
1133*4882a593Smuzhiyun kfree(int_desc);
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /**
1137*4882a593Smuzhiyun * hv_msi_free() - Free the MSI.
1138*4882a593Smuzhiyun * @domain: The interrupt domain pointer
1139*4882a593Smuzhiyun * @info: Extra MSI-related context
1140*4882a593Smuzhiyun * @irq: Identifies the IRQ.
1141*4882a593Smuzhiyun *
1142*4882a593Smuzhiyun * The Hyper-V parent partition and hypervisor are tracking the
1143*4882a593Smuzhiyun * messages that are in use, keeping the interrupt redirection
1144*4882a593Smuzhiyun * table up to date. This callback sends a message that frees
1145*4882a593Smuzhiyun * the IRT entry and related tracking nonsense.
1146*4882a593Smuzhiyun */
hv_msi_free(struct irq_domain * domain,struct msi_domain_info * info,unsigned int irq)1147*4882a593Smuzhiyun static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
1148*4882a593Smuzhiyun unsigned int irq)
1149*4882a593Smuzhiyun {
1150*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
1151*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1152*4882a593Smuzhiyun struct pci_dev *pdev;
1153*4882a593Smuzhiyun struct tran_int_desc *int_desc;
1154*4882a593Smuzhiyun struct irq_data *irq_data = irq_domain_get_irq_data(domain, irq);
1155*4882a593Smuzhiyun struct msi_desc *msi = irq_data_get_msi_desc(irq_data);
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun pdev = msi_desc_to_pci_dev(msi);
1158*4882a593Smuzhiyun hbus = info->data;
1159*4882a593Smuzhiyun int_desc = irq_data_get_irq_chip_data(irq_data);
1160*4882a593Smuzhiyun if (!int_desc)
1161*4882a593Smuzhiyun return;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun irq_data->chip_data = NULL;
1164*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1165*4882a593Smuzhiyun if (!hpdev) {
1166*4882a593Smuzhiyun kfree(int_desc);
1167*4882a593Smuzhiyun return;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun hv_int_desc_free(hpdev, int_desc);
1171*4882a593Smuzhiyun put_pcichild(hpdev);
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun
hv_set_affinity(struct irq_data * data,const struct cpumask * dest,bool force)1174*4882a593Smuzhiyun static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
1175*4882a593Smuzhiyun bool force)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun struct irq_data *parent = data->parent_data;
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun return parent->chip->irq_set_affinity(parent, dest, force);
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun
hv_irq_mask(struct irq_data * data)1182*4882a593Smuzhiyun static void hv_irq_mask(struct irq_data *data)
1183*4882a593Smuzhiyun {
1184*4882a593Smuzhiyun pci_msi_mask_irq(data);
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
hv_msi_get_int_vector(struct irq_data * data)1187*4882a593Smuzhiyun static unsigned int hv_msi_get_int_vector(struct irq_data *data)
1188*4882a593Smuzhiyun {
1189*4882a593Smuzhiyun struct irq_cfg *cfg = irqd_cfg(data);
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun return cfg->vector;
1192*4882a593Smuzhiyun }
1193*4882a593Smuzhiyun
hv_msi_prepare(struct irq_domain * domain,struct device * dev,int nvec,msi_alloc_info_t * info)1194*4882a593Smuzhiyun static int hv_msi_prepare(struct irq_domain *domain, struct device *dev,
1195*4882a593Smuzhiyun int nvec, msi_alloc_info_t *info)
1196*4882a593Smuzhiyun {
1197*4882a593Smuzhiyun int ret = pci_msi_prepare(domain, dev, nvec, info);
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun /*
1200*4882a593Smuzhiyun * By using the interrupt remapper in the hypervisor IOMMU, contiguous
1201*4882a593Smuzhiyun * CPU vectors is not needed for multi-MSI
1202*4882a593Smuzhiyun */
1203*4882a593Smuzhiyun if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
1204*4882a593Smuzhiyun info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun return ret;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun /**
1210*4882a593Smuzhiyun * hv_irq_unmask() - "Unmask" the IRQ by setting its current
1211*4882a593Smuzhiyun * affinity.
1212*4882a593Smuzhiyun * @data: Describes the IRQ
1213*4882a593Smuzhiyun *
1214*4882a593Smuzhiyun * Build new a destination for the MSI and make a hypercall to
1215*4882a593Smuzhiyun * update the Interrupt Redirection Table. "Device Logical ID"
1216*4882a593Smuzhiyun * is built out of this PCI bus's instance GUID and the function
1217*4882a593Smuzhiyun * number of the device.
1218*4882a593Smuzhiyun */
hv_irq_unmask(struct irq_data * data)1219*4882a593Smuzhiyun static void hv_irq_unmask(struct irq_data *data)
1220*4882a593Smuzhiyun {
1221*4882a593Smuzhiyun struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
1222*4882a593Smuzhiyun struct irq_cfg *cfg = irqd_cfg(data);
1223*4882a593Smuzhiyun struct hv_retarget_device_interrupt *params;
1224*4882a593Smuzhiyun struct tran_int_desc *int_desc;
1225*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
1226*4882a593Smuzhiyun struct cpumask *dest;
1227*4882a593Smuzhiyun cpumask_var_t tmp;
1228*4882a593Smuzhiyun struct pci_bus *pbus;
1229*4882a593Smuzhiyun struct pci_dev *pdev;
1230*4882a593Smuzhiyun unsigned long flags;
1231*4882a593Smuzhiyun u32 var_size = 0;
1232*4882a593Smuzhiyun int cpu, nr_bank;
1233*4882a593Smuzhiyun u64 res;
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun dest = irq_data_get_effective_affinity_mask(data);
1236*4882a593Smuzhiyun pdev = msi_desc_to_pci_dev(msi_desc);
1237*4882a593Smuzhiyun pbus = pdev->bus;
1238*4882a593Smuzhiyun hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1239*4882a593Smuzhiyun int_desc = data->chip_data;
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun spin_lock_irqsave(&hbus->retarget_msi_interrupt_lock, flags);
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun params = &hbus->retarget_msi_interrupt_params;
1244*4882a593Smuzhiyun memset(params, 0, sizeof(*params));
1245*4882a593Smuzhiyun params->partition_id = HV_PARTITION_ID_SELF;
1246*4882a593Smuzhiyun params->int_entry.source = 1; /* MSI(-X) */
1247*4882a593Smuzhiyun params->int_entry.msi_entry.address = int_desc->address & 0xffffffff;
1248*4882a593Smuzhiyun params->int_entry.msi_entry.data = int_desc->data;
1249*4882a593Smuzhiyun params->device_id = (hbus->hdev->dev_instance.b[5] << 24) |
1250*4882a593Smuzhiyun (hbus->hdev->dev_instance.b[4] << 16) |
1251*4882a593Smuzhiyun (hbus->hdev->dev_instance.b[7] << 8) |
1252*4882a593Smuzhiyun (hbus->hdev->dev_instance.b[6] & 0xf8) |
1253*4882a593Smuzhiyun PCI_FUNC(pdev->devfn);
1254*4882a593Smuzhiyun params->int_target.vector = cfg->vector;
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun /*
1257*4882a593Smuzhiyun * Honoring apic->irq_delivery_mode set to dest_Fixed by
1258*4882a593Smuzhiyun * setting the HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a
1259*4882a593Smuzhiyun * spurious interrupt storm. Not doing so does not seem to have a
1260*4882a593Smuzhiyun * negative effect (yet?).
1261*4882a593Smuzhiyun */
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun if (hbus->protocol_version >= PCI_PROTOCOL_VERSION_1_2) {
1264*4882a593Smuzhiyun /*
1265*4882a593Smuzhiyun * PCI_PROTOCOL_VERSION_1_2 supports the VP_SET version of the
1266*4882a593Smuzhiyun * HVCALL_RETARGET_INTERRUPT hypercall, which also coincides
1267*4882a593Smuzhiyun * with >64 VP support.
1268*4882a593Smuzhiyun * ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED
1269*4882a593Smuzhiyun * is not sufficient for this hypercall.
1270*4882a593Smuzhiyun */
1271*4882a593Smuzhiyun params->int_target.flags |=
1272*4882a593Smuzhiyun HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET;
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun if (!alloc_cpumask_var(&tmp, GFP_ATOMIC)) {
1275*4882a593Smuzhiyun res = 1;
1276*4882a593Smuzhiyun goto exit_unlock;
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun cpumask_and(tmp, dest, cpu_online_mask);
1280*4882a593Smuzhiyun nr_bank = cpumask_to_vpset(¶ms->int_target.vp_set, tmp);
1281*4882a593Smuzhiyun free_cpumask_var(tmp);
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun if (nr_bank <= 0) {
1284*4882a593Smuzhiyun res = 1;
1285*4882a593Smuzhiyun goto exit_unlock;
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun /*
1289*4882a593Smuzhiyun * var-sized hypercall, var-size starts after vp_mask (thus
1290*4882a593Smuzhiyun * vp_set.format does not count, but vp_set.valid_bank_mask
1291*4882a593Smuzhiyun * does).
1292*4882a593Smuzhiyun */
1293*4882a593Smuzhiyun var_size = 1 + nr_bank;
1294*4882a593Smuzhiyun } else {
1295*4882a593Smuzhiyun for_each_cpu_and(cpu, dest, cpu_online_mask) {
1296*4882a593Smuzhiyun params->int_target.vp_mask |=
1297*4882a593Smuzhiyun (1ULL << hv_cpu_number_to_vp_number(cpu));
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun res = hv_do_hypercall(HVCALL_RETARGET_INTERRUPT | (var_size << 17),
1302*4882a593Smuzhiyun params, NULL);
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun exit_unlock:
1305*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->retarget_msi_interrupt_lock, flags);
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun /*
1308*4882a593Smuzhiyun * During hibernation, when a CPU is offlined, the kernel tries
1309*4882a593Smuzhiyun * to move the interrupt to the remaining CPUs that haven't
1310*4882a593Smuzhiyun * been offlined yet. In this case, the below hv_do_hypercall()
1311*4882a593Smuzhiyun * always fails since the vmbus channel has been closed:
1312*4882a593Smuzhiyun * refer to cpu_disable_common() -> fixup_irqs() ->
1313*4882a593Smuzhiyun * irq_migrate_all_off_this_cpu() -> migrate_one_irq().
1314*4882a593Smuzhiyun *
1315*4882a593Smuzhiyun * Suppress the error message for hibernation because the failure
1316*4882a593Smuzhiyun * during hibernation does not matter (at this time all the devices
1317*4882a593Smuzhiyun * have been frozen). Note: the correct affinity info is still updated
1318*4882a593Smuzhiyun * into the irqdata data structure in migrate_one_irq() ->
1319*4882a593Smuzhiyun * irq_do_set_affinity() -> hv_set_affinity(), so later when the VM
1320*4882a593Smuzhiyun * resumes, hv_pci_restore_msi_state() is able to correctly restore
1321*4882a593Smuzhiyun * the interrupt with the correct affinity.
1322*4882a593Smuzhiyun */
1323*4882a593Smuzhiyun if (res && hbus->state != hv_pcibus_removing)
1324*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1325*4882a593Smuzhiyun "%s() failed: %#llx", __func__, res);
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun pci_msi_unmask_irq(data);
1328*4882a593Smuzhiyun }
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun struct compose_comp_ctxt {
1331*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
1332*4882a593Smuzhiyun struct tran_int_desc int_desc;
1333*4882a593Smuzhiyun };
1334*4882a593Smuzhiyun
hv_pci_compose_compl(void * context,struct pci_response * resp,int resp_packet_size)1335*4882a593Smuzhiyun static void hv_pci_compose_compl(void *context, struct pci_response *resp,
1336*4882a593Smuzhiyun int resp_packet_size)
1337*4882a593Smuzhiyun {
1338*4882a593Smuzhiyun struct compose_comp_ctxt *comp_pkt = context;
1339*4882a593Smuzhiyun struct pci_create_int_response *int_resp =
1340*4882a593Smuzhiyun (struct pci_create_int_response *)resp;
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun comp_pkt->comp_pkt.completion_status = resp->status;
1343*4882a593Smuzhiyun comp_pkt->int_desc = int_resp->int_desc;
1344*4882a593Smuzhiyun complete(&comp_pkt->comp_pkt.host_event);
1345*4882a593Smuzhiyun }
1346*4882a593Smuzhiyun
hv_compose_msi_req_v1(struct pci_create_interrupt * int_pkt,struct cpumask * affinity,u32 slot,u8 vector,u8 vector_count)1347*4882a593Smuzhiyun static u32 hv_compose_msi_req_v1(
1348*4882a593Smuzhiyun struct pci_create_interrupt *int_pkt, struct cpumask *affinity,
1349*4882a593Smuzhiyun u32 slot, u8 vector, u8 vector_count)
1350*4882a593Smuzhiyun {
1351*4882a593Smuzhiyun int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1352*4882a593Smuzhiyun int_pkt->wslot.slot = slot;
1353*4882a593Smuzhiyun int_pkt->int_desc.vector = vector;
1354*4882a593Smuzhiyun int_pkt->int_desc.vector_count = vector_count;
1355*4882a593Smuzhiyun int_pkt->int_desc.delivery_mode = dest_Fixed;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun /*
1358*4882a593Smuzhiyun * Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
1359*4882a593Smuzhiyun * hv_irq_unmask().
1360*4882a593Smuzhiyun */
1361*4882a593Smuzhiyun int_pkt->int_desc.cpu_mask = CPU_AFFINITY_ALL;
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun return sizeof(*int_pkt);
1364*4882a593Smuzhiyun }
1365*4882a593Smuzhiyun
hv_compose_msi_req_v2(struct pci_create_interrupt2 * int_pkt,struct cpumask * affinity,u32 slot,u8 vector,u8 vector_count)1366*4882a593Smuzhiyun static u32 hv_compose_msi_req_v2(
1367*4882a593Smuzhiyun struct pci_create_interrupt2 *int_pkt, struct cpumask *affinity,
1368*4882a593Smuzhiyun u32 slot, u8 vector, u8 vector_count)
1369*4882a593Smuzhiyun {
1370*4882a593Smuzhiyun int cpu;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE2;
1373*4882a593Smuzhiyun int_pkt->wslot.slot = slot;
1374*4882a593Smuzhiyun int_pkt->int_desc.vector = vector;
1375*4882a593Smuzhiyun int_pkt->int_desc.vector_count = vector_count;
1376*4882a593Smuzhiyun int_pkt->int_desc.delivery_mode = dest_Fixed;
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun /*
1379*4882a593Smuzhiyun * Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten
1380*4882a593Smuzhiyun * by subsequent retarget in hv_irq_unmask().
1381*4882a593Smuzhiyun */
1382*4882a593Smuzhiyun cpu = cpumask_first_and(affinity, cpu_online_mask);
1383*4882a593Smuzhiyun int_pkt->int_desc.processor_array[0] =
1384*4882a593Smuzhiyun hv_cpu_number_to_vp_number(cpu);
1385*4882a593Smuzhiyun int_pkt->int_desc.processor_count = 1;
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun return sizeof(*int_pkt);
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun /**
1391*4882a593Smuzhiyun * hv_compose_msi_msg() - Supplies a valid MSI address/data
1392*4882a593Smuzhiyun * @data: Everything about this MSI
1393*4882a593Smuzhiyun * @msg: Buffer that is filled in by this function
1394*4882a593Smuzhiyun *
1395*4882a593Smuzhiyun * This function unpacks the IRQ looking for target CPU set, IDT
1396*4882a593Smuzhiyun * vector and mode and sends a message to the parent partition
1397*4882a593Smuzhiyun * asking for a mapping for that tuple in this partition. The
1398*4882a593Smuzhiyun * response supplies a data value and address to which that data
1399*4882a593Smuzhiyun * should be written to trigger that interrupt.
1400*4882a593Smuzhiyun */
hv_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)1401*4882a593Smuzhiyun static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
1404*4882a593Smuzhiyun struct vmbus_channel *channel;
1405*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1406*4882a593Smuzhiyun struct pci_bus *pbus;
1407*4882a593Smuzhiyun struct pci_dev *pdev;
1408*4882a593Smuzhiyun struct cpumask *dest;
1409*4882a593Smuzhiyun struct compose_comp_ctxt comp;
1410*4882a593Smuzhiyun struct tran_int_desc *int_desc;
1411*4882a593Smuzhiyun struct msi_desc *msi_desc;
1412*4882a593Smuzhiyun u8 vector, vector_count;
1413*4882a593Smuzhiyun struct {
1414*4882a593Smuzhiyun struct pci_packet pci_pkt;
1415*4882a593Smuzhiyun union {
1416*4882a593Smuzhiyun struct pci_create_interrupt v1;
1417*4882a593Smuzhiyun struct pci_create_interrupt2 v2;
1418*4882a593Smuzhiyun } int_pkts;
1419*4882a593Smuzhiyun } __packed ctxt;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun u32 size;
1422*4882a593Smuzhiyun int ret;
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun /* Reuse the previous allocation */
1425*4882a593Smuzhiyun if (data->chip_data) {
1426*4882a593Smuzhiyun int_desc = data->chip_data;
1427*4882a593Smuzhiyun msg->address_hi = int_desc->address >> 32;
1428*4882a593Smuzhiyun msg->address_lo = int_desc->address & 0xffffffff;
1429*4882a593Smuzhiyun msg->data = int_desc->data;
1430*4882a593Smuzhiyun return;
1431*4882a593Smuzhiyun }
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun msi_desc = irq_data_get_msi_desc(data);
1434*4882a593Smuzhiyun pdev = msi_desc_to_pci_dev(msi_desc);
1435*4882a593Smuzhiyun dest = irq_data_get_effective_affinity_mask(data);
1436*4882a593Smuzhiyun pbus = pdev->bus;
1437*4882a593Smuzhiyun hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1438*4882a593Smuzhiyun channel = hbus->hdev->channel;
1439*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1440*4882a593Smuzhiyun if (!hpdev)
1441*4882a593Smuzhiyun goto return_null_message;
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun int_desc = kzalloc(sizeof(*int_desc), GFP_ATOMIC);
1444*4882a593Smuzhiyun if (!int_desc)
1445*4882a593Smuzhiyun goto drop_reference;
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun if (!msi_desc->msi_attrib.is_msix && msi_desc->nvec_used > 1) {
1448*4882a593Smuzhiyun /*
1449*4882a593Smuzhiyun * If this is not the first MSI of Multi MSI, we already have
1450*4882a593Smuzhiyun * a mapping. Can exit early.
1451*4882a593Smuzhiyun */
1452*4882a593Smuzhiyun if (msi_desc->irq != data->irq) {
1453*4882a593Smuzhiyun data->chip_data = int_desc;
1454*4882a593Smuzhiyun int_desc->address = msi_desc->msg.address_lo |
1455*4882a593Smuzhiyun (u64)msi_desc->msg.address_hi << 32;
1456*4882a593Smuzhiyun int_desc->data = msi_desc->msg.data +
1457*4882a593Smuzhiyun (data->irq - msi_desc->irq);
1458*4882a593Smuzhiyun msg->address_hi = msi_desc->msg.address_hi;
1459*4882a593Smuzhiyun msg->address_lo = msi_desc->msg.address_lo;
1460*4882a593Smuzhiyun msg->data = int_desc->data;
1461*4882a593Smuzhiyun put_pcichild(hpdev);
1462*4882a593Smuzhiyun return;
1463*4882a593Smuzhiyun }
1464*4882a593Smuzhiyun /*
1465*4882a593Smuzhiyun * The vector we select here is a dummy value. The correct
1466*4882a593Smuzhiyun * value gets sent to the hypervisor in unmask(). This needs
1467*4882a593Smuzhiyun * to be aligned with the count, and also not zero. Multi-msi
1468*4882a593Smuzhiyun * is powers of 2 up to 32, so 32 will always work here.
1469*4882a593Smuzhiyun */
1470*4882a593Smuzhiyun vector = 32;
1471*4882a593Smuzhiyun vector_count = msi_desc->nvec_used;
1472*4882a593Smuzhiyun } else {
1473*4882a593Smuzhiyun vector = hv_msi_get_int_vector(data);
1474*4882a593Smuzhiyun vector_count = 1;
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun memset(&ctxt, 0, sizeof(ctxt));
1478*4882a593Smuzhiyun init_completion(&comp.comp_pkt.host_event);
1479*4882a593Smuzhiyun ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
1480*4882a593Smuzhiyun ctxt.pci_pkt.compl_ctxt = ∁
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun switch (hbus->protocol_version) {
1483*4882a593Smuzhiyun case PCI_PROTOCOL_VERSION_1_1:
1484*4882a593Smuzhiyun size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
1485*4882a593Smuzhiyun dest,
1486*4882a593Smuzhiyun hpdev->desc.win_slot.slot,
1487*4882a593Smuzhiyun vector,
1488*4882a593Smuzhiyun vector_count);
1489*4882a593Smuzhiyun break;
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun case PCI_PROTOCOL_VERSION_1_2:
1492*4882a593Smuzhiyun case PCI_PROTOCOL_VERSION_1_3:
1493*4882a593Smuzhiyun size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
1494*4882a593Smuzhiyun dest,
1495*4882a593Smuzhiyun hpdev->desc.win_slot.slot,
1496*4882a593Smuzhiyun vector,
1497*4882a593Smuzhiyun vector_count);
1498*4882a593Smuzhiyun break;
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun default:
1501*4882a593Smuzhiyun /* As we only negotiate protocol versions known to this driver,
1502*4882a593Smuzhiyun * this path should never hit. However, this is it not a hot
1503*4882a593Smuzhiyun * path so we print a message to aid future updates.
1504*4882a593Smuzhiyun */
1505*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1506*4882a593Smuzhiyun "Unexpected vPCI protocol, update driver.");
1507*4882a593Smuzhiyun goto free_int_desc;
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun ret = vmbus_sendpacket(hpdev->hbus->hdev->channel, &ctxt.int_pkts,
1511*4882a593Smuzhiyun size, (unsigned long)&ctxt.pci_pkt,
1512*4882a593Smuzhiyun VM_PKT_DATA_INBAND,
1513*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1514*4882a593Smuzhiyun if (ret) {
1515*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1516*4882a593Smuzhiyun "Sending request for interrupt failed: 0x%x",
1517*4882a593Smuzhiyun comp.comp_pkt.completion_status);
1518*4882a593Smuzhiyun goto free_int_desc;
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun /*
1522*4882a593Smuzhiyun * Prevents hv_pci_onchannelcallback() from running concurrently
1523*4882a593Smuzhiyun * in the tasklet.
1524*4882a593Smuzhiyun */
1525*4882a593Smuzhiyun tasklet_disable(&channel->callback_event);
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun /*
1528*4882a593Smuzhiyun * Since this function is called with IRQ locks held, can't
1529*4882a593Smuzhiyun * do normal wait for completion; instead poll.
1530*4882a593Smuzhiyun */
1531*4882a593Smuzhiyun while (!try_wait_for_completion(&comp.comp_pkt.host_event)) {
1532*4882a593Smuzhiyun unsigned long flags;
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun /* 0xFFFF means an invalid PCI VENDOR ID. */
1535*4882a593Smuzhiyun if (hv_pcifront_get_vendor_id(hpdev) == 0xFFFF) {
1536*4882a593Smuzhiyun dev_err_once(&hbus->hdev->device,
1537*4882a593Smuzhiyun "the device has gone\n");
1538*4882a593Smuzhiyun goto enable_tasklet;
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun /*
1542*4882a593Smuzhiyun * Make sure that the ring buffer data structure doesn't get
1543*4882a593Smuzhiyun * freed while we dereference the ring buffer pointer. Test
1544*4882a593Smuzhiyun * for the channel's onchannel_callback being NULL within a
1545*4882a593Smuzhiyun * sched_lock critical section. See also the inline comments
1546*4882a593Smuzhiyun * in vmbus_reset_channel_cb().
1547*4882a593Smuzhiyun */
1548*4882a593Smuzhiyun spin_lock_irqsave(&channel->sched_lock, flags);
1549*4882a593Smuzhiyun if (unlikely(channel->onchannel_callback == NULL)) {
1550*4882a593Smuzhiyun spin_unlock_irqrestore(&channel->sched_lock, flags);
1551*4882a593Smuzhiyun goto enable_tasklet;
1552*4882a593Smuzhiyun }
1553*4882a593Smuzhiyun hv_pci_onchannelcallback(hbus);
1554*4882a593Smuzhiyun spin_unlock_irqrestore(&channel->sched_lock, flags);
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun if (hpdev->state == hv_pcichild_ejecting) {
1557*4882a593Smuzhiyun dev_err_once(&hbus->hdev->device,
1558*4882a593Smuzhiyun "the device is being ejected\n");
1559*4882a593Smuzhiyun goto enable_tasklet;
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun
1562*4882a593Smuzhiyun udelay(100);
1563*4882a593Smuzhiyun }
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun tasklet_enable(&channel->callback_event);
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun if (comp.comp_pkt.completion_status < 0) {
1568*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1569*4882a593Smuzhiyun "Request for interrupt failed: 0x%x",
1570*4882a593Smuzhiyun comp.comp_pkt.completion_status);
1571*4882a593Smuzhiyun goto free_int_desc;
1572*4882a593Smuzhiyun }
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun /*
1575*4882a593Smuzhiyun * Record the assignment so that this can be unwound later. Using
1576*4882a593Smuzhiyun * irq_set_chip_data() here would be appropriate, but the lock it takes
1577*4882a593Smuzhiyun * is already held.
1578*4882a593Smuzhiyun */
1579*4882a593Smuzhiyun *int_desc = comp.int_desc;
1580*4882a593Smuzhiyun data->chip_data = int_desc;
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun /* Pass up the result. */
1583*4882a593Smuzhiyun msg->address_hi = comp.int_desc.address >> 32;
1584*4882a593Smuzhiyun msg->address_lo = comp.int_desc.address & 0xffffffff;
1585*4882a593Smuzhiyun msg->data = comp.int_desc.data;
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun put_pcichild(hpdev);
1588*4882a593Smuzhiyun return;
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun enable_tasklet:
1591*4882a593Smuzhiyun tasklet_enable(&channel->callback_event);
1592*4882a593Smuzhiyun free_int_desc:
1593*4882a593Smuzhiyun kfree(int_desc);
1594*4882a593Smuzhiyun drop_reference:
1595*4882a593Smuzhiyun put_pcichild(hpdev);
1596*4882a593Smuzhiyun return_null_message:
1597*4882a593Smuzhiyun msg->address_hi = 0;
1598*4882a593Smuzhiyun msg->address_lo = 0;
1599*4882a593Smuzhiyun msg->data = 0;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun /* HW Interrupt Chip Descriptor */
1603*4882a593Smuzhiyun static struct irq_chip hv_msi_irq_chip = {
1604*4882a593Smuzhiyun .name = "Hyper-V PCIe MSI",
1605*4882a593Smuzhiyun .irq_compose_msi_msg = hv_compose_msi_msg,
1606*4882a593Smuzhiyun .irq_set_affinity = hv_set_affinity,
1607*4882a593Smuzhiyun .irq_ack = irq_chip_ack_parent,
1608*4882a593Smuzhiyun .irq_mask = hv_irq_mask,
1609*4882a593Smuzhiyun .irq_unmask = hv_irq_unmask,
1610*4882a593Smuzhiyun };
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun static struct msi_domain_ops hv_msi_ops = {
1613*4882a593Smuzhiyun .msi_prepare = hv_msi_prepare,
1614*4882a593Smuzhiyun .msi_free = hv_msi_free,
1615*4882a593Smuzhiyun };
1616*4882a593Smuzhiyun
1617*4882a593Smuzhiyun /**
1618*4882a593Smuzhiyun * hv_pcie_init_irq_domain() - Initialize IRQ domain
1619*4882a593Smuzhiyun * @hbus: The root PCI bus
1620*4882a593Smuzhiyun *
1621*4882a593Smuzhiyun * This function creates an IRQ domain which will be used for
1622*4882a593Smuzhiyun * interrupts from devices that have been passed through. These
1623*4882a593Smuzhiyun * devices only support MSI and MSI-X, not line-based interrupts
1624*4882a593Smuzhiyun * or simulations of line-based interrupts through PCIe's
1625*4882a593Smuzhiyun * fabric-layer messages. Because interrupts are remapped, we
1626*4882a593Smuzhiyun * can support multi-message MSI here.
1627*4882a593Smuzhiyun *
1628*4882a593Smuzhiyun * Return: '0' on success and error value on failure
1629*4882a593Smuzhiyun */
hv_pcie_init_irq_domain(struct hv_pcibus_device * hbus)1630*4882a593Smuzhiyun static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
1631*4882a593Smuzhiyun {
1632*4882a593Smuzhiyun hbus->msi_info.chip = &hv_msi_irq_chip;
1633*4882a593Smuzhiyun hbus->msi_info.ops = &hv_msi_ops;
1634*4882a593Smuzhiyun hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
1635*4882a593Smuzhiyun MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
1636*4882a593Smuzhiyun MSI_FLAG_PCI_MSIX);
1637*4882a593Smuzhiyun hbus->msi_info.handler = handle_edge_irq;
1638*4882a593Smuzhiyun hbus->msi_info.handler_name = "edge";
1639*4882a593Smuzhiyun hbus->msi_info.data = hbus;
1640*4882a593Smuzhiyun hbus->irq_domain = pci_msi_create_irq_domain(hbus->sysdata.fwnode,
1641*4882a593Smuzhiyun &hbus->msi_info,
1642*4882a593Smuzhiyun x86_vector_domain);
1643*4882a593Smuzhiyun if (!hbus->irq_domain) {
1644*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1645*4882a593Smuzhiyun "Failed to build an MSI IRQ domain\n");
1646*4882a593Smuzhiyun return -ENODEV;
1647*4882a593Smuzhiyun }
1648*4882a593Smuzhiyun
1649*4882a593Smuzhiyun return 0;
1650*4882a593Smuzhiyun }
1651*4882a593Smuzhiyun
1652*4882a593Smuzhiyun /**
1653*4882a593Smuzhiyun * get_bar_size() - Get the address space consumed by a BAR
1654*4882a593Smuzhiyun * @bar_val: Value that a BAR returned after -1 was written
1655*4882a593Smuzhiyun * to it.
1656*4882a593Smuzhiyun *
1657*4882a593Smuzhiyun * This function returns the size of the BAR, rounded up to 1
1658*4882a593Smuzhiyun * page. It has to be rounded up because the hypervisor's page
1659*4882a593Smuzhiyun * table entry that maps the BAR into the VM can't specify an
1660*4882a593Smuzhiyun * offset within a page. The invariant is that the hypervisor
1661*4882a593Smuzhiyun * must place any BARs of smaller than page length at the
1662*4882a593Smuzhiyun * beginning of a page.
1663*4882a593Smuzhiyun *
1664*4882a593Smuzhiyun * Return: Size in bytes of the consumed MMIO space.
1665*4882a593Smuzhiyun */
get_bar_size(u64 bar_val)1666*4882a593Smuzhiyun static u64 get_bar_size(u64 bar_val)
1667*4882a593Smuzhiyun {
1668*4882a593Smuzhiyun return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
1669*4882a593Smuzhiyun PAGE_SIZE);
1670*4882a593Smuzhiyun }
1671*4882a593Smuzhiyun
1672*4882a593Smuzhiyun /**
1673*4882a593Smuzhiyun * survey_child_resources() - Total all MMIO requirements
1674*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
1675*4882a593Smuzhiyun */
survey_child_resources(struct hv_pcibus_device * hbus)1676*4882a593Smuzhiyun static void survey_child_resources(struct hv_pcibus_device *hbus)
1677*4882a593Smuzhiyun {
1678*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1679*4882a593Smuzhiyun resource_size_t bar_size = 0;
1680*4882a593Smuzhiyun unsigned long flags;
1681*4882a593Smuzhiyun struct completion *event;
1682*4882a593Smuzhiyun u64 bar_val;
1683*4882a593Smuzhiyun int i;
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun /* If nobody is waiting on the answer, don't compute it. */
1686*4882a593Smuzhiyun event = xchg(&hbus->survey_event, NULL);
1687*4882a593Smuzhiyun if (!event)
1688*4882a593Smuzhiyun return;
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun /* If the answer has already been computed, go with it. */
1691*4882a593Smuzhiyun if (hbus->low_mmio_space || hbus->high_mmio_space) {
1692*4882a593Smuzhiyun complete(event);
1693*4882a593Smuzhiyun return;
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun /*
1699*4882a593Smuzhiyun * Due to an interesting quirk of the PCI spec, all memory regions
1700*4882a593Smuzhiyun * for a child device are a power of 2 in size and aligned in memory,
1701*4882a593Smuzhiyun * so it's sufficient to just add them up without tracking alignment.
1702*4882a593Smuzhiyun */
1703*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
1704*4882a593Smuzhiyun for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1705*4882a593Smuzhiyun if (hpdev->probed_bar[i] & PCI_BASE_ADDRESS_SPACE_IO)
1706*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
1707*4882a593Smuzhiyun "There's an I/O BAR in this list!\n");
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun if (hpdev->probed_bar[i] != 0) {
1710*4882a593Smuzhiyun /*
1711*4882a593Smuzhiyun * A probed BAR has all the upper bits set that
1712*4882a593Smuzhiyun * can be changed.
1713*4882a593Smuzhiyun */
1714*4882a593Smuzhiyun
1715*4882a593Smuzhiyun bar_val = hpdev->probed_bar[i];
1716*4882a593Smuzhiyun if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
1717*4882a593Smuzhiyun bar_val |=
1718*4882a593Smuzhiyun ((u64)hpdev->probed_bar[++i] << 32);
1719*4882a593Smuzhiyun else
1720*4882a593Smuzhiyun bar_val |= 0xffffffff00000000ULL;
1721*4882a593Smuzhiyun
1722*4882a593Smuzhiyun bar_size = get_bar_size(bar_val);
1723*4882a593Smuzhiyun
1724*4882a593Smuzhiyun if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
1725*4882a593Smuzhiyun hbus->high_mmio_space += bar_size;
1726*4882a593Smuzhiyun else
1727*4882a593Smuzhiyun hbus->low_mmio_space += bar_size;
1728*4882a593Smuzhiyun }
1729*4882a593Smuzhiyun }
1730*4882a593Smuzhiyun }
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
1733*4882a593Smuzhiyun complete(event);
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun /**
1737*4882a593Smuzhiyun * prepopulate_bars() - Fill in BARs with defaults
1738*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
1739*4882a593Smuzhiyun *
1740*4882a593Smuzhiyun * The core PCI driver code seems much, much happier if the BARs
1741*4882a593Smuzhiyun * for a device have values upon first scan. So fill them in.
1742*4882a593Smuzhiyun * The algorithm below works down from large sizes to small,
1743*4882a593Smuzhiyun * attempting to pack the assignments optimally. The assumption,
1744*4882a593Smuzhiyun * enforced in other parts of the code, is that the beginning of
1745*4882a593Smuzhiyun * the memory-mapped I/O space will be aligned on the largest
1746*4882a593Smuzhiyun * BAR size.
1747*4882a593Smuzhiyun */
prepopulate_bars(struct hv_pcibus_device * hbus)1748*4882a593Smuzhiyun static void prepopulate_bars(struct hv_pcibus_device *hbus)
1749*4882a593Smuzhiyun {
1750*4882a593Smuzhiyun resource_size_t high_size = 0;
1751*4882a593Smuzhiyun resource_size_t low_size = 0;
1752*4882a593Smuzhiyun resource_size_t high_base = 0;
1753*4882a593Smuzhiyun resource_size_t low_base = 0;
1754*4882a593Smuzhiyun resource_size_t bar_size;
1755*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1756*4882a593Smuzhiyun unsigned long flags;
1757*4882a593Smuzhiyun u64 bar_val;
1758*4882a593Smuzhiyun u32 command;
1759*4882a593Smuzhiyun bool high;
1760*4882a593Smuzhiyun int i;
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun if (hbus->low_mmio_space) {
1763*4882a593Smuzhiyun low_size = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
1764*4882a593Smuzhiyun low_base = hbus->low_mmio_res->start;
1765*4882a593Smuzhiyun }
1766*4882a593Smuzhiyun
1767*4882a593Smuzhiyun if (hbus->high_mmio_space) {
1768*4882a593Smuzhiyun high_size = 1ULL <<
1769*4882a593Smuzhiyun (63 - __builtin_clzll(hbus->high_mmio_space));
1770*4882a593Smuzhiyun high_base = hbus->high_mmio_res->start;
1771*4882a593Smuzhiyun }
1772*4882a593Smuzhiyun
1773*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun /*
1776*4882a593Smuzhiyun * Clear the memory enable bit, in case it's already set. This occurs
1777*4882a593Smuzhiyun * in the suspend path of hibernation, where the device is suspended,
1778*4882a593Smuzhiyun * resumed and suspended again: see hibernation_snapshot() and
1779*4882a593Smuzhiyun * hibernation_platform_enter().
1780*4882a593Smuzhiyun *
1781*4882a593Smuzhiyun * If the memory enable bit is already set, Hyper-V sliently ignores
1782*4882a593Smuzhiyun * the below BAR updates, and the related PCI device driver can not
1783*4882a593Smuzhiyun * work, because reading from the device register(s) always returns
1784*4882a593Smuzhiyun * 0xFFFFFFFF.
1785*4882a593Smuzhiyun */
1786*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
1787*4882a593Smuzhiyun _hv_pcifront_read_config(hpdev, PCI_COMMAND, 2, &command);
1788*4882a593Smuzhiyun command &= ~PCI_COMMAND_MEMORY;
1789*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev, PCI_COMMAND, 2, command);
1790*4882a593Smuzhiyun }
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun /* Pick addresses for the BARs. */
1793*4882a593Smuzhiyun do {
1794*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
1795*4882a593Smuzhiyun for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1796*4882a593Smuzhiyun bar_val = hpdev->probed_bar[i];
1797*4882a593Smuzhiyun if (bar_val == 0)
1798*4882a593Smuzhiyun continue;
1799*4882a593Smuzhiyun high = bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64;
1800*4882a593Smuzhiyun if (high) {
1801*4882a593Smuzhiyun bar_val |=
1802*4882a593Smuzhiyun ((u64)hpdev->probed_bar[i + 1]
1803*4882a593Smuzhiyun << 32);
1804*4882a593Smuzhiyun } else {
1805*4882a593Smuzhiyun bar_val |= 0xffffffffULL << 32;
1806*4882a593Smuzhiyun }
1807*4882a593Smuzhiyun bar_size = get_bar_size(bar_val);
1808*4882a593Smuzhiyun if (high) {
1809*4882a593Smuzhiyun if (high_size != bar_size) {
1810*4882a593Smuzhiyun i++;
1811*4882a593Smuzhiyun continue;
1812*4882a593Smuzhiyun }
1813*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev,
1814*4882a593Smuzhiyun PCI_BASE_ADDRESS_0 + (4 * i),
1815*4882a593Smuzhiyun 4,
1816*4882a593Smuzhiyun (u32)(high_base & 0xffffff00));
1817*4882a593Smuzhiyun i++;
1818*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev,
1819*4882a593Smuzhiyun PCI_BASE_ADDRESS_0 + (4 * i),
1820*4882a593Smuzhiyun 4, (u32)(high_base >> 32));
1821*4882a593Smuzhiyun high_base += bar_size;
1822*4882a593Smuzhiyun } else {
1823*4882a593Smuzhiyun if (low_size != bar_size)
1824*4882a593Smuzhiyun continue;
1825*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev,
1826*4882a593Smuzhiyun PCI_BASE_ADDRESS_0 + (4 * i),
1827*4882a593Smuzhiyun 4,
1828*4882a593Smuzhiyun (u32)(low_base & 0xffffff00));
1829*4882a593Smuzhiyun low_base += bar_size;
1830*4882a593Smuzhiyun }
1831*4882a593Smuzhiyun }
1832*4882a593Smuzhiyun if (high_size <= 1 && low_size <= 1) {
1833*4882a593Smuzhiyun /* Set the memory enable bit. */
1834*4882a593Smuzhiyun _hv_pcifront_read_config(hpdev, PCI_COMMAND, 2,
1835*4882a593Smuzhiyun &command);
1836*4882a593Smuzhiyun command |= PCI_COMMAND_MEMORY;
1837*4882a593Smuzhiyun _hv_pcifront_write_config(hpdev, PCI_COMMAND, 2,
1838*4882a593Smuzhiyun command);
1839*4882a593Smuzhiyun break;
1840*4882a593Smuzhiyun }
1841*4882a593Smuzhiyun }
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun high_size >>= 1;
1844*4882a593Smuzhiyun low_size >>= 1;
1845*4882a593Smuzhiyun } while (high_size || low_size);
1846*4882a593Smuzhiyun
1847*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
1848*4882a593Smuzhiyun }
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun /*
1851*4882a593Smuzhiyun * Assign entries in sysfs pci slot directory.
1852*4882a593Smuzhiyun *
1853*4882a593Smuzhiyun * Note that this function does not need to lock the children list
1854*4882a593Smuzhiyun * because it is called from pci_devices_present_work which
1855*4882a593Smuzhiyun * is serialized with hv_eject_device_work because they are on the
1856*4882a593Smuzhiyun * same ordered workqueue. Therefore hbus->children list will not change
1857*4882a593Smuzhiyun * even when pci_create_slot sleeps.
1858*4882a593Smuzhiyun */
hv_pci_assign_slots(struct hv_pcibus_device * hbus)1859*4882a593Smuzhiyun static void hv_pci_assign_slots(struct hv_pcibus_device *hbus)
1860*4882a593Smuzhiyun {
1861*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1862*4882a593Smuzhiyun char name[SLOT_NAME_SIZE];
1863*4882a593Smuzhiyun int slot_nr;
1864*4882a593Smuzhiyun
1865*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
1866*4882a593Smuzhiyun if (hpdev->pci_slot)
1867*4882a593Smuzhiyun continue;
1868*4882a593Smuzhiyun
1869*4882a593Smuzhiyun slot_nr = PCI_SLOT(wslot_to_devfn(hpdev->desc.win_slot.slot));
1870*4882a593Smuzhiyun snprintf(name, SLOT_NAME_SIZE, "%u", hpdev->desc.ser);
1871*4882a593Smuzhiyun hpdev->pci_slot = pci_create_slot(hbus->pci_bus, slot_nr,
1872*4882a593Smuzhiyun name, NULL);
1873*4882a593Smuzhiyun if (IS_ERR(hpdev->pci_slot)) {
1874*4882a593Smuzhiyun pr_warn("pci_create slot %s failed\n", name);
1875*4882a593Smuzhiyun hpdev->pci_slot = NULL;
1876*4882a593Smuzhiyun }
1877*4882a593Smuzhiyun }
1878*4882a593Smuzhiyun }
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun /*
1881*4882a593Smuzhiyun * Remove entries in sysfs pci slot directory.
1882*4882a593Smuzhiyun */
hv_pci_remove_slots(struct hv_pcibus_device * hbus)1883*4882a593Smuzhiyun static void hv_pci_remove_slots(struct hv_pcibus_device *hbus)
1884*4882a593Smuzhiyun {
1885*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
1888*4882a593Smuzhiyun if (!hpdev->pci_slot)
1889*4882a593Smuzhiyun continue;
1890*4882a593Smuzhiyun pci_destroy_slot(hpdev->pci_slot);
1891*4882a593Smuzhiyun hpdev->pci_slot = NULL;
1892*4882a593Smuzhiyun }
1893*4882a593Smuzhiyun }
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun /*
1896*4882a593Smuzhiyun * Set NUMA node for the devices on the bus
1897*4882a593Smuzhiyun */
hv_pci_assign_numa_node(struct hv_pcibus_device * hbus)1898*4882a593Smuzhiyun static void hv_pci_assign_numa_node(struct hv_pcibus_device *hbus)
1899*4882a593Smuzhiyun {
1900*4882a593Smuzhiyun struct pci_dev *dev;
1901*4882a593Smuzhiyun struct pci_bus *bus = hbus->pci_bus;
1902*4882a593Smuzhiyun struct hv_pci_dev *hv_dev;
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun list_for_each_entry(dev, &bus->devices, bus_list) {
1905*4882a593Smuzhiyun hv_dev = get_pcichild_wslot(hbus, devfn_to_wslot(dev->devfn));
1906*4882a593Smuzhiyun if (!hv_dev)
1907*4882a593Smuzhiyun continue;
1908*4882a593Smuzhiyun
1909*4882a593Smuzhiyun if (hv_dev->desc.flags & HV_PCI_DEVICE_FLAG_NUMA_AFFINITY &&
1910*4882a593Smuzhiyun hv_dev->desc.virtual_numa_node < num_possible_nodes())
1911*4882a593Smuzhiyun /*
1912*4882a593Smuzhiyun * The kernel may boot with some NUMA nodes offline
1913*4882a593Smuzhiyun * (e.g. in a KDUMP kernel) or with NUMA disabled via
1914*4882a593Smuzhiyun * "numa=off". In those cases, adjust the host provided
1915*4882a593Smuzhiyun * NUMA node to a valid NUMA node used by the kernel.
1916*4882a593Smuzhiyun */
1917*4882a593Smuzhiyun set_dev_node(&dev->dev,
1918*4882a593Smuzhiyun numa_map_to_online_node(
1919*4882a593Smuzhiyun hv_dev->desc.virtual_numa_node));
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun put_pcichild(hv_dev);
1922*4882a593Smuzhiyun }
1923*4882a593Smuzhiyun }
1924*4882a593Smuzhiyun
1925*4882a593Smuzhiyun /**
1926*4882a593Smuzhiyun * create_root_hv_pci_bus() - Expose a new root PCI bus
1927*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
1928*4882a593Smuzhiyun *
1929*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
1930*4882a593Smuzhiyun */
create_root_hv_pci_bus(struct hv_pcibus_device * hbus)1931*4882a593Smuzhiyun static int create_root_hv_pci_bus(struct hv_pcibus_device *hbus)
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun /* Register the device */
1934*4882a593Smuzhiyun hbus->pci_bus = pci_create_root_bus(&hbus->hdev->device,
1935*4882a593Smuzhiyun 0, /* bus number is always zero */
1936*4882a593Smuzhiyun &hv_pcifront_ops,
1937*4882a593Smuzhiyun &hbus->sysdata,
1938*4882a593Smuzhiyun &hbus->resources_for_children);
1939*4882a593Smuzhiyun if (!hbus->pci_bus)
1940*4882a593Smuzhiyun return -ENODEV;
1941*4882a593Smuzhiyun
1942*4882a593Smuzhiyun hbus->pci_bus->msi = &hbus->msi_chip;
1943*4882a593Smuzhiyun hbus->pci_bus->msi->dev = &hbus->hdev->device;
1944*4882a593Smuzhiyun
1945*4882a593Smuzhiyun pci_lock_rescan_remove();
1946*4882a593Smuzhiyun pci_scan_child_bus(hbus->pci_bus);
1947*4882a593Smuzhiyun hv_pci_assign_numa_node(hbus);
1948*4882a593Smuzhiyun pci_bus_assign_resources(hbus->pci_bus);
1949*4882a593Smuzhiyun hv_pci_assign_slots(hbus);
1950*4882a593Smuzhiyun pci_bus_add_devices(hbus->pci_bus);
1951*4882a593Smuzhiyun pci_unlock_rescan_remove();
1952*4882a593Smuzhiyun hbus->state = hv_pcibus_installed;
1953*4882a593Smuzhiyun return 0;
1954*4882a593Smuzhiyun }
1955*4882a593Smuzhiyun
1956*4882a593Smuzhiyun struct q_res_req_compl {
1957*4882a593Smuzhiyun struct completion host_event;
1958*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
1959*4882a593Smuzhiyun };
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun /**
1962*4882a593Smuzhiyun * q_resource_requirements() - Query Resource Requirements
1963*4882a593Smuzhiyun * @context: The completion context.
1964*4882a593Smuzhiyun * @resp: The response that came from the host.
1965*4882a593Smuzhiyun * @resp_packet_size: The size in bytes of resp.
1966*4882a593Smuzhiyun *
1967*4882a593Smuzhiyun * This function is invoked on completion of a Query Resource
1968*4882a593Smuzhiyun * Requirements packet.
1969*4882a593Smuzhiyun */
q_resource_requirements(void * context,struct pci_response * resp,int resp_packet_size)1970*4882a593Smuzhiyun static void q_resource_requirements(void *context, struct pci_response *resp,
1971*4882a593Smuzhiyun int resp_packet_size)
1972*4882a593Smuzhiyun {
1973*4882a593Smuzhiyun struct q_res_req_compl *completion = context;
1974*4882a593Smuzhiyun struct pci_q_res_req_response *q_res_req =
1975*4882a593Smuzhiyun (struct pci_q_res_req_response *)resp;
1976*4882a593Smuzhiyun int i;
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun if (resp->status < 0) {
1979*4882a593Smuzhiyun dev_err(&completion->hpdev->hbus->hdev->device,
1980*4882a593Smuzhiyun "query resource requirements failed: %x\n",
1981*4882a593Smuzhiyun resp->status);
1982*4882a593Smuzhiyun } else {
1983*4882a593Smuzhiyun for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1984*4882a593Smuzhiyun completion->hpdev->probed_bar[i] =
1985*4882a593Smuzhiyun q_res_req->probed_bar[i];
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun }
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun complete(&completion->host_event);
1990*4882a593Smuzhiyun }
1991*4882a593Smuzhiyun
1992*4882a593Smuzhiyun /**
1993*4882a593Smuzhiyun * new_pcichild_device() - Create a new child device
1994*4882a593Smuzhiyun * @hbus: The internal struct tracking this root PCI bus.
1995*4882a593Smuzhiyun * @desc: The information supplied so far from the host
1996*4882a593Smuzhiyun * about the device.
1997*4882a593Smuzhiyun *
1998*4882a593Smuzhiyun * This function creates the tracking structure for a new child
1999*4882a593Smuzhiyun * device and kicks off the process of figuring out what it is.
2000*4882a593Smuzhiyun *
2001*4882a593Smuzhiyun * Return: Pointer to the new tracking struct
2002*4882a593Smuzhiyun */
new_pcichild_device(struct hv_pcibus_device * hbus,struct hv_pcidev_description * desc)2003*4882a593Smuzhiyun static struct hv_pci_dev *new_pcichild_device(struct hv_pcibus_device *hbus,
2004*4882a593Smuzhiyun struct hv_pcidev_description *desc)
2005*4882a593Smuzhiyun {
2006*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
2007*4882a593Smuzhiyun struct pci_child_message *res_req;
2008*4882a593Smuzhiyun struct q_res_req_compl comp_pkt;
2009*4882a593Smuzhiyun struct {
2010*4882a593Smuzhiyun struct pci_packet init_packet;
2011*4882a593Smuzhiyun u8 buffer[sizeof(struct pci_child_message)];
2012*4882a593Smuzhiyun } pkt;
2013*4882a593Smuzhiyun unsigned long flags;
2014*4882a593Smuzhiyun int ret;
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun hpdev = kzalloc(sizeof(*hpdev), GFP_KERNEL);
2017*4882a593Smuzhiyun if (!hpdev)
2018*4882a593Smuzhiyun return NULL;
2019*4882a593Smuzhiyun
2020*4882a593Smuzhiyun hpdev->hbus = hbus;
2021*4882a593Smuzhiyun
2022*4882a593Smuzhiyun memset(&pkt, 0, sizeof(pkt));
2023*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
2024*4882a593Smuzhiyun comp_pkt.hpdev = hpdev;
2025*4882a593Smuzhiyun pkt.init_packet.compl_ctxt = &comp_pkt;
2026*4882a593Smuzhiyun pkt.init_packet.completion_func = q_resource_requirements;
2027*4882a593Smuzhiyun res_req = (struct pci_child_message *)&pkt.init_packet.message;
2028*4882a593Smuzhiyun res_req->message_type.type = PCI_QUERY_RESOURCE_REQUIREMENTS;
2029*4882a593Smuzhiyun res_req->wslot.slot = desc->win_slot.slot;
2030*4882a593Smuzhiyun
2031*4882a593Smuzhiyun ret = vmbus_sendpacket(hbus->hdev->channel, res_req,
2032*4882a593Smuzhiyun sizeof(struct pci_child_message),
2033*4882a593Smuzhiyun (unsigned long)&pkt.init_packet,
2034*4882a593Smuzhiyun VM_PKT_DATA_INBAND,
2035*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2036*4882a593Smuzhiyun if (ret)
2037*4882a593Smuzhiyun goto error;
2038*4882a593Smuzhiyun
2039*4882a593Smuzhiyun if (wait_for_response(hbus->hdev, &comp_pkt.host_event))
2040*4882a593Smuzhiyun goto error;
2041*4882a593Smuzhiyun
2042*4882a593Smuzhiyun hpdev->desc = *desc;
2043*4882a593Smuzhiyun refcount_set(&hpdev->refs, 1);
2044*4882a593Smuzhiyun get_pcichild(hpdev);
2045*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun list_add_tail(&hpdev->list_entry, &hbus->children);
2048*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2049*4882a593Smuzhiyun return hpdev;
2050*4882a593Smuzhiyun
2051*4882a593Smuzhiyun error:
2052*4882a593Smuzhiyun kfree(hpdev);
2053*4882a593Smuzhiyun return NULL;
2054*4882a593Smuzhiyun }
2055*4882a593Smuzhiyun
2056*4882a593Smuzhiyun /**
2057*4882a593Smuzhiyun * get_pcichild_wslot() - Find device from slot
2058*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2059*4882a593Smuzhiyun * @wslot: Location on the bus
2060*4882a593Smuzhiyun *
2061*4882a593Smuzhiyun * This function looks up a PCI device and returns the internal
2062*4882a593Smuzhiyun * representation of it. It acquires a reference on it, so that
2063*4882a593Smuzhiyun * the device won't be deleted while somebody is using it. The
2064*4882a593Smuzhiyun * caller is responsible for calling put_pcichild() to release
2065*4882a593Smuzhiyun * this reference.
2066*4882a593Smuzhiyun *
2067*4882a593Smuzhiyun * Return: Internal representation of a PCI device
2068*4882a593Smuzhiyun */
get_pcichild_wslot(struct hv_pcibus_device * hbus,u32 wslot)2069*4882a593Smuzhiyun static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
2070*4882a593Smuzhiyun u32 wslot)
2071*4882a593Smuzhiyun {
2072*4882a593Smuzhiyun unsigned long flags;
2073*4882a593Smuzhiyun struct hv_pci_dev *iter, *hpdev = NULL;
2074*4882a593Smuzhiyun
2075*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2076*4882a593Smuzhiyun list_for_each_entry(iter, &hbus->children, list_entry) {
2077*4882a593Smuzhiyun if (iter->desc.win_slot.slot == wslot) {
2078*4882a593Smuzhiyun hpdev = iter;
2079*4882a593Smuzhiyun get_pcichild(hpdev);
2080*4882a593Smuzhiyun break;
2081*4882a593Smuzhiyun }
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2084*4882a593Smuzhiyun
2085*4882a593Smuzhiyun return hpdev;
2086*4882a593Smuzhiyun }
2087*4882a593Smuzhiyun
2088*4882a593Smuzhiyun /**
2089*4882a593Smuzhiyun * pci_devices_present_work() - Handle new list of child devices
2090*4882a593Smuzhiyun * @work: Work struct embedded in struct hv_dr_work
2091*4882a593Smuzhiyun *
2092*4882a593Smuzhiyun * "Bus Relations" is the Windows term for "children of this
2093*4882a593Smuzhiyun * bus." The terminology is preserved here for people trying to
2094*4882a593Smuzhiyun * debug the interaction between Hyper-V and Linux. This
2095*4882a593Smuzhiyun * function is called when the parent partition reports a list
2096*4882a593Smuzhiyun * of functions that should be observed under this PCI Express
2097*4882a593Smuzhiyun * port (bus).
2098*4882a593Smuzhiyun *
2099*4882a593Smuzhiyun * This function updates the list, and must tolerate being
2100*4882a593Smuzhiyun * called multiple times with the same information. The typical
2101*4882a593Smuzhiyun * number of child devices is one, with very atypical cases
2102*4882a593Smuzhiyun * involving three or four, so the algorithms used here can be
2103*4882a593Smuzhiyun * simple and inefficient.
2104*4882a593Smuzhiyun *
2105*4882a593Smuzhiyun * It must also treat the omission of a previously observed device as
2106*4882a593Smuzhiyun * notification that the device no longer exists.
2107*4882a593Smuzhiyun *
2108*4882a593Smuzhiyun * Note that this function is serialized with hv_eject_device_work(),
2109*4882a593Smuzhiyun * because both are pushed to the ordered workqueue hbus->wq.
2110*4882a593Smuzhiyun */
pci_devices_present_work(struct work_struct * work)2111*4882a593Smuzhiyun static void pci_devices_present_work(struct work_struct *work)
2112*4882a593Smuzhiyun {
2113*4882a593Smuzhiyun u32 child_no;
2114*4882a593Smuzhiyun bool found;
2115*4882a593Smuzhiyun struct hv_pcidev_description *new_desc;
2116*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
2117*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
2118*4882a593Smuzhiyun struct list_head removed;
2119*4882a593Smuzhiyun struct hv_dr_work *dr_wrk;
2120*4882a593Smuzhiyun struct hv_dr_state *dr = NULL;
2121*4882a593Smuzhiyun unsigned long flags;
2122*4882a593Smuzhiyun
2123*4882a593Smuzhiyun dr_wrk = container_of(work, struct hv_dr_work, wrk);
2124*4882a593Smuzhiyun hbus = dr_wrk->bus;
2125*4882a593Smuzhiyun kfree(dr_wrk);
2126*4882a593Smuzhiyun
2127*4882a593Smuzhiyun INIT_LIST_HEAD(&removed);
2128*4882a593Smuzhiyun
2129*4882a593Smuzhiyun /* Pull this off the queue and process it if it was the last one. */
2130*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2131*4882a593Smuzhiyun while (!list_empty(&hbus->dr_list)) {
2132*4882a593Smuzhiyun dr = list_first_entry(&hbus->dr_list, struct hv_dr_state,
2133*4882a593Smuzhiyun list_entry);
2134*4882a593Smuzhiyun list_del(&dr->list_entry);
2135*4882a593Smuzhiyun
2136*4882a593Smuzhiyun /* Throw this away if the list still has stuff in it. */
2137*4882a593Smuzhiyun if (!list_empty(&hbus->dr_list)) {
2138*4882a593Smuzhiyun kfree(dr);
2139*4882a593Smuzhiyun continue;
2140*4882a593Smuzhiyun }
2141*4882a593Smuzhiyun }
2142*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2143*4882a593Smuzhiyun
2144*4882a593Smuzhiyun if (!dr) {
2145*4882a593Smuzhiyun put_hvpcibus(hbus);
2146*4882a593Smuzhiyun return;
2147*4882a593Smuzhiyun }
2148*4882a593Smuzhiyun
2149*4882a593Smuzhiyun /* First, mark all existing children as reported missing. */
2150*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2151*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
2152*4882a593Smuzhiyun hpdev->reported_missing = true;
2153*4882a593Smuzhiyun }
2154*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun /* Next, add back any reported devices. */
2157*4882a593Smuzhiyun for (child_no = 0; child_no < dr->device_count; child_no++) {
2158*4882a593Smuzhiyun found = false;
2159*4882a593Smuzhiyun new_desc = &dr->func[child_no];
2160*4882a593Smuzhiyun
2161*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2162*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
2163*4882a593Smuzhiyun if ((hpdev->desc.win_slot.slot == new_desc->win_slot.slot) &&
2164*4882a593Smuzhiyun (hpdev->desc.v_id == new_desc->v_id) &&
2165*4882a593Smuzhiyun (hpdev->desc.d_id == new_desc->d_id) &&
2166*4882a593Smuzhiyun (hpdev->desc.ser == new_desc->ser)) {
2167*4882a593Smuzhiyun hpdev->reported_missing = false;
2168*4882a593Smuzhiyun found = true;
2169*4882a593Smuzhiyun }
2170*4882a593Smuzhiyun }
2171*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2172*4882a593Smuzhiyun
2173*4882a593Smuzhiyun if (!found) {
2174*4882a593Smuzhiyun hpdev = new_pcichild_device(hbus, new_desc);
2175*4882a593Smuzhiyun if (!hpdev)
2176*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2177*4882a593Smuzhiyun "couldn't record a child device.\n");
2178*4882a593Smuzhiyun }
2179*4882a593Smuzhiyun }
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun /* Move missing children to a list on the stack. */
2182*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2183*4882a593Smuzhiyun do {
2184*4882a593Smuzhiyun found = false;
2185*4882a593Smuzhiyun list_for_each_entry(hpdev, &hbus->children, list_entry) {
2186*4882a593Smuzhiyun if (hpdev->reported_missing) {
2187*4882a593Smuzhiyun found = true;
2188*4882a593Smuzhiyun put_pcichild(hpdev);
2189*4882a593Smuzhiyun list_move_tail(&hpdev->list_entry, &removed);
2190*4882a593Smuzhiyun break;
2191*4882a593Smuzhiyun }
2192*4882a593Smuzhiyun }
2193*4882a593Smuzhiyun } while (found);
2194*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2195*4882a593Smuzhiyun
2196*4882a593Smuzhiyun /* Delete everything that should no longer exist. */
2197*4882a593Smuzhiyun while (!list_empty(&removed)) {
2198*4882a593Smuzhiyun hpdev = list_first_entry(&removed, struct hv_pci_dev,
2199*4882a593Smuzhiyun list_entry);
2200*4882a593Smuzhiyun list_del(&hpdev->list_entry);
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun if (hpdev->pci_slot)
2203*4882a593Smuzhiyun pci_destroy_slot(hpdev->pci_slot);
2204*4882a593Smuzhiyun
2205*4882a593Smuzhiyun put_pcichild(hpdev);
2206*4882a593Smuzhiyun }
2207*4882a593Smuzhiyun
2208*4882a593Smuzhiyun switch (hbus->state) {
2209*4882a593Smuzhiyun case hv_pcibus_installed:
2210*4882a593Smuzhiyun /*
2211*4882a593Smuzhiyun * Tell the core to rescan bus
2212*4882a593Smuzhiyun * because there may have been changes.
2213*4882a593Smuzhiyun */
2214*4882a593Smuzhiyun pci_lock_rescan_remove();
2215*4882a593Smuzhiyun pci_scan_child_bus(hbus->pci_bus);
2216*4882a593Smuzhiyun hv_pci_assign_numa_node(hbus);
2217*4882a593Smuzhiyun hv_pci_assign_slots(hbus);
2218*4882a593Smuzhiyun pci_unlock_rescan_remove();
2219*4882a593Smuzhiyun break;
2220*4882a593Smuzhiyun
2221*4882a593Smuzhiyun case hv_pcibus_init:
2222*4882a593Smuzhiyun case hv_pcibus_probed:
2223*4882a593Smuzhiyun survey_child_resources(hbus);
2224*4882a593Smuzhiyun break;
2225*4882a593Smuzhiyun
2226*4882a593Smuzhiyun default:
2227*4882a593Smuzhiyun break;
2228*4882a593Smuzhiyun }
2229*4882a593Smuzhiyun
2230*4882a593Smuzhiyun put_hvpcibus(hbus);
2231*4882a593Smuzhiyun kfree(dr);
2232*4882a593Smuzhiyun }
2233*4882a593Smuzhiyun
2234*4882a593Smuzhiyun /**
2235*4882a593Smuzhiyun * hv_pci_start_relations_work() - Queue work to start device discovery
2236*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2237*4882a593Smuzhiyun * @dr: The list of children returned from host
2238*4882a593Smuzhiyun *
2239*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2240*4882a593Smuzhiyun */
hv_pci_start_relations_work(struct hv_pcibus_device * hbus,struct hv_dr_state * dr)2241*4882a593Smuzhiyun static int hv_pci_start_relations_work(struct hv_pcibus_device *hbus,
2242*4882a593Smuzhiyun struct hv_dr_state *dr)
2243*4882a593Smuzhiyun {
2244*4882a593Smuzhiyun struct hv_dr_work *dr_wrk;
2245*4882a593Smuzhiyun unsigned long flags;
2246*4882a593Smuzhiyun bool pending_dr;
2247*4882a593Smuzhiyun
2248*4882a593Smuzhiyun if (hbus->state == hv_pcibus_removing) {
2249*4882a593Smuzhiyun dev_info(&hbus->hdev->device,
2250*4882a593Smuzhiyun "PCI VMBus BUS_RELATIONS: ignored\n");
2251*4882a593Smuzhiyun return -ENOENT;
2252*4882a593Smuzhiyun }
2253*4882a593Smuzhiyun
2254*4882a593Smuzhiyun dr_wrk = kzalloc(sizeof(*dr_wrk), GFP_NOWAIT);
2255*4882a593Smuzhiyun if (!dr_wrk)
2256*4882a593Smuzhiyun return -ENOMEM;
2257*4882a593Smuzhiyun
2258*4882a593Smuzhiyun INIT_WORK(&dr_wrk->wrk, pci_devices_present_work);
2259*4882a593Smuzhiyun dr_wrk->bus = hbus;
2260*4882a593Smuzhiyun
2261*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2262*4882a593Smuzhiyun /*
2263*4882a593Smuzhiyun * If pending_dr is true, we have already queued a work,
2264*4882a593Smuzhiyun * which will see the new dr. Otherwise, we need to
2265*4882a593Smuzhiyun * queue a new work.
2266*4882a593Smuzhiyun */
2267*4882a593Smuzhiyun pending_dr = !list_empty(&hbus->dr_list);
2268*4882a593Smuzhiyun list_add_tail(&dr->list_entry, &hbus->dr_list);
2269*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2270*4882a593Smuzhiyun
2271*4882a593Smuzhiyun if (pending_dr) {
2272*4882a593Smuzhiyun kfree(dr_wrk);
2273*4882a593Smuzhiyun } else {
2274*4882a593Smuzhiyun get_hvpcibus(hbus);
2275*4882a593Smuzhiyun queue_work(hbus->wq, &dr_wrk->wrk);
2276*4882a593Smuzhiyun }
2277*4882a593Smuzhiyun
2278*4882a593Smuzhiyun return 0;
2279*4882a593Smuzhiyun }
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun /**
2282*4882a593Smuzhiyun * hv_pci_devices_present() - Handle list of new children
2283*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2284*4882a593Smuzhiyun * @relations: Packet from host listing children
2285*4882a593Smuzhiyun *
2286*4882a593Smuzhiyun * Process a new list of devices on the bus. The list of devices is
2287*4882a593Smuzhiyun * discovered by VSP and sent to us via VSP message PCI_BUS_RELATIONS,
2288*4882a593Smuzhiyun * whenever a new list of devices for this bus appears.
2289*4882a593Smuzhiyun */
hv_pci_devices_present(struct hv_pcibus_device * hbus,struct pci_bus_relations * relations)2290*4882a593Smuzhiyun static void hv_pci_devices_present(struct hv_pcibus_device *hbus,
2291*4882a593Smuzhiyun struct pci_bus_relations *relations)
2292*4882a593Smuzhiyun {
2293*4882a593Smuzhiyun struct hv_dr_state *dr;
2294*4882a593Smuzhiyun int i;
2295*4882a593Smuzhiyun
2296*4882a593Smuzhiyun dr = kzalloc(struct_size(dr, func, relations->device_count),
2297*4882a593Smuzhiyun GFP_NOWAIT);
2298*4882a593Smuzhiyun if (!dr)
2299*4882a593Smuzhiyun return;
2300*4882a593Smuzhiyun
2301*4882a593Smuzhiyun dr->device_count = relations->device_count;
2302*4882a593Smuzhiyun for (i = 0; i < dr->device_count; i++) {
2303*4882a593Smuzhiyun dr->func[i].v_id = relations->func[i].v_id;
2304*4882a593Smuzhiyun dr->func[i].d_id = relations->func[i].d_id;
2305*4882a593Smuzhiyun dr->func[i].rev = relations->func[i].rev;
2306*4882a593Smuzhiyun dr->func[i].prog_intf = relations->func[i].prog_intf;
2307*4882a593Smuzhiyun dr->func[i].subclass = relations->func[i].subclass;
2308*4882a593Smuzhiyun dr->func[i].base_class = relations->func[i].base_class;
2309*4882a593Smuzhiyun dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2310*4882a593Smuzhiyun dr->func[i].win_slot = relations->func[i].win_slot;
2311*4882a593Smuzhiyun dr->func[i].ser = relations->func[i].ser;
2312*4882a593Smuzhiyun }
2313*4882a593Smuzhiyun
2314*4882a593Smuzhiyun if (hv_pci_start_relations_work(hbus, dr))
2315*4882a593Smuzhiyun kfree(dr);
2316*4882a593Smuzhiyun }
2317*4882a593Smuzhiyun
2318*4882a593Smuzhiyun /**
2319*4882a593Smuzhiyun * hv_pci_devices_present2() - Handle list of new children
2320*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2321*4882a593Smuzhiyun * @relations: Packet from host listing children
2322*4882a593Smuzhiyun *
2323*4882a593Smuzhiyun * This function is the v2 version of hv_pci_devices_present()
2324*4882a593Smuzhiyun */
hv_pci_devices_present2(struct hv_pcibus_device * hbus,struct pci_bus_relations2 * relations)2325*4882a593Smuzhiyun static void hv_pci_devices_present2(struct hv_pcibus_device *hbus,
2326*4882a593Smuzhiyun struct pci_bus_relations2 *relations)
2327*4882a593Smuzhiyun {
2328*4882a593Smuzhiyun struct hv_dr_state *dr;
2329*4882a593Smuzhiyun int i;
2330*4882a593Smuzhiyun
2331*4882a593Smuzhiyun dr = kzalloc(struct_size(dr, func, relations->device_count),
2332*4882a593Smuzhiyun GFP_NOWAIT);
2333*4882a593Smuzhiyun if (!dr)
2334*4882a593Smuzhiyun return;
2335*4882a593Smuzhiyun
2336*4882a593Smuzhiyun dr->device_count = relations->device_count;
2337*4882a593Smuzhiyun for (i = 0; i < dr->device_count; i++) {
2338*4882a593Smuzhiyun dr->func[i].v_id = relations->func[i].v_id;
2339*4882a593Smuzhiyun dr->func[i].d_id = relations->func[i].d_id;
2340*4882a593Smuzhiyun dr->func[i].rev = relations->func[i].rev;
2341*4882a593Smuzhiyun dr->func[i].prog_intf = relations->func[i].prog_intf;
2342*4882a593Smuzhiyun dr->func[i].subclass = relations->func[i].subclass;
2343*4882a593Smuzhiyun dr->func[i].base_class = relations->func[i].base_class;
2344*4882a593Smuzhiyun dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2345*4882a593Smuzhiyun dr->func[i].win_slot = relations->func[i].win_slot;
2346*4882a593Smuzhiyun dr->func[i].ser = relations->func[i].ser;
2347*4882a593Smuzhiyun dr->func[i].flags = relations->func[i].flags;
2348*4882a593Smuzhiyun dr->func[i].virtual_numa_node =
2349*4882a593Smuzhiyun relations->func[i].virtual_numa_node;
2350*4882a593Smuzhiyun }
2351*4882a593Smuzhiyun
2352*4882a593Smuzhiyun if (hv_pci_start_relations_work(hbus, dr))
2353*4882a593Smuzhiyun kfree(dr);
2354*4882a593Smuzhiyun }
2355*4882a593Smuzhiyun
2356*4882a593Smuzhiyun /**
2357*4882a593Smuzhiyun * hv_eject_device_work() - Asynchronously handles ejection
2358*4882a593Smuzhiyun * @work: Work struct embedded in internal device struct
2359*4882a593Smuzhiyun *
2360*4882a593Smuzhiyun * This function handles ejecting a device. Windows will
2361*4882a593Smuzhiyun * attempt to gracefully eject a device, waiting 60 seconds to
2362*4882a593Smuzhiyun * hear back from the guest OS that this completed successfully.
2363*4882a593Smuzhiyun * If this timer expires, the device will be forcibly removed.
2364*4882a593Smuzhiyun */
hv_eject_device_work(struct work_struct * work)2365*4882a593Smuzhiyun static void hv_eject_device_work(struct work_struct *work)
2366*4882a593Smuzhiyun {
2367*4882a593Smuzhiyun struct pci_eject_response *ejct_pkt;
2368*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
2369*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
2370*4882a593Smuzhiyun struct pci_dev *pdev;
2371*4882a593Smuzhiyun unsigned long flags;
2372*4882a593Smuzhiyun int wslot;
2373*4882a593Smuzhiyun struct {
2374*4882a593Smuzhiyun struct pci_packet pkt;
2375*4882a593Smuzhiyun u8 buffer[sizeof(struct pci_eject_response)];
2376*4882a593Smuzhiyun } ctxt;
2377*4882a593Smuzhiyun
2378*4882a593Smuzhiyun hpdev = container_of(work, struct hv_pci_dev, wrk);
2379*4882a593Smuzhiyun hbus = hpdev->hbus;
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun WARN_ON(hpdev->state != hv_pcichild_ejecting);
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun /*
2384*4882a593Smuzhiyun * Ejection can come before or after the PCI bus has been set up, so
2385*4882a593Smuzhiyun * attempt to find it and tear down the bus state, if it exists. This
2386*4882a593Smuzhiyun * must be done without constructs like pci_domain_nr(hbus->pci_bus)
2387*4882a593Smuzhiyun * because hbus->pci_bus may not exist yet.
2388*4882a593Smuzhiyun */
2389*4882a593Smuzhiyun wslot = wslot_to_devfn(hpdev->desc.win_slot.slot);
2390*4882a593Smuzhiyun pdev = pci_get_domain_bus_and_slot(hbus->sysdata.domain, 0, wslot);
2391*4882a593Smuzhiyun if (pdev) {
2392*4882a593Smuzhiyun pci_lock_rescan_remove();
2393*4882a593Smuzhiyun pci_stop_and_remove_bus_device(pdev);
2394*4882a593Smuzhiyun pci_dev_put(pdev);
2395*4882a593Smuzhiyun pci_unlock_rescan_remove();
2396*4882a593Smuzhiyun }
2397*4882a593Smuzhiyun
2398*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
2399*4882a593Smuzhiyun list_del(&hpdev->list_entry);
2400*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun if (hpdev->pci_slot)
2403*4882a593Smuzhiyun pci_destroy_slot(hpdev->pci_slot);
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun memset(&ctxt, 0, sizeof(ctxt));
2406*4882a593Smuzhiyun ejct_pkt = (struct pci_eject_response *)&ctxt.pkt.message;
2407*4882a593Smuzhiyun ejct_pkt->message_type.type = PCI_EJECTION_COMPLETE;
2408*4882a593Smuzhiyun ejct_pkt->wslot.slot = hpdev->desc.win_slot.slot;
2409*4882a593Smuzhiyun vmbus_sendpacket(hbus->hdev->channel, ejct_pkt,
2410*4882a593Smuzhiyun sizeof(*ejct_pkt), (unsigned long)&ctxt.pkt,
2411*4882a593Smuzhiyun VM_PKT_DATA_INBAND, 0);
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun /* For the get_pcichild() in hv_pci_eject_device() */
2414*4882a593Smuzhiyun put_pcichild(hpdev);
2415*4882a593Smuzhiyun /* For the two refs got in new_pcichild_device() */
2416*4882a593Smuzhiyun put_pcichild(hpdev);
2417*4882a593Smuzhiyun put_pcichild(hpdev);
2418*4882a593Smuzhiyun /* hpdev has been freed. Do not use it any more. */
2419*4882a593Smuzhiyun
2420*4882a593Smuzhiyun put_hvpcibus(hbus);
2421*4882a593Smuzhiyun }
2422*4882a593Smuzhiyun
2423*4882a593Smuzhiyun /**
2424*4882a593Smuzhiyun * hv_pci_eject_device() - Handles device ejection
2425*4882a593Smuzhiyun * @hpdev: Internal device tracking struct
2426*4882a593Smuzhiyun *
2427*4882a593Smuzhiyun * This function is invoked when an ejection packet arrives. It
2428*4882a593Smuzhiyun * just schedules work so that we don't re-enter the packet
2429*4882a593Smuzhiyun * delivery code handling the ejection.
2430*4882a593Smuzhiyun */
hv_pci_eject_device(struct hv_pci_dev * hpdev)2431*4882a593Smuzhiyun static void hv_pci_eject_device(struct hv_pci_dev *hpdev)
2432*4882a593Smuzhiyun {
2433*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hpdev->hbus;
2434*4882a593Smuzhiyun struct hv_device *hdev = hbus->hdev;
2435*4882a593Smuzhiyun
2436*4882a593Smuzhiyun if (hbus->state == hv_pcibus_removing) {
2437*4882a593Smuzhiyun dev_info(&hdev->device, "PCI VMBus EJECT: ignored\n");
2438*4882a593Smuzhiyun return;
2439*4882a593Smuzhiyun }
2440*4882a593Smuzhiyun
2441*4882a593Smuzhiyun hpdev->state = hv_pcichild_ejecting;
2442*4882a593Smuzhiyun get_pcichild(hpdev);
2443*4882a593Smuzhiyun INIT_WORK(&hpdev->wrk, hv_eject_device_work);
2444*4882a593Smuzhiyun get_hvpcibus(hbus);
2445*4882a593Smuzhiyun queue_work(hbus->wq, &hpdev->wrk);
2446*4882a593Smuzhiyun }
2447*4882a593Smuzhiyun
2448*4882a593Smuzhiyun /**
2449*4882a593Smuzhiyun * hv_pci_onchannelcallback() - Handles incoming packets
2450*4882a593Smuzhiyun * @context: Internal bus tracking struct
2451*4882a593Smuzhiyun *
2452*4882a593Smuzhiyun * This function is invoked whenever the host sends a packet to
2453*4882a593Smuzhiyun * this channel (which is private to this root PCI bus).
2454*4882a593Smuzhiyun */
hv_pci_onchannelcallback(void * context)2455*4882a593Smuzhiyun static void hv_pci_onchannelcallback(void *context)
2456*4882a593Smuzhiyun {
2457*4882a593Smuzhiyun const int packet_size = 0x100;
2458*4882a593Smuzhiyun int ret;
2459*4882a593Smuzhiyun struct hv_pcibus_device *hbus = context;
2460*4882a593Smuzhiyun u32 bytes_recvd;
2461*4882a593Smuzhiyun u64 req_id;
2462*4882a593Smuzhiyun struct vmpacket_descriptor *desc;
2463*4882a593Smuzhiyun unsigned char *buffer;
2464*4882a593Smuzhiyun int bufferlen = packet_size;
2465*4882a593Smuzhiyun struct pci_packet *comp_packet;
2466*4882a593Smuzhiyun struct pci_response *response;
2467*4882a593Smuzhiyun struct pci_incoming_message *new_message;
2468*4882a593Smuzhiyun struct pci_bus_relations *bus_rel;
2469*4882a593Smuzhiyun struct pci_bus_relations2 *bus_rel2;
2470*4882a593Smuzhiyun struct pci_dev_inval_block *inval;
2471*4882a593Smuzhiyun struct pci_dev_incoming *dev_message;
2472*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
2473*4882a593Smuzhiyun
2474*4882a593Smuzhiyun buffer = kmalloc(bufferlen, GFP_ATOMIC);
2475*4882a593Smuzhiyun if (!buffer)
2476*4882a593Smuzhiyun return;
2477*4882a593Smuzhiyun
2478*4882a593Smuzhiyun while (1) {
2479*4882a593Smuzhiyun ret = vmbus_recvpacket_raw(hbus->hdev->channel, buffer,
2480*4882a593Smuzhiyun bufferlen, &bytes_recvd, &req_id);
2481*4882a593Smuzhiyun
2482*4882a593Smuzhiyun if (ret == -ENOBUFS) {
2483*4882a593Smuzhiyun kfree(buffer);
2484*4882a593Smuzhiyun /* Handle large packet */
2485*4882a593Smuzhiyun bufferlen = bytes_recvd;
2486*4882a593Smuzhiyun buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
2487*4882a593Smuzhiyun if (!buffer)
2488*4882a593Smuzhiyun return;
2489*4882a593Smuzhiyun continue;
2490*4882a593Smuzhiyun }
2491*4882a593Smuzhiyun
2492*4882a593Smuzhiyun /* Zero length indicates there are no more packets. */
2493*4882a593Smuzhiyun if (ret || !bytes_recvd)
2494*4882a593Smuzhiyun break;
2495*4882a593Smuzhiyun
2496*4882a593Smuzhiyun /*
2497*4882a593Smuzhiyun * All incoming packets must be at least as large as a
2498*4882a593Smuzhiyun * response.
2499*4882a593Smuzhiyun */
2500*4882a593Smuzhiyun if (bytes_recvd <= sizeof(struct pci_response))
2501*4882a593Smuzhiyun continue;
2502*4882a593Smuzhiyun desc = (struct vmpacket_descriptor *)buffer;
2503*4882a593Smuzhiyun
2504*4882a593Smuzhiyun switch (desc->type) {
2505*4882a593Smuzhiyun case VM_PKT_COMP:
2506*4882a593Smuzhiyun
2507*4882a593Smuzhiyun /*
2508*4882a593Smuzhiyun * The host is trusted, and thus it's safe to interpret
2509*4882a593Smuzhiyun * this transaction ID as a pointer.
2510*4882a593Smuzhiyun */
2511*4882a593Smuzhiyun comp_packet = (struct pci_packet *)req_id;
2512*4882a593Smuzhiyun response = (struct pci_response *)buffer;
2513*4882a593Smuzhiyun comp_packet->completion_func(comp_packet->compl_ctxt,
2514*4882a593Smuzhiyun response,
2515*4882a593Smuzhiyun bytes_recvd);
2516*4882a593Smuzhiyun break;
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun case VM_PKT_DATA_INBAND:
2519*4882a593Smuzhiyun
2520*4882a593Smuzhiyun new_message = (struct pci_incoming_message *)buffer;
2521*4882a593Smuzhiyun switch (new_message->message_type.type) {
2522*4882a593Smuzhiyun case PCI_BUS_RELATIONS:
2523*4882a593Smuzhiyun
2524*4882a593Smuzhiyun bus_rel = (struct pci_bus_relations *)buffer;
2525*4882a593Smuzhiyun if (bytes_recvd <
2526*4882a593Smuzhiyun struct_size(bus_rel, func,
2527*4882a593Smuzhiyun bus_rel->device_count)) {
2528*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2529*4882a593Smuzhiyun "bus relations too small\n");
2530*4882a593Smuzhiyun break;
2531*4882a593Smuzhiyun }
2532*4882a593Smuzhiyun
2533*4882a593Smuzhiyun hv_pci_devices_present(hbus, bus_rel);
2534*4882a593Smuzhiyun break;
2535*4882a593Smuzhiyun
2536*4882a593Smuzhiyun case PCI_BUS_RELATIONS2:
2537*4882a593Smuzhiyun
2538*4882a593Smuzhiyun bus_rel2 = (struct pci_bus_relations2 *)buffer;
2539*4882a593Smuzhiyun if (bytes_recvd <
2540*4882a593Smuzhiyun struct_size(bus_rel2, func,
2541*4882a593Smuzhiyun bus_rel2->device_count)) {
2542*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2543*4882a593Smuzhiyun "bus relations v2 too small\n");
2544*4882a593Smuzhiyun break;
2545*4882a593Smuzhiyun }
2546*4882a593Smuzhiyun
2547*4882a593Smuzhiyun hv_pci_devices_present2(hbus, bus_rel2);
2548*4882a593Smuzhiyun break;
2549*4882a593Smuzhiyun
2550*4882a593Smuzhiyun case PCI_EJECT:
2551*4882a593Smuzhiyun
2552*4882a593Smuzhiyun dev_message = (struct pci_dev_incoming *)buffer;
2553*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus,
2554*4882a593Smuzhiyun dev_message->wslot.slot);
2555*4882a593Smuzhiyun if (hpdev) {
2556*4882a593Smuzhiyun hv_pci_eject_device(hpdev);
2557*4882a593Smuzhiyun put_pcichild(hpdev);
2558*4882a593Smuzhiyun }
2559*4882a593Smuzhiyun break;
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun case PCI_INVALIDATE_BLOCK:
2562*4882a593Smuzhiyun
2563*4882a593Smuzhiyun inval = (struct pci_dev_inval_block *)buffer;
2564*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus,
2565*4882a593Smuzhiyun inval->wslot.slot);
2566*4882a593Smuzhiyun if (hpdev) {
2567*4882a593Smuzhiyun if (hpdev->block_invalidate) {
2568*4882a593Smuzhiyun hpdev->block_invalidate(
2569*4882a593Smuzhiyun hpdev->invalidate_context,
2570*4882a593Smuzhiyun inval->block_mask);
2571*4882a593Smuzhiyun }
2572*4882a593Smuzhiyun put_pcichild(hpdev);
2573*4882a593Smuzhiyun }
2574*4882a593Smuzhiyun break;
2575*4882a593Smuzhiyun
2576*4882a593Smuzhiyun default:
2577*4882a593Smuzhiyun dev_warn(&hbus->hdev->device,
2578*4882a593Smuzhiyun "Unimplemented protocol message %x\n",
2579*4882a593Smuzhiyun new_message->message_type.type);
2580*4882a593Smuzhiyun break;
2581*4882a593Smuzhiyun }
2582*4882a593Smuzhiyun break;
2583*4882a593Smuzhiyun
2584*4882a593Smuzhiyun default:
2585*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2586*4882a593Smuzhiyun "unhandled packet type %d, tid %llx len %d\n",
2587*4882a593Smuzhiyun desc->type, req_id, bytes_recvd);
2588*4882a593Smuzhiyun break;
2589*4882a593Smuzhiyun }
2590*4882a593Smuzhiyun }
2591*4882a593Smuzhiyun
2592*4882a593Smuzhiyun kfree(buffer);
2593*4882a593Smuzhiyun }
2594*4882a593Smuzhiyun
2595*4882a593Smuzhiyun /**
2596*4882a593Smuzhiyun * hv_pci_protocol_negotiation() - Set up protocol
2597*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus.
2598*4882a593Smuzhiyun * @version: Array of supported channel protocol versions in
2599*4882a593Smuzhiyun * the order of probing - highest go first.
2600*4882a593Smuzhiyun * @num_version: Number of elements in the version array.
2601*4882a593Smuzhiyun *
2602*4882a593Smuzhiyun * This driver is intended to support running on Windows 10
2603*4882a593Smuzhiyun * (server) and later versions. It will not run on earlier
2604*4882a593Smuzhiyun * versions, as they assume that many of the operations which
2605*4882a593Smuzhiyun * Linux needs accomplished with a spinlock held were done via
2606*4882a593Smuzhiyun * asynchronous messaging via VMBus. Windows 10 increases the
2607*4882a593Smuzhiyun * surface area of PCI emulation so that these actions can take
2608*4882a593Smuzhiyun * place by suspending a virtual processor for their duration.
2609*4882a593Smuzhiyun *
2610*4882a593Smuzhiyun * This function negotiates the channel protocol version,
2611*4882a593Smuzhiyun * failing if the host doesn't support the necessary protocol
2612*4882a593Smuzhiyun * level.
2613*4882a593Smuzhiyun */
hv_pci_protocol_negotiation(struct hv_device * hdev,enum pci_protocol_version_t version[],int num_version)2614*4882a593Smuzhiyun static int hv_pci_protocol_negotiation(struct hv_device *hdev,
2615*4882a593Smuzhiyun enum pci_protocol_version_t version[],
2616*4882a593Smuzhiyun int num_version)
2617*4882a593Smuzhiyun {
2618*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2619*4882a593Smuzhiyun struct pci_version_request *version_req;
2620*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
2621*4882a593Smuzhiyun struct pci_packet *pkt;
2622*4882a593Smuzhiyun int ret;
2623*4882a593Smuzhiyun int i;
2624*4882a593Smuzhiyun
2625*4882a593Smuzhiyun /*
2626*4882a593Smuzhiyun * Initiate the handshake with the host and negotiate
2627*4882a593Smuzhiyun * a version that the host can support. We start with the
2628*4882a593Smuzhiyun * highest version number and go down if the host cannot
2629*4882a593Smuzhiyun * support it.
2630*4882a593Smuzhiyun */
2631*4882a593Smuzhiyun pkt = kzalloc(sizeof(*pkt) + sizeof(*version_req), GFP_KERNEL);
2632*4882a593Smuzhiyun if (!pkt)
2633*4882a593Smuzhiyun return -ENOMEM;
2634*4882a593Smuzhiyun
2635*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
2636*4882a593Smuzhiyun pkt->completion_func = hv_pci_generic_compl;
2637*4882a593Smuzhiyun pkt->compl_ctxt = &comp_pkt;
2638*4882a593Smuzhiyun version_req = (struct pci_version_request *)&pkt->message;
2639*4882a593Smuzhiyun version_req->message_type.type = PCI_QUERY_PROTOCOL_VERSION;
2640*4882a593Smuzhiyun
2641*4882a593Smuzhiyun for (i = 0; i < num_version; i++) {
2642*4882a593Smuzhiyun version_req->protocol_version = version[i];
2643*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, version_req,
2644*4882a593Smuzhiyun sizeof(struct pci_version_request),
2645*4882a593Smuzhiyun (unsigned long)pkt, VM_PKT_DATA_INBAND,
2646*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2647*4882a593Smuzhiyun if (!ret)
2648*4882a593Smuzhiyun ret = wait_for_response(hdev, &comp_pkt.host_event);
2649*4882a593Smuzhiyun
2650*4882a593Smuzhiyun if (ret) {
2651*4882a593Smuzhiyun dev_err(&hdev->device,
2652*4882a593Smuzhiyun "PCI Pass-through VSP failed to request version: %d",
2653*4882a593Smuzhiyun ret);
2654*4882a593Smuzhiyun goto exit;
2655*4882a593Smuzhiyun }
2656*4882a593Smuzhiyun
2657*4882a593Smuzhiyun if (comp_pkt.completion_status >= 0) {
2658*4882a593Smuzhiyun hbus->protocol_version = version[i];
2659*4882a593Smuzhiyun dev_info(&hdev->device,
2660*4882a593Smuzhiyun "PCI VMBus probing: Using version %#x\n",
2661*4882a593Smuzhiyun hbus->protocol_version);
2662*4882a593Smuzhiyun goto exit;
2663*4882a593Smuzhiyun }
2664*4882a593Smuzhiyun
2665*4882a593Smuzhiyun if (comp_pkt.completion_status != STATUS_REVISION_MISMATCH) {
2666*4882a593Smuzhiyun dev_err(&hdev->device,
2667*4882a593Smuzhiyun "PCI Pass-through VSP failed version request: %#x",
2668*4882a593Smuzhiyun comp_pkt.completion_status);
2669*4882a593Smuzhiyun ret = -EPROTO;
2670*4882a593Smuzhiyun goto exit;
2671*4882a593Smuzhiyun }
2672*4882a593Smuzhiyun
2673*4882a593Smuzhiyun reinit_completion(&comp_pkt.host_event);
2674*4882a593Smuzhiyun }
2675*4882a593Smuzhiyun
2676*4882a593Smuzhiyun dev_err(&hdev->device,
2677*4882a593Smuzhiyun "PCI pass-through VSP failed to find supported version");
2678*4882a593Smuzhiyun ret = -EPROTO;
2679*4882a593Smuzhiyun
2680*4882a593Smuzhiyun exit:
2681*4882a593Smuzhiyun kfree(pkt);
2682*4882a593Smuzhiyun return ret;
2683*4882a593Smuzhiyun }
2684*4882a593Smuzhiyun
2685*4882a593Smuzhiyun /**
2686*4882a593Smuzhiyun * hv_pci_free_bridge_windows() - Release memory regions for the
2687*4882a593Smuzhiyun * bus
2688*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2689*4882a593Smuzhiyun */
hv_pci_free_bridge_windows(struct hv_pcibus_device * hbus)2690*4882a593Smuzhiyun static void hv_pci_free_bridge_windows(struct hv_pcibus_device *hbus)
2691*4882a593Smuzhiyun {
2692*4882a593Smuzhiyun /*
2693*4882a593Smuzhiyun * Set the resources back to the way they looked when they
2694*4882a593Smuzhiyun * were allocated by setting IORESOURCE_BUSY again.
2695*4882a593Smuzhiyun */
2696*4882a593Smuzhiyun
2697*4882a593Smuzhiyun if (hbus->low_mmio_space && hbus->low_mmio_res) {
2698*4882a593Smuzhiyun hbus->low_mmio_res->flags |= IORESOURCE_BUSY;
2699*4882a593Smuzhiyun vmbus_free_mmio(hbus->low_mmio_res->start,
2700*4882a593Smuzhiyun resource_size(hbus->low_mmio_res));
2701*4882a593Smuzhiyun }
2702*4882a593Smuzhiyun
2703*4882a593Smuzhiyun if (hbus->high_mmio_space && hbus->high_mmio_res) {
2704*4882a593Smuzhiyun hbus->high_mmio_res->flags |= IORESOURCE_BUSY;
2705*4882a593Smuzhiyun vmbus_free_mmio(hbus->high_mmio_res->start,
2706*4882a593Smuzhiyun resource_size(hbus->high_mmio_res));
2707*4882a593Smuzhiyun }
2708*4882a593Smuzhiyun }
2709*4882a593Smuzhiyun
2710*4882a593Smuzhiyun /**
2711*4882a593Smuzhiyun * hv_pci_allocate_bridge_windows() - Allocate memory regions
2712*4882a593Smuzhiyun * for the bus
2713*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2714*4882a593Smuzhiyun *
2715*4882a593Smuzhiyun * This function calls vmbus_allocate_mmio(), which is itself a
2716*4882a593Smuzhiyun * bit of a compromise. Ideally, we might change the pnp layer
2717*4882a593Smuzhiyun * in the kernel such that it comprehends either PCI devices
2718*4882a593Smuzhiyun * which are "grandchildren of ACPI," with some intermediate bus
2719*4882a593Smuzhiyun * node (in this case, VMBus) or change it such that it
2720*4882a593Smuzhiyun * understands VMBus. The pnp layer, however, has been declared
2721*4882a593Smuzhiyun * deprecated, and not subject to change.
2722*4882a593Smuzhiyun *
2723*4882a593Smuzhiyun * The workaround, implemented here, is to ask VMBus to allocate
2724*4882a593Smuzhiyun * MMIO space for this bus. VMBus itself knows which ranges are
2725*4882a593Smuzhiyun * appropriate by looking at its own ACPI objects. Then, after
2726*4882a593Smuzhiyun * these ranges are claimed, they're modified to look like they
2727*4882a593Smuzhiyun * would have looked if the ACPI and pnp code had allocated
2728*4882a593Smuzhiyun * bridge windows. These descriptors have to exist in this form
2729*4882a593Smuzhiyun * in order to satisfy the code which will get invoked when the
2730*4882a593Smuzhiyun * endpoint PCI function driver calls request_mem_region() or
2731*4882a593Smuzhiyun * request_mem_region_exclusive().
2732*4882a593Smuzhiyun *
2733*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2734*4882a593Smuzhiyun */
hv_pci_allocate_bridge_windows(struct hv_pcibus_device * hbus)2735*4882a593Smuzhiyun static int hv_pci_allocate_bridge_windows(struct hv_pcibus_device *hbus)
2736*4882a593Smuzhiyun {
2737*4882a593Smuzhiyun resource_size_t align;
2738*4882a593Smuzhiyun int ret;
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun if (hbus->low_mmio_space) {
2741*4882a593Smuzhiyun align = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
2742*4882a593Smuzhiyun ret = vmbus_allocate_mmio(&hbus->low_mmio_res, hbus->hdev, 0,
2743*4882a593Smuzhiyun (u64)(u32)0xffffffff,
2744*4882a593Smuzhiyun hbus->low_mmio_space,
2745*4882a593Smuzhiyun align, false);
2746*4882a593Smuzhiyun if (ret) {
2747*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2748*4882a593Smuzhiyun "Need %#llx of low MMIO space. Consider reconfiguring the VM.\n",
2749*4882a593Smuzhiyun hbus->low_mmio_space);
2750*4882a593Smuzhiyun return ret;
2751*4882a593Smuzhiyun }
2752*4882a593Smuzhiyun
2753*4882a593Smuzhiyun /* Modify this resource to become a bridge window. */
2754*4882a593Smuzhiyun hbus->low_mmio_res->flags |= IORESOURCE_WINDOW;
2755*4882a593Smuzhiyun hbus->low_mmio_res->flags &= ~IORESOURCE_BUSY;
2756*4882a593Smuzhiyun pci_add_resource(&hbus->resources_for_children,
2757*4882a593Smuzhiyun hbus->low_mmio_res);
2758*4882a593Smuzhiyun }
2759*4882a593Smuzhiyun
2760*4882a593Smuzhiyun if (hbus->high_mmio_space) {
2761*4882a593Smuzhiyun align = 1ULL << (63 - __builtin_clzll(hbus->high_mmio_space));
2762*4882a593Smuzhiyun ret = vmbus_allocate_mmio(&hbus->high_mmio_res, hbus->hdev,
2763*4882a593Smuzhiyun 0x100000000, -1,
2764*4882a593Smuzhiyun hbus->high_mmio_space, align,
2765*4882a593Smuzhiyun false);
2766*4882a593Smuzhiyun if (ret) {
2767*4882a593Smuzhiyun dev_err(&hbus->hdev->device,
2768*4882a593Smuzhiyun "Need %#llx of high MMIO space. Consider reconfiguring the VM.\n",
2769*4882a593Smuzhiyun hbus->high_mmio_space);
2770*4882a593Smuzhiyun goto release_low_mmio;
2771*4882a593Smuzhiyun }
2772*4882a593Smuzhiyun
2773*4882a593Smuzhiyun /* Modify this resource to become a bridge window. */
2774*4882a593Smuzhiyun hbus->high_mmio_res->flags |= IORESOURCE_WINDOW;
2775*4882a593Smuzhiyun hbus->high_mmio_res->flags &= ~IORESOURCE_BUSY;
2776*4882a593Smuzhiyun pci_add_resource(&hbus->resources_for_children,
2777*4882a593Smuzhiyun hbus->high_mmio_res);
2778*4882a593Smuzhiyun }
2779*4882a593Smuzhiyun
2780*4882a593Smuzhiyun return 0;
2781*4882a593Smuzhiyun
2782*4882a593Smuzhiyun release_low_mmio:
2783*4882a593Smuzhiyun if (hbus->low_mmio_res) {
2784*4882a593Smuzhiyun vmbus_free_mmio(hbus->low_mmio_res->start,
2785*4882a593Smuzhiyun resource_size(hbus->low_mmio_res));
2786*4882a593Smuzhiyun }
2787*4882a593Smuzhiyun
2788*4882a593Smuzhiyun return ret;
2789*4882a593Smuzhiyun }
2790*4882a593Smuzhiyun
2791*4882a593Smuzhiyun /**
2792*4882a593Smuzhiyun * hv_allocate_config_window() - Find MMIO space for PCI Config
2793*4882a593Smuzhiyun * @hbus: Root PCI bus, as understood by this driver
2794*4882a593Smuzhiyun *
2795*4882a593Smuzhiyun * This function claims memory-mapped I/O space for accessing
2796*4882a593Smuzhiyun * configuration space for the functions on this bus.
2797*4882a593Smuzhiyun *
2798*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2799*4882a593Smuzhiyun */
hv_allocate_config_window(struct hv_pcibus_device * hbus)2800*4882a593Smuzhiyun static int hv_allocate_config_window(struct hv_pcibus_device *hbus)
2801*4882a593Smuzhiyun {
2802*4882a593Smuzhiyun int ret;
2803*4882a593Smuzhiyun
2804*4882a593Smuzhiyun /*
2805*4882a593Smuzhiyun * Set up a region of MMIO space to use for accessing configuration
2806*4882a593Smuzhiyun * space.
2807*4882a593Smuzhiyun */
2808*4882a593Smuzhiyun ret = vmbus_allocate_mmio(&hbus->mem_config, hbus->hdev, 0, -1,
2809*4882a593Smuzhiyun PCI_CONFIG_MMIO_LENGTH, 0x1000, false);
2810*4882a593Smuzhiyun if (ret)
2811*4882a593Smuzhiyun return ret;
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun /*
2814*4882a593Smuzhiyun * vmbus_allocate_mmio() gets used for allocating both device endpoint
2815*4882a593Smuzhiyun * resource claims (those which cannot be overlapped) and the ranges
2816*4882a593Smuzhiyun * which are valid for the children of this bus, which are intended
2817*4882a593Smuzhiyun * to be overlapped by those children. Set the flag on this claim
2818*4882a593Smuzhiyun * meaning that this region can't be overlapped.
2819*4882a593Smuzhiyun */
2820*4882a593Smuzhiyun
2821*4882a593Smuzhiyun hbus->mem_config->flags |= IORESOURCE_BUSY;
2822*4882a593Smuzhiyun
2823*4882a593Smuzhiyun return 0;
2824*4882a593Smuzhiyun }
2825*4882a593Smuzhiyun
hv_free_config_window(struct hv_pcibus_device * hbus)2826*4882a593Smuzhiyun static void hv_free_config_window(struct hv_pcibus_device *hbus)
2827*4882a593Smuzhiyun {
2828*4882a593Smuzhiyun vmbus_free_mmio(hbus->mem_config->start, PCI_CONFIG_MMIO_LENGTH);
2829*4882a593Smuzhiyun }
2830*4882a593Smuzhiyun
2831*4882a593Smuzhiyun static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs);
2832*4882a593Smuzhiyun
2833*4882a593Smuzhiyun /**
2834*4882a593Smuzhiyun * hv_pci_enter_d0() - Bring the "bus" into the D0 power state
2835*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
2836*4882a593Smuzhiyun *
2837*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2838*4882a593Smuzhiyun */
hv_pci_enter_d0(struct hv_device * hdev)2839*4882a593Smuzhiyun static int hv_pci_enter_d0(struct hv_device *hdev)
2840*4882a593Smuzhiyun {
2841*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2842*4882a593Smuzhiyun struct pci_bus_d0_entry *d0_entry;
2843*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
2844*4882a593Smuzhiyun struct pci_packet *pkt;
2845*4882a593Smuzhiyun int ret;
2846*4882a593Smuzhiyun
2847*4882a593Smuzhiyun /*
2848*4882a593Smuzhiyun * Tell the host that the bus is ready to use, and moved into the
2849*4882a593Smuzhiyun * powered-on state. This includes telling the host which region
2850*4882a593Smuzhiyun * of memory-mapped I/O space has been chosen for configuration space
2851*4882a593Smuzhiyun * access.
2852*4882a593Smuzhiyun */
2853*4882a593Smuzhiyun pkt = kzalloc(sizeof(*pkt) + sizeof(*d0_entry), GFP_KERNEL);
2854*4882a593Smuzhiyun if (!pkt)
2855*4882a593Smuzhiyun return -ENOMEM;
2856*4882a593Smuzhiyun
2857*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
2858*4882a593Smuzhiyun pkt->completion_func = hv_pci_generic_compl;
2859*4882a593Smuzhiyun pkt->compl_ctxt = &comp_pkt;
2860*4882a593Smuzhiyun d0_entry = (struct pci_bus_d0_entry *)&pkt->message;
2861*4882a593Smuzhiyun d0_entry->message_type.type = PCI_BUS_D0ENTRY;
2862*4882a593Smuzhiyun d0_entry->mmio_base = hbus->mem_config->start;
2863*4882a593Smuzhiyun
2864*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, d0_entry, sizeof(*d0_entry),
2865*4882a593Smuzhiyun (unsigned long)pkt, VM_PKT_DATA_INBAND,
2866*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2867*4882a593Smuzhiyun if (!ret)
2868*4882a593Smuzhiyun ret = wait_for_response(hdev, &comp_pkt.host_event);
2869*4882a593Smuzhiyun
2870*4882a593Smuzhiyun if (ret)
2871*4882a593Smuzhiyun goto exit;
2872*4882a593Smuzhiyun
2873*4882a593Smuzhiyun if (comp_pkt.completion_status < 0) {
2874*4882a593Smuzhiyun dev_err(&hdev->device,
2875*4882a593Smuzhiyun "PCI Pass-through VSP failed D0 Entry with status %x\n",
2876*4882a593Smuzhiyun comp_pkt.completion_status);
2877*4882a593Smuzhiyun ret = -EPROTO;
2878*4882a593Smuzhiyun goto exit;
2879*4882a593Smuzhiyun }
2880*4882a593Smuzhiyun
2881*4882a593Smuzhiyun ret = 0;
2882*4882a593Smuzhiyun
2883*4882a593Smuzhiyun exit:
2884*4882a593Smuzhiyun kfree(pkt);
2885*4882a593Smuzhiyun return ret;
2886*4882a593Smuzhiyun }
2887*4882a593Smuzhiyun
2888*4882a593Smuzhiyun /**
2889*4882a593Smuzhiyun * hv_pci_query_relations() - Ask host to send list of child
2890*4882a593Smuzhiyun * devices
2891*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
2892*4882a593Smuzhiyun *
2893*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2894*4882a593Smuzhiyun */
hv_pci_query_relations(struct hv_device * hdev)2895*4882a593Smuzhiyun static int hv_pci_query_relations(struct hv_device *hdev)
2896*4882a593Smuzhiyun {
2897*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2898*4882a593Smuzhiyun struct pci_message message;
2899*4882a593Smuzhiyun struct completion comp;
2900*4882a593Smuzhiyun int ret;
2901*4882a593Smuzhiyun
2902*4882a593Smuzhiyun /* Ask the host to send along the list of child devices */
2903*4882a593Smuzhiyun init_completion(&comp);
2904*4882a593Smuzhiyun if (cmpxchg(&hbus->survey_event, NULL, &comp))
2905*4882a593Smuzhiyun return -ENOTEMPTY;
2906*4882a593Smuzhiyun
2907*4882a593Smuzhiyun memset(&message, 0, sizeof(message));
2908*4882a593Smuzhiyun message.type = PCI_QUERY_BUS_RELATIONS;
2909*4882a593Smuzhiyun
2910*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, &message, sizeof(message),
2911*4882a593Smuzhiyun 0, VM_PKT_DATA_INBAND, 0);
2912*4882a593Smuzhiyun if (!ret)
2913*4882a593Smuzhiyun ret = wait_for_response(hdev, &comp);
2914*4882a593Smuzhiyun
2915*4882a593Smuzhiyun return ret;
2916*4882a593Smuzhiyun }
2917*4882a593Smuzhiyun
2918*4882a593Smuzhiyun /**
2919*4882a593Smuzhiyun * hv_send_resources_allocated() - Report local resource choices
2920*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
2921*4882a593Smuzhiyun *
2922*4882a593Smuzhiyun * The host OS is expecting to be sent a request as a message
2923*4882a593Smuzhiyun * which contains all the resources that the device will use.
2924*4882a593Smuzhiyun * The response contains those same resources, "translated"
2925*4882a593Smuzhiyun * which is to say, the values which should be used by the
2926*4882a593Smuzhiyun * hardware, when it delivers an interrupt. (MMIO resources are
2927*4882a593Smuzhiyun * used in local terms.) This is nice for Windows, and lines up
2928*4882a593Smuzhiyun * with the FDO/PDO split, which doesn't exist in Linux. Linux
2929*4882a593Smuzhiyun * is deeply expecting to scan an emulated PCI configuration
2930*4882a593Smuzhiyun * space. So this message is sent here only to drive the state
2931*4882a593Smuzhiyun * machine on the host forward.
2932*4882a593Smuzhiyun *
2933*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
2934*4882a593Smuzhiyun */
hv_send_resources_allocated(struct hv_device * hdev)2935*4882a593Smuzhiyun static int hv_send_resources_allocated(struct hv_device *hdev)
2936*4882a593Smuzhiyun {
2937*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
2938*4882a593Smuzhiyun struct pci_resources_assigned *res_assigned;
2939*4882a593Smuzhiyun struct pci_resources_assigned2 *res_assigned2;
2940*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
2941*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
2942*4882a593Smuzhiyun struct pci_packet *pkt;
2943*4882a593Smuzhiyun size_t size_res;
2944*4882a593Smuzhiyun int wslot;
2945*4882a593Smuzhiyun int ret;
2946*4882a593Smuzhiyun
2947*4882a593Smuzhiyun size_res = (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2)
2948*4882a593Smuzhiyun ? sizeof(*res_assigned) : sizeof(*res_assigned2);
2949*4882a593Smuzhiyun
2950*4882a593Smuzhiyun pkt = kmalloc(sizeof(*pkt) + size_res, GFP_KERNEL);
2951*4882a593Smuzhiyun if (!pkt)
2952*4882a593Smuzhiyun return -ENOMEM;
2953*4882a593Smuzhiyun
2954*4882a593Smuzhiyun ret = 0;
2955*4882a593Smuzhiyun
2956*4882a593Smuzhiyun for (wslot = 0; wslot < 256; wslot++) {
2957*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, wslot);
2958*4882a593Smuzhiyun if (!hpdev)
2959*4882a593Smuzhiyun continue;
2960*4882a593Smuzhiyun
2961*4882a593Smuzhiyun memset(pkt, 0, sizeof(*pkt) + size_res);
2962*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
2963*4882a593Smuzhiyun pkt->completion_func = hv_pci_generic_compl;
2964*4882a593Smuzhiyun pkt->compl_ctxt = &comp_pkt;
2965*4882a593Smuzhiyun
2966*4882a593Smuzhiyun if (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2) {
2967*4882a593Smuzhiyun res_assigned =
2968*4882a593Smuzhiyun (struct pci_resources_assigned *)&pkt->message;
2969*4882a593Smuzhiyun res_assigned->message_type.type =
2970*4882a593Smuzhiyun PCI_RESOURCES_ASSIGNED;
2971*4882a593Smuzhiyun res_assigned->wslot.slot = hpdev->desc.win_slot.slot;
2972*4882a593Smuzhiyun } else {
2973*4882a593Smuzhiyun res_assigned2 =
2974*4882a593Smuzhiyun (struct pci_resources_assigned2 *)&pkt->message;
2975*4882a593Smuzhiyun res_assigned2->message_type.type =
2976*4882a593Smuzhiyun PCI_RESOURCES_ASSIGNED2;
2977*4882a593Smuzhiyun res_assigned2->wslot.slot = hpdev->desc.win_slot.slot;
2978*4882a593Smuzhiyun }
2979*4882a593Smuzhiyun put_pcichild(hpdev);
2980*4882a593Smuzhiyun
2981*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, &pkt->message,
2982*4882a593Smuzhiyun size_res, (unsigned long)pkt,
2983*4882a593Smuzhiyun VM_PKT_DATA_INBAND,
2984*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2985*4882a593Smuzhiyun if (!ret)
2986*4882a593Smuzhiyun ret = wait_for_response(hdev, &comp_pkt.host_event);
2987*4882a593Smuzhiyun if (ret)
2988*4882a593Smuzhiyun break;
2989*4882a593Smuzhiyun
2990*4882a593Smuzhiyun if (comp_pkt.completion_status < 0) {
2991*4882a593Smuzhiyun ret = -EPROTO;
2992*4882a593Smuzhiyun dev_err(&hdev->device,
2993*4882a593Smuzhiyun "resource allocated returned 0x%x",
2994*4882a593Smuzhiyun comp_pkt.completion_status);
2995*4882a593Smuzhiyun break;
2996*4882a593Smuzhiyun }
2997*4882a593Smuzhiyun
2998*4882a593Smuzhiyun hbus->wslot_res_allocated = wslot;
2999*4882a593Smuzhiyun }
3000*4882a593Smuzhiyun
3001*4882a593Smuzhiyun kfree(pkt);
3002*4882a593Smuzhiyun return ret;
3003*4882a593Smuzhiyun }
3004*4882a593Smuzhiyun
3005*4882a593Smuzhiyun /**
3006*4882a593Smuzhiyun * hv_send_resources_released() - Report local resources
3007*4882a593Smuzhiyun * released
3008*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
3009*4882a593Smuzhiyun *
3010*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
3011*4882a593Smuzhiyun */
hv_send_resources_released(struct hv_device * hdev)3012*4882a593Smuzhiyun static int hv_send_resources_released(struct hv_device *hdev)
3013*4882a593Smuzhiyun {
3014*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3015*4882a593Smuzhiyun struct pci_child_message pkt;
3016*4882a593Smuzhiyun struct hv_pci_dev *hpdev;
3017*4882a593Smuzhiyun int wslot;
3018*4882a593Smuzhiyun int ret;
3019*4882a593Smuzhiyun
3020*4882a593Smuzhiyun for (wslot = hbus->wslot_res_allocated; wslot >= 0; wslot--) {
3021*4882a593Smuzhiyun hpdev = get_pcichild_wslot(hbus, wslot);
3022*4882a593Smuzhiyun if (!hpdev)
3023*4882a593Smuzhiyun continue;
3024*4882a593Smuzhiyun
3025*4882a593Smuzhiyun memset(&pkt, 0, sizeof(pkt));
3026*4882a593Smuzhiyun pkt.message_type.type = PCI_RESOURCES_RELEASED;
3027*4882a593Smuzhiyun pkt.wslot.slot = hpdev->desc.win_slot.slot;
3028*4882a593Smuzhiyun
3029*4882a593Smuzhiyun put_pcichild(hpdev);
3030*4882a593Smuzhiyun
3031*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, &pkt, sizeof(pkt), 0,
3032*4882a593Smuzhiyun VM_PKT_DATA_INBAND, 0);
3033*4882a593Smuzhiyun if (ret)
3034*4882a593Smuzhiyun return ret;
3035*4882a593Smuzhiyun
3036*4882a593Smuzhiyun hbus->wslot_res_allocated = wslot - 1;
3037*4882a593Smuzhiyun }
3038*4882a593Smuzhiyun
3039*4882a593Smuzhiyun hbus->wslot_res_allocated = -1;
3040*4882a593Smuzhiyun
3041*4882a593Smuzhiyun return 0;
3042*4882a593Smuzhiyun }
3043*4882a593Smuzhiyun
get_hvpcibus(struct hv_pcibus_device * hbus)3044*4882a593Smuzhiyun static void get_hvpcibus(struct hv_pcibus_device *hbus)
3045*4882a593Smuzhiyun {
3046*4882a593Smuzhiyun refcount_inc(&hbus->remove_lock);
3047*4882a593Smuzhiyun }
3048*4882a593Smuzhiyun
put_hvpcibus(struct hv_pcibus_device * hbus)3049*4882a593Smuzhiyun static void put_hvpcibus(struct hv_pcibus_device *hbus)
3050*4882a593Smuzhiyun {
3051*4882a593Smuzhiyun if (refcount_dec_and_test(&hbus->remove_lock))
3052*4882a593Smuzhiyun complete(&hbus->remove_event);
3053*4882a593Smuzhiyun }
3054*4882a593Smuzhiyun
3055*4882a593Smuzhiyun #define HVPCI_DOM_MAP_SIZE (64 * 1024)
3056*4882a593Smuzhiyun static DECLARE_BITMAP(hvpci_dom_map, HVPCI_DOM_MAP_SIZE);
3057*4882a593Smuzhiyun
3058*4882a593Smuzhiyun /*
3059*4882a593Smuzhiyun * PCI domain number 0 is used by emulated devices on Gen1 VMs, so define 0
3060*4882a593Smuzhiyun * as invalid for passthrough PCI devices of this driver.
3061*4882a593Smuzhiyun */
3062*4882a593Smuzhiyun #define HVPCI_DOM_INVALID 0
3063*4882a593Smuzhiyun
3064*4882a593Smuzhiyun /**
3065*4882a593Smuzhiyun * hv_get_dom_num() - Get a valid PCI domain number
3066*4882a593Smuzhiyun * Check if the PCI domain number is in use, and return another number if
3067*4882a593Smuzhiyun * it is in use.
3068*4882a593Smuzhiyun *
3069*4882a593Smuzhiyun * @dom: Requested domain number
3070*4882a593Smuzhiyun *
3071*4882a593Smuzhiyun * return: domain number on success, HVPCI_DOM_INVALID on failure
3072*4882a593Smuzhiyun */
hv_get_dom_num(u16 dom)3073*4882a593Smuzhiyun static u16 hv_get_dom_num(u16 dom)
3074*4882a593Smuzhiyun {
3075*4882a593Smuzhiyun unsigned int i;
3076*4882a593Smuzhiyun
3077*4882a593Smuzhiyun if (test_and_set_bit(dom, hvpci_dom_map) == 0)
3078*4882a593Smuzhiyun return dom;
3079*4882a593Smuzhiyun
3080*4882a593Smuzhiyun for_each_clear_bit(i, hvpci_dom_map, HVPCI_DOM_MAP_SIZE) {
3081*4882a593Smuzhiyun if (test_and_set_bit(i, hvpci_dom_map) == 0)
3082*4882a593Smuzhiyun return i;
3083*4882a593Smuzhiyun }
3084*4882a593Smuzhiyun
3085*4882a593Smuzhiyun return HVPCI_DOM_INVALID;
3086*4882a593Smuzhiyun }
3087*4882a593Smuzhiyun
3088*4882a593Smuzhiyun /**
3089*4882a593Smuzhiyun * hv_put_dom_num() - Mark the PCI domain number as free
3090*4882a593Smuzhiyun * @dom: Domain number to be freed
3091*4882a593Smuzhiyun */
hv_put_dom_num(u16 dom)3092*4882a593Smuzhiyun static void hv_put_dom_num(u16 dom)
3093*4882a593Smuzhiyun {
3094*4882a593Smuzhiyun clear_bit(dom, hvpci_dom_map);
3095*4882a593Smuzhiyun }
3096*4882a593Smuzhiyun
3097*4882a593Smuzhiyun /**
3098*4882a593Smuzhiyun * hv_pci_probe() - New VMBus channel probe, for a root PCI bus
3099*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
3100*4882a593Smuzhiyun * @dev_id: Identifies the device itself
3101*4882a593Smuzhiyun *
3102*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
3103*4882a593Smuzhiyun */
hv_pci_probe(struct hv_device * hdev,const struct hv_vmbus_device_id * dev_id)3104*4882a593Smuzhiyun static int hv_pci_probe(struct hv_device *hdev,
3105*4882a593Smuzhiyun const struct hv_vmbus_device_id *dev_id)
3106*4882a593Smuzhiyun {
3107*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
3108*4882a593Smuzhiyun u16 dom_req, dom;
3109*4882a593Smuzhiyun char *name;
3110*4882a593Smuzhiyun bool enter_d0_retry = true;
3111*4882a593Smuzhiyun int ret;
3112*4882a593Smuzhiyun
3113*4882a593Smuzhiyun /*
3114*4882a593Smuzhiyun * hv_pcibus_device contains the hypercall arguments for retargeting in
3115*4882a593Smuzhiyun * hv_irq_unmask(). Those must not cross a page boundary.
3116*4882a593Smuzhiyun */
3117*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(*hbus) > HV_HYP_PAGE_SIZE);
3118*4882a593Smuzhiyun
3119*4882a593Smuzhiyun /*
3120*4882a593Smuzhiyun * With the recent 59bb47985c1d ("mm, sl[aou]b: guarantee natural
3121*4882a593Smuzhiyun * alignment for kmalloc(power-of-two)"), kzalloc() is able to allocate
3122*4882a593Smuzhiyun * a 4KB buffer that is guaranteed to be 4KB-aligned. Here the size and
3123*4882a593Smuzhiyun * alignment of hbus is important because hbus's field
3124*4882a593Smuzhiyun * retarget_msi_interrupt_params must not cross a 4KB page boundary.
3125*4882a593Smuzhiyun *
3126*4882a593Smuzhiyun * Here we prefer kzalloc to get_zeroed_page(), because a buffer
3127*4882a593Smuzhiyun * allocated by the latter is not tracked and scanned by kmemleak, and
3128*4882a593Smuzhiyun * hence kmemleak reports the pointer contained in the hbus buffer
3129*4882a593Smuzhiyun * (i.e. the hpdev struct, which is created in new_pcichild_device() and
3130*4882a593Smuzhiyun * is tracked by hbus->children) as memory leak (false positive).
3131*4882a593Smuzhiyun *
3132*4882a593Smuzhiyun * If the kernel doesn't have 59bb47985c1d, get_zeroed_page() *must* be
3133*4882a593Smuzhiyun * used to allocate the hbus buffer and we can avoid the kmemleak false
3134*4882a593Smuzhiyun * positive by using kmemleak_alloc() and kmemleak_free() to ask
3135*4882a593Smuzhiyun * kmemleak to track and scan the hbus buffer.
3136*4882a593Smuzhiyun */
3137*4882a593Smuzhiyun hbus = kzalloc(HV_HYP_PAGE_SIZE, GFP_KERNEL);
3138*4882a593Smuzhiyun if (!hbus)
3139*4882a593Smuzhiyun return -ENOMEM;
3140*4882a593Smuzhiyun hbus->state = hv_pcibus_init;
3141*4882a593Smuzhiyun hbus->wslot_res_allocated = -1;
3142*4882a593Smuzhiyun
3143*4882a593Smuzhiyun /*
3144*4882a593Smuzhiyun * The PCI bus "domain" is what is called "segment" in ACPI and other
3145*4882a593Smuzhiyun * specs. Pull it from the instance ID, to get something usually
3146*4882a593Smuzhiyun * unique. In rare cases of collision, we will find out another number
3147*4882a593Smuzhiyun * not in use.
3148*4882a593Smuzhiyun *
3149*4882a593Smuzhiyun * Note that, since this code only runs in a Hyper-V VM, Hyper-V
3150*4882a593Smuzhiyun * together with this guest driver can guarantee that (1) The only
3151*4882a593Smuzhiyun * domain used by Gen1 VMs for something that looks like a physical
3152*4882a593Smuzhiyun * PCI bus (which is actually emulated by the hypervisor) is domain 0.
3153*4882a593Smuzhiyun * (2) There will be no overlap between domains (after fixing possible
3154*4882a593Smuzhiyun * collisions) in the same VM.
3155*4882a593Smuzhiyun */
3156*4882a593Smuzhiyun dom_req = hdev->dev_instance.b[5] << 8 | hdev->dev_instance.b[4];
3157*4882a593Smuzhiyun dom = hv_get_dom_num(dom_req);
3158*4882a593Smuzhiyun
3159*4882a593Smuzhiyun if (dom == HVPCI_DOM_INVALID) {
3160*4882a593Smuzhiyun dev_err(&hdev->device,
3161*4882a593Smuzhiyun "Unable to use dom# 0x%hx or other numbers", dom_req);
3162*4882a593Smuzhiyun ret = -EINVAL;
3163*4882a593Smuzhiyun goto free_bus;
3164*4882a593Smuzhiyun }
3165*4882a593Smuzhiyun
3166*4882a593Smuzhiyun if (dom != dom_req)
3167*4882a593Smuzhiyun dev_info(&hdev->device,
3168*4882a593Smuzhiyun "PCI dom# 0x%hx has collision, using 0x%hx",
3169*4882a593Smuzhiyun dom_req, dom);
3170*4882a593Smuzhiyun
3171*4882a593Smuzhiyun hbus->sysdata.domain = dom;
3172*4882a593Smuzhiyun
3173*4882a593Smuzhiyun hbus->hdev = hdev;
3174*4882a593Smuzhiyun refcount_set(&hbus->remove_lock, 1);
3175*4882a593Smuzhiyun INIT_LIST_HEAD(&hbus->children);
3176*4882a593Smuzhiyun INIT_LIST_HEAD(&hbus->dr_list);
3177*4882a593Smuzhiyun INIT_LIST_HEAD(&hbus->resources_for_children);
3178*4882a593Smuzhiyun spin_lock_init(&hbus->config_lock);
3179*4882a593Smuzhiyun spin_lock_init(&hbus->device_list_lock);
3180*4882a593Smuzhiyun spin_lock_init(&hbus->retarget_msi_interrupt_lock);
3181*4882a593Smuzhiyun init_completion(&hbus->remove_event);
3182*4882a593Smuzhiyun hbus->wq = alloc_ordered_workqueue("hv_pci_%x", 0,
3183*4882a593Smuzhiyun hbus->sysdata.domain);
3184*4882a593Smuzhiyun if (!hbus->wq) {
3185*4882a593Smuzhiyun ret = -ENOMEM;
3186*4882a593Smuzhiyun goto free_dom;
3187*4882a593Smuzhiyun }
3188*4882a593Smuzhiyun
3189*4882a593Smuzhiyun ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
3190*4882a593Smuzhiyun hv_pci_onchannelcallback, hbus);
3191*4882a593Smuzhiyun if (ret)
3192*4882a593Smuzhiyun goto destroy_wq;
3193*4882a593Smuzhiyun
3194*4882a593Smuzhiyun hv_set_drvdata(hdev, hbus);
3195*4882a593Smuzhiyun
3196*4882a593Smuzhiyun ret = hv_pci_protocol_negotiation(hdev, pci_protocol_versions,
3197*4882a593Smuzhiyun ARRAY_SIZE(pci_protocol_versions));
3198*4882a593Smuzhiyun if (ret)
3199*4882a593Smuzhiyun goto close;
3200*4882a593Smuzhiyun
3201*4882a593Smuzhiyun ret = hv_allocate_config_window(hbus);
3202*4882a593Smuzhiyun if (ret)
3203*4882a593Smuzhiyun goto close;
3204*4882a593Smuzhiyun
3205*4882a593Smuzhiyun hbus->cfg_addr = ioremap(hbus->mem_config->start,
3206*4882a593Smuzhiyun PCI_CONFIG_MMIO_LENGTH);
3207*4882a593Smuzhiyun if (!hbus->cfg_addr) {
3208*4882a593Smuzhiyun dev_err(&hdev->device,
3209*4882a593Smuzhiyun "Unable to map a virtual address for config space\n");
3210*4882a593Smuzhiyun ret = -ENOMEM;
3211*4882a593Smuzhiyun goto free_config;
3212*4882a593Smuzhiyun }
3213*4882a593Smuzhiyun
3214*4882a593Smuzhiyun name = kasprintf(GFP_KERNEL, "%pUL", &hdev->dev_instance);
3215*4882a593Smuzhiyun if (!name) {
3216*4882a593Smuzhiyun ret = -ENOMEM;
3217*4882a593Smuzhiyun goto unmap;
3218*4882a593Smuzhiyun }
3219*4882a593Smuzhiyun
3220*4882a593Smuzhiyun hbus->sysdata.fwnode = irq_domain_alloc_named_fwnode(name);
3221*4882a593Smuzhiyun kfree(name);
3222*4882a593Smuzhiyun if (!hbus->sysdata.fwnode) {
3223*4882a593Smuzhiyun ret = -ENOMEM;
3224*4882a593Smuzhiyun goto unmap;
3225*4882a593Smuzhiyun }
3226*4882a593Smuzhiyun
3227*4882a593Smuzhiyun ret = hv_pcie_init_irq_domain(hbus);
3228*4882a593Smuzhiyun if (ret)
3229*4882a593Smuzhiyun goto free_fwnode;
3230*4882a593Smuzhiyun
3231*4882a593Smuzhiyun retry:
3232*4882a593Smuzhiyun ret = hv_pci_query_relations(hdev);
3233*4882a593Smuzhiyun if (ret)
3234*4882a593Smuzhiyun goto free_irq_domain;
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun ret = hv_pci_enter_d0(hdev);
3237*4882a593Smuzhiyun /*
3238*4882a593Smuzhiyun * In certain case (Kdump) the pci device of interest was
3239*4882a593Smuzhiyun * not cleanly shut down and resource is still held on host
3240*4882a593Smuzhiyun * side, the host could return invalid device status.
3241*4882a593Smuzhiyun * We need to explicitly request host to release the resource
3242*4882a593Smuzhiyun * and try to enter D0 again.
3243*4882a593Smuzhiyun * Since the hv_pci_bus_exit() call releases structures
3244*4882a593Smuzhiyun * of all its child devices, we need to start the retry from
3245*4882a593Smuzhiyun * hv_pci_query_relations() call, requesting host to send
3246*4882a593Smuzhiyun * the synchronous child device relations message before this
3247*4882a593Smuzhiyun * information is needed in hv_send_resources_allocated()
3248*4882a593Smuzhiyun * call later.
3249*4882a593Smuzhiyun */
3250*4882a593Smuzhiyun if (ret == -EPROTO && enter_d0_retry) {
3251*4882a593Smuzhiyun enter_d0_retry = false;
3252*4882a593Smuzhiyun
3253*4882a593Smuzhiyun dev_err(&hdev->device, "Retrying D0 Entry\n");
3254*4882a593Smuzhiyun
3255*4882a593Smuzhiyun /*
3256*4882a593Smuzhiyun * Hv_pci_bus_exit() calls hv_send_resources_released()
3257*4882a593Smuzhiyun * to free up resources of its child devices.
3258*4882a593Smuzhiyun * In the kdump kernel we need to set the
3259*4882a593Smuzhiyun * wslot_res_allocated to 255 so it scans all child
3260*4882a593Smuzhiyun * devices to release resources allocated in the
3261*4882a593Smuzhiyun * normal kernel before panic happened.
3262*4882a593Smuzhiyun */
3263*4882a593Smuzhiyun hbus->wslot_res_allocated = 255;
3264*4882a593Smuzhiyun ret = hv_pci_bus_exit(hdev, true);
3265*4882a593Smuzhiyun
3266*4882a593Smuzhiyun if (ret == 0)
3267*4882a593Smuzhiyun goto retry;
3268*4882a593Smuzhiyun
3269*4882a593Smuzhiyun dev_err(&hdev->device,
3270*4882a593Smuzhiyun "Retrying D0 failed with ret %d\n", ret);
3271*4882a593Smuzhiyun }
3272*4882a593Smuzhiyun if (ret)
3273*4882a593Smuzhiyun goto free_irq_domain;
3274*4882a593Smuzhiyun
3275*4882a593Smuzhiyun ret = hv_pci_allocate_bridge_windows(hbus);
3276*4882a593Smuzhiyun if (ret)
3277*4882a593Smuzhiyun goto exit_d0;
3278*4882a593Smuzhiyun
3279*4882a593Smuzhiyun ret = hv_send_resources_allocated(hdev);
3280*4882a593Smuzhiyun if (ret)
3281*4882a593Smuzhiyun goto free_windows;
3282*4882a593Smuzhiyun
3283*4882a593Smuzhiyun prepopulate_bars(hbus);
3284*4882a593Smuzhiyun
3285*4882a593Smuzhiyun hbus->state = hv_pcibus_probed;
3286*4882a593Smuzhiyun
3287*4882a593Smuzhiyun ret = create_root_hv_pci_bus(hbus);
3288*4882a593Smuzhiyun if (ret)
3289*4882a593Smuzhiyun goto free_windows;
3290*4882a593Smuzhiyun
3291*4882a593Smuzhiyun return 0;
3292*4882a593Smuzhiyun
3293*4882a593Smuzhiyun free_windows:
3294*4882a593Smuzhiyun hv_pci_free_bridge_windows(hbus);
3295*4882a593Smuzhiyun exit_d0:
3296*4882a593Smuzhiyun (void) hv_pci_bus_exit(hdev, true);
3297*4882a593Smuzhiyun free_irq_domain:
3298*4882a593Smuzhiyun irq_domain_remove(hbus->irq_domain);
3299*4882a593Smuzhiyun free_fwnode:
3300*4882a593Smuzhiyun irq_domain_free_fwnode(hbus->sysdata.fwnode);
3301*4882a593Smuzhiyun unmap:
3302*4882a593Smuzhiyun iounmap(hbus->cfg_addr);
3303*4882a593Smuzhiyun free_config:
3304*4882a593Smuzhiyun hv_free_config_window(hbus);
3305*4882a593Smuzhiyun close:
3306*4882a593Smuzhiyun vmbus_close(hdev->channel);
3307*4882a593Smuzhiyun destroy_wq:
3308*4882a593Smuzhiyun destroy_workqueue(hbus->wq);
3309*4882a593Smuzhiyun free_dom:
3310*4882a593Smuzhiyun hv_put_dom_num(hbus->sysdata.domain);
3311*4882a593Smuzhiyun free_bus:
3312*4882a593Smuzhiyun kfree(hbus);
3313*4882a593Smuzhiyun return ret;
3314*4882a593Smuzhiyun }
3315*4882a593Smuzhiyun
hv_pci_bus_exit(struct hv_device * hdev,bool keep_devs)3316*4882a593Smuzhiyun static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs)
3317*4882a593Smuzhiyun {
3318*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3319*4882a593Smuzhiyun struct {
3320*4882a593Smuzhiyun struct pci_packet teardown_packet;
3321*4882a593Smuzhiyun u8 buffer[sizeof(struct pci_message)];
3322*4882a593Smuzhiyun } pkt;
3323*4882a593Smuzhiyun struct hv_pci_compl comp_pkt;
3324*4882a593Smuzhiyun struct hv_pci_dev *hpdev, *tmp;
3325*4882a593Smuzhiyun unsigned long flags;
3326*4882a593Smuzhiyun int ret;
3327*4882a593Smuzhiyun
3328*4882a593Smuzhiyun /*
3329*4882a593Smuzhiyun * After the host sends the RESCIND_CHANNEL message, it doesn't
3330*4882a593Smuzhiyun * access the per-channel ringbuffer any longer.
3331*4882a593Smuzhiyun */
3332*4882a593Smuzhiyun if (hdev->channel->rescind)
3333*4882a593Smuzhiyun return 0;
3334*4882a593Smuzhiyun
3335*4882a593Smuzhiyun if (!keep_devs) {
3336*4882a593Smuzhiyun struct list_head removed;
3337*4882a593Smuzhiyun
3338*4882a593Smuzhiyun /* Move all present children to the list on stack */
3339*4882a593Smuzhiyun INIT_LIST_HEAD(&removed);
3340*4882a593Smuzhiyun spin_lock_irqsave(&hbus->device_list_lock, flags);
3341*4882a593Smuzhiyun list_for_each_entry_safe(hpdev, tmp, &hbus->children, list_entry)
3342*4882a593Smuzhiyun list_move_tail(&hpdev->list_entry, &removed);
3343*4882a593Smuzhiyun spin_unlock_irqrestore(&hbus->device_list_lock, flags);
3344*4882a593Smuzhiyun
3345*4882a593Smuzhiyun /* Remove all children in the list */
3346*4882a593Smuzhiyun list_for_each_entry_safe(hpdev, tmp, &removed, list_entry) {
3347*4882a593Smuzhiyun list_del(&hpdev->list_entry);
3348*4882a593Smuzhiyun if (hpdev->pci_slot)
3349*4882a593Smuzhiyun pci_destroy_slot(hpdev->pci_slot);
3350*4882a593Smuzhiyun /* For the two refs got in new_pcichild_device() */
3351*4882a593Smuzhiyun put_pcichild(hpdev);
3352*4882a593Smuzhiyun put_pcichild(hpdev);
3353*4882a593Smuzhiyun }
3354*4882a593Smuzhiyun }
3355*4882a593Smuzhiyun
3356*4882a593Smuzhiyun ret = hv_send_resources_released(hdev);
3357*4882a593Smuzhiyun if (ret) {
3358*4882a593Smuzhiyun dev_err(&hdev->device,
3359*4882a593Smuzhiyun "Couldn't send resources released packet(s)\n");
3360*4882a593Smuzhiyun return ret;
3361*4882a593Smuzhiyun }
3362*4882a593Smuzhiyun
3363*4882a593Smuzhiyun memset(&pkt.teardown_packet, 0, sizeof(pkt.teardown_packet));
3364*4882a593Smuzhiyun init_completion(&comp_pkt.host_event);
3365*4882a593Smuzhiyun pkt.teardown_packet.completion_func = hv_pci_generic_compl;
3366*4882a593Smuzhiyun pkt.teardown_packet.compl_ctxt = &comp_pkt;
3367*4882a593Smuzhiyun pkt.teardown_packet.message[0].type = PCI_BUS_D0EXIT;
3368*4882a593Smuzhiyun
3369*4882a593Smuzhiyun ret = vmbus_sendpacket(hdev->channel, &pkt.teardown_packet.message,
3370*4882a593Smuzhiyun sizeof(struct pci_message),
3371*4882a593Smuzhiyun (unsigned long)&pkt.teardown_packet,
3372*4882a593Smuzhiyun VM_PKT_DATA_INBAND,
3373*4882a593Smuzhiyun VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3374*4882a593Smuzhiyun if (ret)
3375*4882a593Smuzhiyun return ret;
3376*4882a593Smuzhiyun
3377*4882a593Smuzhiyun if (wait_for_completion_timeout(&comp_pkt.host_event, 10 * HZ) == 0)
3378*4882a593Smuzhiyun return -ETIMEDOUT;
3379*4882a593Smuzhiyun
3380*4882a593Smuzhiyun return 0;
3381*4882a593Smuzhiyun }
3382*4882a593Smuzhiyun
3383*4882a593Smuzhiyun /**
3384*4882a593Smuzhiyun * hv_pci_remove() - Remove routine for this VMBus channel
3385*4882a593Smuzhiyun * @hdev: VMBus's tracking struct for this root PCI bus
3386*4882a593Smuzhiyun *
3387*4882a593Smuzhiyun * Return: 0 on success, -errno on failure
3388*4882a593Smuzhiyun */
hv_pci_remove(struct hv_device * hdev)3389*4882a593Smuzhiyun static int hv_pci_remove(struct hv_device *hdev)
3390*4882a593Smuzhiyun {
3391*4882a593Smuzhiyun struct hv_pcibus_device *hbus;
3392*4882a593Smuzhiyun int ret;
3393*4882a593Smuzhiyun
3394*4882a593Smuzhiyun hbus = hv_get_drvdata(hdev);
3395*4882a593Smuzhiyun if (hbus->state == hv_pcibus_installed) {
3396*4882a593Smuzhiyun tasklet_disable(&hdev->channel->callback_event);
3397*4882a593Smuzhiyun hbus->state = hv_pcibus_removing;
3398*4882a593Smuzhiyun tasklet_enable(&hdev->channel->callback_event);
3399*4882a593Smuzhiyun destroy_workqueue(hbus->wq);
3400*4882a593Smuzhiyun hbus->wq = NULL;
3401*4882a593Smuzhiyun /*
3402*4882a593Smuzhiyun * At this point, no work is running or can be scheduled
3403*4882a593Smuzhiyun * on hbus-wq. We can't race with hv_pci_devices_present()
3404*4882a593Smuzhiyun * or hv_pci_eject_device(), it's safe to proceed.
3405*4882a593Smuzhiyun */
3406*4882a593Smuzhiyun
3407*4882a593Smuzhiyun /* Remove the bus from PCI's point of view. */
3408*4882a593Smuzhiyun pci_lock_rescan_remove();
3409*4882a593Smuzhiyun pci_stop_root_bus(hbus->pci_bus);
3410*4882a593Smuzhiyun hv_pci_remove_slots(hbus);
3411*4882a593Smuzhiyun pci_remove_root_bus(hbus->pci_bus);
3412*4882a593Smuzhiyun pci_unlock_rescan_remove();
3413*4882a593Smuzhiyun }
3414*4882a593Smuzhiyun
3415*4882a593Smuzhiyun ret = hv_pci_bus_exit(hdev, false);
3416*4882a593Smuzhiyun
3417*4882a593Smuzhiyun vmbus_close(hdev->channel);
3418*4882a593Smuzhiyun
3419*4882a593Smuzhiyun iounmap(hbus->cfg_addr);
3420*4882a593Smuzhiyun hv_free_config_window(hbus);
3421*4882a593Smuzhiyun pci_free_resource_list(&hbus->resources_for_children);
3422*4882a593Smuzhiyun hv_pci_free_bridge_windows(hbus);
3423*4882a593Smuzhiyun irq_domain_remove(hbus->irq_domain);
3424*4882a593Smuzhiyun irq_domain_free_fwnode(hbus->sysdata.fwnode);
3425*4882a593Smuzhiyun put_hvpcibus(hbus);
3426*4882a593Smuzhiyun wait_for_completion(&hbus->remove_event);
3427*4882a593Smuzhiyun
3428*4882a593Smuzhiyun hv_put_dom_num(hbus->sysdata.domain);
3429*4882a593Smuzhiyun
3430*4882a593Smuzhiyun kfree(hbus);
3431*4882a593Smuzhiyun return ret;
3432*4882a593Smuzhiyun }
3433*4882a593Smuzhiyun
hv_pci_suspend(struct hv_device * hdev)3434*4882a593Smuzhiyun static int hv_pci_suspend(struct hv_device *hdev)
3435*4882a593Smuzhiyun {
3436*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3437*4882a593Smuzhiyun enum hv_pcibus_state old_state;
3438*4882a593Smuzhiyun int ret;
3439*4882a593Smuzhiyun
3440*4882a593Smuzhiyun /*
3441*4882a593Smuzhiyun * hv_pci_suspend() must make sure there are no pending work items
3442*4882a593Smuzhiyun * before calling vmbus_close(), since it runs in a process context
3443*4882a593Smuzhiyun * as a callback in dpm_suspend(). When it starts to run, the channel
3444*4882a593Smuzhiyun * callback hv_pci_onchannelcallback(), which runs in a tasklet
3445*4882a593Smuzhiyun * context, can be still running concurrently and scheduling new work
3446*4882a593Smuzhiyun * items onto hbus->wq in hv_pci_devices_present() and
3447*4882a593Smuzhiyun * hv_pci_eject_device(), and the work item handlers can access the
3448*4882a593Smuzhiyun * vmbus channel, which can be being closed by hv_pci_suspend(), e.g.
3449*4882a593Smuzhiyun * the work item handler pci_devices_present_work() ->
3450*4882a593Smuzhiyun * new_pcichild_device() writes to the vmbus channel.
3451*4882a593Smuzhiyun *
3452*4882a593Smuzhiyun * To eliminate the race, hv_pci_suspend() disables the channel
3453*4882a593Smuzhiyun * callback tasklet, sets hbus->state to hv_pcibus_removing, and
3454*4882a593Smuzhiyun * re-enables the tasklet. This way, when hv_pci_suspend() proceeds,
3455*4882a593Smuzhiyun * it knows that no new work item can be scheduled, and then it flushes
3456*4882a593Smuzhiyun * hbus->wq and safely closes the vmbus channel.
3457*4882a593Smuzhiyun */
3458*4882a593Smuzhiyun tasklet_disable(&hdev->channel->callback_event);
3459*4882a593Smuzhiyun
3460*4882a593Smuzhiyun /* Change the hbus state to prevent new work items. */
3461*4882a593Smuzhiyun old_state = hbus->state;
3462*4882a593Smuzhiyun if (hbus->state == hv_pcibus_installed)
3463*4882a593Smuzhiyun hbus->state = hv_pcibus_removing;
3464*4882a593Smuzhiyun
3465*4882a593Smuzhiyun tasklet_enable(&hdev->channel->callback_event);
3466*4882a593Smuzhiyun
3467*4882a593Smuzhiyun if (old_state != hv_pcibus_installed)
3468*4882a593Smuzhiyun return -EINVAL;
3469*4882a593Smuzhiyun
3470*4882a593Smuzhiyun flush_workqueue(hbus->wq);
3471*4882a593Smuzhiyun
3472*4882a593Smuzhiyun ret = hv_pci_bus_exit(hdev, true);
3473*4882a593Smuzhiyun if (ret)
3474*4882a593Smuzhiyun return ret;
3475*4882a593Smuzhiyun
3476*4882a593Smuzhiyun vmbus_close(hdev->channel);
3477*4882a593Smuzhiyun
3478*4882a593Smuzhiyun return 0;
3479*4882a593Smuzhiyun }
3480*4882a593Smuzhiyun
hv_pci_restore_msi_msg(struct pci_dev * pdev,void * arg)3481*4882a593Smuzhiyun static int hv_pci_restore_msi_msg(struct pci_dev *pdev, void *arg)
3482*4882a593Smuzhiyun {
3483*4882a593Smuzhiyun struct msi_desc *entry;
3484*4882a593Smuzhiyun struct irq_data *irq_data;
3485*4882a593Smuzhiyun
3486*4882a593Smuzhiyun for_each_pci_msi_entry(entry, pdev) {
3487*4882a593Smuzhiyun irq_data = irq_get_irq_data(entry->irq);
3488*4882a593Smuzhiyun if (WARN_ON_ONCE(!irq_data))
3489*4882a593Smuzhiyun return -EINVAL;
3490*4882a593Smuzhiyun
3491*4882a593Smuzhiyun hv_compose_msi_msg(irq_data, &entry->msg);
3492*4882a593Smuzhiyun }
3493*4882a593Smuzhiyun
3494*4882a593Smuzhiyun return 0;
3495*4882a593Smuzhiyun }
3496*4882a593Smuzhiyun
3497*4882a593Smuzhiyun /*
3498*4882a593Smuzhiyun * Upon resume, pci_restore_msi_state() -> ... -> __pci_write_msi_msg()
3499*4882a593Smuzhiyun * directly writes the MSI/MSI-X registers via MMIO, but since Hyper-V
3500*4882a593Smuzhiyun * doesn't trap and emulate the MMIO accesses, here hv_compose_msi_msg()
3501*4882a593Smuzhiyun * must be used to ask Hyper-V to re-create the IOMMU Interrupt Remapping
3502*4882a593Smuzhiyun * Table entries.
3503*4882a593Smuzhiyun */
hv_pci_restore_msi_state(struct hv_pcibus_device * hbus)3504*4882a593Smuzhiyun static void hv_pci_restore_msi_state(struct hv_pcibus_device *hbus)
3505*4882a593Smuzhiyun {
3506*4882a593Smuzhiyun pci_walk_bus(hbus->pci_bus, hv_pci_restore_msi_msg, NULL);
3507*4882a593Smuzhiyun }
3508*4882a593Smuzhiyun
hv_pci_resume(struct hv_device * hdev)3509*4882a593Smuzhiyun static int hv_pci_resume(struct hv_device *hdev)
3510*4882a593Smuzhiyun {
3511*4882a593Smuzhiyun struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3512*4882a593Smuzhiyun enum pci_protocol_version_t version[1];
3513*4882a593Smuzhiyun int ret;
3514*4882a593Smuzhiyun
3515*4882a593Smuzhiyun hbus->state = hv_pcibus_init;
3516*4882a593Smuzhiyun
3517*4882a593Smuzhiyun ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
3518*4882a593Smuzhiyun hv_pci_onchannelcallback, hbus);
3519*4882a593Smuzhiyun if (ret)
3520*4882a593Smuzhiyun return ret;
3521*4882a593Smuzhiyun
3522*4882a593Smuzhiyun /* Only use the version that was in use before hibernation. */
3523*4882a593Smuzhiyun version[0] = hbus->protocol_version;
3524*4882a593Smuzhiyun ret = hv_pci_protocol_negotiation(hdev, version, 1);
3525*4882a593Smuzhiyun if (ret)
3526*4882a593Smuzhiyun goto out;
3527*4882a593Smuzhiyun
3528*4882a593Smuzhiyun ret = hv_pci_query_relations(hdev);
3529*4882a593Smuzhiyun if (ret)
3530*4882a593Smuzhiyun goto out;
3531*4882a593Smuzhiyun
3532*4882a593Smuzhiyun ret = hv_pci_enter_d0(hdev);
3533*4882a593Smuzhiyun if (ret)
3534*4882a593Smuzhiyun goto out;
3535*4882a593Smuzhiyun
3536*4882a593Smuzhiyun ret = hv_send_resources_allocated(hdev);
3537*4882a593Smuzhiyun if (ret)
3538*4882a593Smuzhiyun goto out;
3539*4882a593Smuzhiyun
3540*4882a593Smuzhiyun prepopulate_bars(hbus);
3541*4882a593Smuzhiyun
3542*4882a593Smuzhiyun hv_pci_restore_msi_state(hbus);
3543*4882a593Smuzhiyun
3544*4882a593Smuzhiyun hbus->state = hv_pcibus_installed;
3545*4882a593Smuzhiyun return 0;
3546*4882a593Smuzhiyun out:
3547*4882a593Smuzhiyun vmbus_close(hdev->channel);
3548*4882a593Smuzhiyun return ret;
3549*4882a593Smuzhiyun }
3550*4882a593Smuzhiyun
3551*4882a593Smuzhiyun static const struct hv_vmbus_device_id hv_pci_id_table[] = {
3552*4882a593Smuzhiyun /* PCI Pass-through Class ID */
3553*4882a593Smuzhiyun /* 44C4F61D-4444-4400-9D52-802E27EDE19F */
3554*4882a593Smuzhiyun { HV_PCIE_GUID, },
3555*4882a593Smuzhiyun { },
3556*4882a593Smuzhiyun };
3557*4882a593Smuzhiyun
3558*4882a593Smuzhiyun MODULE_DEVICE_TABLE(vmbus, hv_pci_id_table);
3559*4882a593Smuzhiyun
3560*4882a593Smuzhiyun static struct hv_driver hv_pci_drv = {
3561*4882a593Smuzhiyun .name = "hv_pci",
3562*4882a593Smuzhiyun .id_table = hv_pci_id_table,
3563*4882a593Smuzhiyun .probe = hv_pci_probe,
3564*4882a593Smuzhiyun .remove = hv_pci_remove,
3565*4882a593Smuzhiyun .suspend = hv_pci_suspend,
3566*4882a593Smuzhiyun .resume = hv_pci_resume,
3567*4882a593Smuzhiyun };
3568*4882a593Smuzhiyun
exit_hv_pci_drv(void)3569*4882a593Smuzhiyun static void __exit exit_hv_pci_drv(void)
3570*4882a593Smuzhiyun {
3571*4882a593Smuzhiyun vmbus_driver_unregister(&hv_pci_drv);
3572*4882a593Smuzhiyun
3573*4882a593Smuzhiyun hvpci_block_ops.read_block = NULL;
3574*4882a593Smuzhiyun hvpci_block_ops.write_block = NULL;
3575*4882a593Smuzhiyun hvpci_block_ops.reg_blk_invalidate = NULL;
3576*4882a593Smuzhiyun }
3577*4882a593Smuzhiyun
init_hv_pci_drv(void)3578*4882a593Smuzhiyun static int __init init_hv_pci_drv(void)
3579*4882a593Smuzhiyun {
3580*4882a593Smuzhiyun if (!hv_is_hyperv_initialized())
3581*4882a593Smuzhiyun return -ENODEV;
3582*4882a593Smuzhiyun
3583*4882a593Smuzhiyun /* Set the invalid domain number's bit, so it will not be used */
3584*4882a593Smuzhiyun set_bit(HVPCI_DOM_INVALID, hvpci_dom_map);
3585*4882a593Smuzhiyun
3586*4882a593Smuzhiyun /* Initialize PCI block r/w interface */
3587*4882a593Smuzhiyun hvpci_block_ops.read_block = hv_read_config_block;
3588*4882a593Smuzhiyun hvpci_block_ops.write_block = hv_write_config_block;
3589*4882a593Smuzhiyun hvpci_block_ops.reg_blk_invalidate = hv_register_block_invalidate;
3590*4882a593Smuzhiyun
3591*4882a593Smuzhiyun return vmbus_driver_register(&hv_pci_drv);
3592*4882a593Smuzhiyun }
3593*4882a593Smuzhiyun
3594*4882a593Smuzhiyun module_init(init_hv_pci_drv);
3595*4882a593Smuzhiyun module_exit(exit_hv_pci_drv);
3596*4882a593Smuzhiyun
3597*4882a593Smuzhiyun MODULE_DESCRIPTION("Hyper-V PCI");
3598*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
3599