1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PCIe host controller driver for HiSilicon SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors: Zhou Wang <wangzhou1@hisilicon.com>
8*4882a593Smuzhiyun * Dacai Zhu <zhudacai@hisilicon.com>
9*4882a593Smuzhiyun * Gabriele Paoloni <gabriele.paoloni@huawei.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/pci-acpi.h>
16*4882a593Smuzhiyun #include <linux/pci-ecam.h>
17*4882a593Smuzhiyun #include "../../pci.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
20*4882a593Smuzhiyun
hisi_pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)21*4882a593Smuzhiyun static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
22*4882a593Smuzhiyun int size, u32 *val)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct pci_config_window *cfg = bus->sysdata;
25*4882a593Smuzhiyun int dev = PCI_SLOT(devfn);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun if (bus->number == cfg->busr.start) {
28*4882a593Smuzhiyun /* access only one slot on each root port */
29*4882a593Smuzhiyun if (dev > 0)
30*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
31*4882a593Smuzhiyun else
32*4882a593Smuzhiyun return pci_generic_config_read32(bus, devfn, where,
33*4882a593Smuzhiyun size, val);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return pci_generic_config_read(bus, devfn, where, size, val);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
hisi_pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)39*4882a593Smuzhiyun static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
40*4882a593Smuzhiyun int where, int size, u32 val)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct pci_config_window *cfg = bus->sysdata;
43*4882a593Smuzhiyun int dev = PCI_SLOT(devfn);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (bus->number == cfg->busr.start) {
46*4882a593Smuzhiyun /* access only one slot on each root port */
47*4882a593Smuzhiyun if (dev > 0)
48*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
49*4882a593Smuzhiyun else
50*4882a593Smuzhiyun return pci_generic_config_write32(bus, devfn, where,
51*4882a593Smuzhiyun size, val);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return pci_generic_config_write(bus, devfn, where, size, val);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
hisi_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)57*4882a593Smuzhiyun static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
58*4882a593Smuzhiyun int where)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct pci_config_window *cfg = bus->sysdata;
61*4882a593Smuzhiyun void __iomem *reg_base = cfg->priv;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (bus->number == cfg->busr.start)
64*4882a593Smuzhiyun return reg_base + where;
65*4882a593Smuzhiyun else
66*4882a593Smuzhiyun return pci_ecam_map_bus(bus, devfn, where);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
70*4882a593Smuzhiyun
hisi_pcie_init(struct pci_config_window * cfg)71*4882a593Smuzhiyun static int hisi_pcie_init(struct pci_config_window *cfg)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct device *dev = cfg->parent;
74*4882a593Smuzhiyun struct acpi_device *adev = to_acpi_device(dev);
75*4882a593Smuzhiyun struct acpi_pci_root *root = acpi_driver_data(adev);
76*4882a593Smuzhiyun struct resource *res;
77*4882a593Smuzhiyun void __iomem *reg_base;
78*4882a593Smuzhiyun int ret;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * Retrieve RC base and size from a HISI0081 device with _UID
82*4882a593Smuzhiyun * matching our segment.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
85*4882a593Smuzhiyun if (!res)
86*4882a593Smuzhiyun return -ENOMEM;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
89*4882a593Smuzhiyun if (ret) {
90*4882a593Smuzhiyun dev_err(dev, "can't get rc base address\n");
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
95*4882a593Smuzhiyun if (!reg_base)
96*4882a593Smuzhiyun return -ENOMEM;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun cfg->priv = reg_base;
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun const struct pci_ecam_ops hisi_pcie_ops = {
103*4882a593Smuzhiyun .bus_shift = 20,
104*4882a593Smuzhiyun .init = hisi_pcie_init,
105*4882a593Smuzhiyun .pci_ops = {
106*4882a593Smuzhiyun .map_bus = hisi_pcie_map_bus,
107*4882a593Smuzhiyun .read = hisi_pcie_rd_conf,
108*4882a593Smuzhiyun .write = hisi_pcie_wr_conf,
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #endif
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #ifdef CONFIG_PCI_HISI
115*4882a593Smuzhiyun
hisi_pcie_platform_init(struct pci_config_window * cfg)116*4882a593Smuzhiyun static int hisi_pcie_platform_init(struct pci_config_window *cfg)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct device *dev = cfg->parent;
119*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(dev);
120*4882a593Smuzhiyun struct resource *res;
121*4882a593Smuzhiyun void __iomem *reg_base;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
124*4882a593Smuzhiyun if (!res) {
125*4882a593Smuzhiyun dev_err(dev, "missing \"reg[1]\"property\n");
126*4882a593Smuzhiyun return -EINVAL;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
130*4882a593Smuzhiyun if (!reg_base)
131*4882a593Smuzhiyun return -ENOMEM;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun cfg->priv = reg_base;
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct pci_ecam_ops hisi_pcie_platform_ops = {
138*4882a593Smuzhiyun .bus_shift = 20,
139*4882a593Smuzhiyun .init = hisi_pcie_platform_init,
140*4882a593Smuzhiyun .pci_ops = {
141*4882a593Smuzhiyun .map_bus = hisi_pcie_map_bus,
142*4882a593Smuzhiyun .read = hisi_pcie_rd_conf,
143*4882a593Smuzhiyun .write = hisi_pcie_wr_conf,
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun .compatible = "hisilicon,hip06-pcie-ecam",
150*4882a593Smuzhiyun .data = &hisi_pcie_platform_ops,
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun .compatible = "hisilicon,hip07-pcie-ecam",
154*4882a593Smuzhiyun .data = &hisi_pcie_platform_ops,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun {},
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static struct platform_driver hisi_pcie_almost_ecam_driver = {
160*4882a593Smuzhiyun .probe = pci_host_common_probe,
161*4882a593Smuzhiyun .driver = {
162*4882a593Smuzhiyun .name = "hisi-pcie-almost-ecam",
163*4882a593Smuzhiyun .of_match_table = hisi_pcie_almost_ecam_of_match,
164*4882a593Smuzhiyun .suppress_bind_attrs = true,
165*4882a593Smuzhiyun },
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun builtin_platform_driver(hisi_pcie_almost_ecam_driver);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun #endif
170*4882a593Smuzhiyun #endif
171