1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ACPI PCIe host controller driver for Rockchip SoCs
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
7 *
8 */
9
10 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
14 #include <linux/pci.h>
15
16 #include "pcie-designware.h"
17 #include "../../pci.h"
18
19 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
20
21 #define DWC_ATU_REGION_INDEX1 (0x1 << 0)
22 #define ECAM_RESV_SIZE SZ_16M
23
24 struct rk_pcie_acpi {
25 void __iomem *dbi_base;
26 void __iomem *cfg_base;
27 phys_addr_t mcfg_addr;
28 };
29
rk_pcie_writel_ob_unroll(void __iomem * dbi_base,u32 index,u32 reg,u32 val)30 static void rk_pcie_writel_ob_unroll(void __iomem *dbi_base, u32 index, u32 reg, u32 val)
31 {
32 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
33
34 writel(val, dbi_base + offset + reg + DEFAULT_DBI_ATU_OFFSET);
35 }
36
rk_pcie_readl_ob_unroll(void __iomem * dbi_base,u32 index,u32 reg)37 static u32 rk_pcie_readl_ob_unroll(void __iomem *dbi_base, u32 index, u32 reg)
38 {
39 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
40
41 return readl(dbi_base + offset + reg + DEFAULT_DBI_ATU_OFFSET);
42 }
43
rk_pcie_prog_outbound_atu_unroll(struct device * dev,void __iomem * dbi_base,u32 index,u32 type,u64 cpu_addr,u64 pci_addr,u32 size)44 static void rk_pcie_prog_outbound_atu_unroll(struct device *dev, void __iomem *dbi_base, u32 index,
45 u32 type, u64 cpu_addr, u64 pci_addr, u32 size)
46 {
47 u32 retries, val;
48
49 dev_dbg(dev, "%s: ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
50 __func__, index, type, cpu_addr, pci_addr, size);
51
52 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr));
53 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(cpu_addr));
54 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_LIMIT, lower_32_bits(cpu_addr + size - 1));
55 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_LIMIT, upper_32_bits(cpu_addr + size - 1));
56 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr));
57 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr));
58 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL1, type);
59 rk_pcie_writel_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE);
60
61 /*
62 * Make sure ATU enable takes effect before any subsequent config
63 * and I/O accesses.
64 */
65 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
66 val = rk_pcie_readl_ob_unroll(dbi_base, index, PCIE_ATU_UNR_REGION_CTRL2);
67 if (val & PCIE_ATU_ENABLE)
68 return;
69 mdelay(LINK_WAIT_IATU);
70 }
71
72 dev_err(dev, "outbound iATU is not being enabled\n");
73 }
74
rk_pcie_ecam_init(struct pci_config_window * cfg)75 static int rk_pcie_ecam_init(struct pci_config_window *cfg)
76 {
77 struct device *dev = cfg->parent;
78 struct acpi_device *adev = to_acpi_device(dev);
79 struct acpi_pci_root *root = acpi_driver_data(adev);
80 struct resource *res;
81 phys_addr_t mcfg_addr;
82 struct rk_pcie_acpi *rk_pcie;
83 int ret;
84
85 rk_pcie = devm_kzalloc(dev, sizeof(*rk_pcie), GFP_KERNEL);
86 if (!rk_pcie)
87 return -ENOMEM;
88
89 /*
90 * Retrieve RC base and size from a RKCP0001 device with _UID
91 * matching our segment.
92 */
93 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
94 if (!res)
95 return -ENOMEM;
96
97 ret = acpi_get_rc_resources(dev, "RKCP0001", root->segment, res);
98 if (ret) {
99 dev_err(dev, "can't get rc base (DBI) address\n");
100 return -ENOMEM;
101 }
102
103 dev_info(dev, "DBI address is %pa\n", &res->start);
104 rk_pcie->dbi_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
105 if (!rk_pcie->dbi_base)
106 return -ENOMEM;
107
108 mcfg_addr = acpi_pci_root_get_mcfg_addr(adev->handle);
109 if (!mcfg_addr) {
110 dev_err(dev, "can't get mcfg base (cfg) address\n");
111 return -ENOMEM;
112 }
113
114 dev_info(dev, "mcfg address is %pa\n", &mcfg_addr);
115 rk_pcie->mcfg_addr = mcfg_addr;
116
117 rk_pcie->cfg_base = devm_pci_remap_cfgspace(dev, mcfg_addr, SZ_1M);
118 if (!rk_pcie->cfg_base)
119 return -ENOMEM;
120
121 cfg->priv = rk_pcie;
122
123 return 0;
124 }
125
rk_pcie_ecam_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)126 static int rk_pcie_ecam_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val)
127 {
128 struct pci_config_window *cfg = bus->sysdata;
129 int dev = PCI_SLOT(devfn);
130
131 /* access only one slot on each root port */
132 if (bus->number == cfg->busr.start && dev > 0)
133 return PCIBIOS_DEVICE_NOT_FOUND;
134
135 return pci_generic_config_read(bus, devfn, where, size, val);
136 }
137
rk_pcie_ecam_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)138 static int rk_pcie_ecam_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val)
139 {
140 struct pci_config_window *cfg = bus->sysdata;
141 int dev = PCI_SLOT(devfn);
142
143 /* access only one slot on each root port */
144 if (bus->number == cfg->busr.start && dev > 0)
145 return PCIBIOS_DEVICE_NOT_FOUND;
146
147 return pci_generic_config_write(bus, devfn, where, size, val);
148 }
149
rk_pcie_ecam_map_bus(struct pci_bus * bus,unsigned int devfn,int where)150 static void __iomem *rk_pcie_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
151 {
152 struct pci_config_window *cfg = bus->sysdata;
153 struct rk_pcie_acpi *rk_pcie = cfg->priv;
154 u32 atu_type;
155 u32 busdev;
156
157 /* read RC config space */
158 if (bus->number == cfg->busr.start)
159 return rk_pcie->dbi_base + where;
160
161 if (pci_is_root_bus(bus->parent))
162 atu_type = PCIE_ATU_TYPE_CFG0;
163 else
164 atu_type = PCIE_ATU_TYPE_CFG1;
165
166 busdev = PCIE_ATU_BUS(bus->number) |
167 PCIE_ATU_DEV(PCI_SLOT(devfn)) |
168 PCIE_ATU_FUNC(PCI_FUNC(devfn));
169
170 /*
171 * UEFI region mapping relation:
172 * index0: 32-bit np memory
173 * index1: config
174 * index2: IO
175 * index3: 64-bit np memory
176 */
177 rk_pcie_prog_outbound_atu_unroll(cfg->parent, rk_pcie->dbi_base, DWC_ATU_REGION_INDEX1,
178 atu_type, (u64)rk_pcie->mcfg_addr, busdev, ECAM_RESV_SIZE);
179
180 dev_dbg(cfg->parent, "Read other config: 0x%p where = %d\n",
181 rk_pcie->cfg_base + where, where);
182
183 return rk_pcie->cfg_base + where;
184 }
185
186 const struct pci_ecam_ops rk_pcie_ecam_ops = {
187 .bus_shift = 20, /* We don't need this */
188 .init = rk_pcie_ecam_init,
189 .pci_ops = {
190 .map_bus = rk_pcie_ecam_map_bus,
191 .read = rk_pcie_ecam_rd_conf,
192 .write = rk_pcie_ecam_wr_conf,
193 }
194 };
195 #endif
196