1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __PCIE_DW_DMATEST_H 6*4882a593Smuzhiyun #define __PCIE_DW_DMATEST_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun struct dma_trx_obj; 9*4882a593Smuzhiyun struct device; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_PCIE_DW_DMATEST) 12*4882a593Smuzhiyun struct dma_trx_obj *pcie_dw_dmatest_register(struct device *dev, bool irq_en); 13*4882a593Smuzhiyun #else pcie_dw_dmatest_register(struct device * dev,bool irq_en)14*4882a593Smuzhiyunstatic inline struct dma_trx_obj *pcie_dw_dmatest_register(struct device *dev, bool irq_en) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun return NULL; 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif 21