xref: /OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/pci-layerscape-ep.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * PCIe controller EP driver for Freescale Layerscape SoCs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018 NXP Semiconductor.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/of_pci.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/resource.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "pcie-designware.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define PCIE_DBI2_OFFSET		0x1000	/* DBI2 base address*/
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define to_ls_pcie_ep(x)	dev_get_drvdata((x)->dev)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct ls_pcie_ep_drvdata {
26*4882a593Smuzhiyun 	u32				func_offset;
27*4882a593Smuzhiyun 	const struct dw_pcie_ep_ops	*ops;
28*4882a593Smuzhiyun 	const struct dw_pcie_ops	*dw_pcie_ops;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct ls_pcie_ep {
32*4882a593Smuzhiyun 	struct dw_pcie			*pci;
33*4882a593Smuzhiyun 	struct pci_epc_features		*ls_epc;
34*4882a593Smuzhiyun 	const struct ls_pcie_ep_drvdata *drvdata;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
ls_pcie_establish_link(struct dw_pcie * pci)37*4882a593Smuzhiyun static int ls_pcie_establish_link(struct dw_pcie *pci)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
43*4882a593Smuzhiyun 	.start_link = ls_pcie_establish_link,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun static const struct pci_epc_features*
ls_pcie_ep_get_features(struct dw_pcie_ep * ep)47*4882a593Smuzhiyun ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
50*4882a593Smuzhiyun 	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return pcie->ls_epc;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
ls_pcie_ep_init(struct dw_pcie_ep * ep)55*4882a593Smuzhiyun static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
58*4882a593Smuzhiyun 	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
59*4882a593Smuzhiyun 	struct dw_pcie_ep_func *ep_func;
60*4882a593Smuzhiyun 	enum pci_barno bar;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
63*4882a593Smuzhiyun 	if (!ep_func)
64*4882a593Smuzhiyun 		return;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
67*4882a593Smuzhiyun 		dw_pcie_ep_reset_bar(pci, bar);
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
70*4882a593Smuzhiyun 	pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
ls_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,enum pci_epc_irq_type type,u16 interrupt_num)73*4882a593Smuzhiyun static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
74*4882a593Smuzhiyun 				enum pci_epc_irq_type type, u16 interrupt_num)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	switch (type) {
79*4882a593Smuzhiyun 	case PCI_EPC_IRQ_LEGACY:
80*4882a593Smuzhiyun 		return dw_pcie_ep_raise_legacy_irq(ep, func_no);
81*4882a593Smuzhiyun 	case PCI_EPC_IRQ_MSI:
82*4882a593Smuzhiyun 		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
83*4882a593Smuzhiyun 	case PCI_EPC_IRQ_MSIX:
84*4882a593Smuzhiyun 		return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
85*4882a593Smuzhiyun 							  interrupt_num);
86*4882a593Smuzhiyun 	default:
87*4882a593Smuzhiyun 		dev_err(pci->dev, "UNKNOWN IRQ type\n");
88*4882a593Smuzhiyun 		return -EINVAL;
89*4882a593Smuzhiyun 	}
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
ls_pcie_ep_func_conf_select(struct dw_pcie_ep * ep,u8 func_no)92*4882a593Smuzhiyun static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
93*4882a593Smuzhiyun 						u8 func_no)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
96*4882a593Smuzhiyun 	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	WARN_ON(func_no && !pcie->drvdata->func_offset);
99*4882a593Smuzhiyun 	return pcie->drvdata->func_offset * func_no;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
103*4882a593Smuzhiyun 	.ep_init = ls_pcie_ep_init,
104*4882a593Smuzhiyun 	.raise_irq = ls_pcie_ep_raise_irq,
105*4882a593Smuzhiyun 	.get_features = ls_pcie_ep_get_features,
106*4882a593Smuzhiyun 	.func_conf_select = ls_pcie_ep_func_conf_select,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
110*4882a593Smuzhiyun 	.ops = &ls_pcie_ep_ops,
111*4882a593Smuzhiyun 	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
115*4882a593Smuzhiyun 	.func_offset = 0x20000,
116*4882a593Smuzhiyun 	.ops = &ls_pcie_ep_ops,
117*4882a593Smuzhiyun 	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun static const struct of_device_id ls_pcie_ep_of_match[] = {
121*4882a593Smuzhiyun 	{ .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
122*4882a593Smuzhiyun 	{ .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
123*4882a593Smuzhiyun 	{ .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
124*4882a593Smuzhiyun 	{ },
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
ls_add_pcie_ep(struct ls_pcie_ep * pcie,struct platform_device * pdev)127*4882a593Smuzhiyun static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
128*4882a593Smuzhiyun 				 struct platform_device *pdev)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct dw_pcie *pci = pcie->pci;
131*4882a593Smuzhiyun 	struct device *dev = pci->dev;
132*4882a593Smuzhiyun 	struct dw_pcie_ep *ep;
133*4882a593Smuzhiyun 	struct resource *res;
134*4882a593Smuzhiyun 	int ret;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	ep = &pci->ep;
137*4882a593Smuzhiyun 	ep->ops = pcie->drvdata->ops;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
140*4882a593Smuzhiyun 	if (!res)
141*4882a593Smuzhiyun 		return -EINVAL;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	ep->phys_base = res->start;
144*4882a593Smuzhiyun 	ep->addr_size = resource_size(res);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	ret = dw_pcie_ep_init(ep);
147*4882a593Smuzhiyun 	if (ret) {
148*4882a593Smuzhiyun 		dev_err(dev, "failed to initialize endpoint\n");
149*4882a593Smuzhiyun 		return ret;
150*4882a593Smuzhiyun 	}
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return 0;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
ls_pcie_ep_probe(struct platform_device * pdev)155*4882a593Smuzhiyun static int __init ls_pcie_ep_probe(struct platform_device *pdev)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
158*4882a593Smuzhiyun 	struct dw_pcie *pci;
159*4882a593Smuzhiyun 	struct ls_pcie_ep *pcie;
160*4882a593Smuzhiyun 	struct pci_epc_features *ls_epc;
161*4882a593Smuzhiyun 	struct resource *dbi_base;
162*4882a593Smuzhiyun 	int ret;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
165*4882a593Smuzhiyun 	if (!pcie)
166*4882a593Smuzhiyun 		return -ENOMEM;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
169*4882a593Smuzhiyun 	if (!pci)
170*4882a593Smuzhiyun 		return -ENOMEM;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
173*4882a593Smuzhiyun 	if (!ls_epc)
174*4882a593Smuzhiyun 		return -ENOMEM;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	pcie->drvdata = of_device_get_match_data(dev);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	pci->dev = dev;
179*4882a593Smuzhiyun 	pci->ops = pcie->drvdata->dw_pcie_ops;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	pcie->pci = pci;
184*4882a593Smuzhiyun 	pcie->ls_epc = ls_epc;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
187*4882a593Smuzhiyun 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
188*4882a593Smuzhiyun 	if (IS_ERR(pci->dbi_base))
189*4882a593Smuzhiyun 		return PTR_ERR(pci->dbi_base);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	platform_set_drvdata(pdev, pcie);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	ret = ls_add_pcie_ep(pcie, pdev);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	return ret;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static struct platform_driver ls_pcie_ep_driver = {
201*4882a593Smuzhiyun 	.driver = {
202*4882a593Smuzhiyun 		.name = "layerscape-pcie-ep",
203*4882a593Smuzhiyun 		.of_match_table = ls_pcie_ep_of_match,
204*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
205*4882a593Smuzhiyun 	},
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
208