1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Cadence PCIe platform driver.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2019, Cadence Design Systems
6*4882a593Smuzhiyun * Author: Tom Joseph <tjoseph@cadence.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/of_pci.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pm_runtime.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include "pcie-cadence.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /**
19*4882a593Smuzhiyun * struct cdns_plat_pcie - private data for this PCIe platform driver
20*4882a593Smuzhiyun * @pcie: Cadence PCIe controller
21*4882a593Smuzhiyun * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
22*4882a593Smuzhiyun * if 0 it is in Endpoint mode.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun struct cdns_plat_pcie {
25*4882a593Smuzhiyun struct cdns_pcie *pcie;
26*4882a593Smuzhiyun bool is_rc;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct cdns_plat_pcie_of_data {
30*4882a593Smuzhiyun bool is_rc;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const struct of_device_id cdns_plat_pcie_of_match[];
34*4882a593Smuzhiyun
cdns_plat_cpu_addr_fixup(struct cdns_pcie * pcie,u64 cpu_addr)35*4882a593Smuzhiyun static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static const struct cdns_pcie_ops cdns_plat_ops = {
41*4882a593Smuzhiyun .cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
cdns_plat_pcie_probe(struct platform_device * pdev)44*4882a593Smuzhiyun static int cdns_plat_pcie_probe(struct platform_device *pdev)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun const struct cdns_plat_pcie_of_data *data;
47*4882a593Smuzhiyun struct cdns_plat_pcie *cdns_plat_pcie;
48*4882a593Smuzhiyun const struct of_device_id *match;
49*4882a593Smuzhiyun struct device *dev = &pdev->dev;
50*4882a593Smuzhiyun struct pci_host_bridge *bridge;
51*4882a593Smuzhiyun struct cdns_pcie_ep *ep;
52*4882a593Smuzhiyun struct cdns_pcie_rc *rc;
53*4882a593Smuzhiyun int phy_count;
54*4882a593Smuzhiyun bool is_rc;
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun match = of_match_device(cdns_plat_pcie_of_match, dev);
58*4882a593Smuzhiyun if (!match)
59*4882a593Smuzhiyun return -EINVAL;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun data = (struct cdns_plat_pcie_of_data *)match->data;
62*4882a593Smuzhiyun is_rc = data->is_rc;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc);
65*4882a593Smuzhiyun cdns_plat_pcie = devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL);
66*4882a593Smuzhiyun if (!cdns_plat_pcie)
67*4882a593Smuzhiyun return -ENOMEM;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun platform_set_drvdata(pdev, cdns_plat_pcie);
70*4882a593Smuzhiyun if (is_rc) {
71*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST))
72*4882a593Smuzhiyun return -ENODEV;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
75*4882a593Smuzhiyun if (!bridge)
76*4882a593Smuzhiyun return -ENOMEM;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun rc = pci_host_bridge_priv(bridge);
79*4882a593Smuzhiyun rc->pcie.dev = dev;
80*4882a593Smuzhiyun rc->pcie.ops = &cdns_plat_ops;
81*4882a593Smuzhiyun cdns_plat_pcie->pcie = &rc->pcie;
82*4882a593Smuzhiyun cdns_plat_pcie->is_rc = is_rc;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
85*4882a593Smuzhiyun if (ret) {
86*4882a593Smuzhiyun dev_err(dev, "failed to init phy\n");
87*4882a593Smuzhiyun return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun pm_runtime_enable(dev);
90*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
91*4882a593Smuzhiyun if (ret < 0) {
92*4882a593Smuzhiyun dev_err(dev, "pm_runtime_get_sync() failed\n");
93*4882a593Smuzhiyun goto err_get_sync;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ret = cdns_pcie_host_setup(rc);
97*4882a593Smuzhiyun if (ret)
98*4882a593Smuzhiyun goto err_init;
99*4882a593Smuzhiyun } else {
100*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP))
101*4882a593Smuzhiyun return -ENODEV;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
104*4882a593Smuzhiyun if (!ep)
105*4882a593Smuzhiyun return -ENOMEM;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ep->pcie.dev = dev;
108*4882a593Smuzhiyun ep->pcie.ops = &cdns_plat_ops;
109*4882a593Smuzhiyun cdns_plat_pcie->pcie = &ep->pcie;
110*4882a593Smuzhiyun cdns_plat_pcie->is_rc = is_rc;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
113*4882a593Smuzhiyun if (ret) {
114*4882a593Smuzhiyun dev_err(dev, "failed to init phy\n");
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun pm_runtime_enable(dev);
119*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
120*4882a593Smuzhiyun if (ret < 0) {
121*4882a593Smuzhiyun dev_err(dev, "pm_runtime_get_sync() failed\n");
122*4882a593Smuzhiyun goto err_get_sync;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun ret = cdns_pcie_ep_setup(ep);
126*4882a593Smuzhiyun if (ret)
127*4882a593Smuzhiyun goto err_init;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return 0;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun err_init:
133*4882a593Smuzhiyun err_get_sync:
134*4882a593Smuzhiyun pm_runtime_put_sync(dev);
135*4882a593Smuzhiyun pm_runtime_disable(dev);
136*4882a593Smuzhiyun cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
137*4882a593Smuzhiyun phy_count = cdns_plat_pcie->pcie->phy_count;
138*4882a593Smuzhiyun while (phy_count--)
139*4882a593Smuzhiyun device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
cdns_plat_pcie_shutdown(struct platform_device * pdev)144*4882a593Smuzhiyun static void cdns_plat_pcie_shutdown(struct platform_device *pdev)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct device *dev = &pdev->dev;
147*4882a593Smuzhiyun struct cdns_pcie *pcie = dev_get_drvdata(dev);
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ret = pm_runtime_put_sync(dev);
151*4882a593Smuzhiyun if (ret < 0)
152*4882a593Smuzhiyun dev_dbg(dev, "pm_runtime_put_sync failed\n");
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun pm_runtime_disable(dev);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun cdns_pcie_disable_phy(pcie);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const struct cdns_plat_pcie_of_data cdns_plat_pcie_host_of_data = {
160*4882a593Smuzhiyun .is_rc = true,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const struct cdns_plat_pcie_of_data cdns_plat_pcie_ep_of_data = {
164*4882a593Smuzhiyun .is_rc = false,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const struct of_device_id cdns_plat_pcie_of_match[] = {
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun .compatible = "cdns,cdns-pcie-host",
170*4882a593Smuzhiyun .data = &cdns_plat_pcie_host_of_data,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun .compatible = "cdns,cdns-pcie-ep",
174*4882a593Smuzhiyun .data = &cdns_plat_pcie_ep_of_data,
175*4882a593Smuzhiyun },
176*4882a593Smuzhiyun {},
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static struct platform_driver cdns_plat_pcie_driver = {
180*4882a593Smuzhiyun .driver = {
181*4882a593Smuzhiyun .name = "cdns-pcie",
182*4882a593Smuzhiyun .of_match_table = cdns_plat_pcie_of_match,
183*4882a593Smuzhiyun .pm = &cdns_pcie_pm_ops,
184*4882a593Smuzhiyun },
185*4882a593Smuzhiyun .probe = cdns_plat_pcie_probe,
186*4882a593Smuzhiyun .shutdown = cdns_plat_pcie_shutdown,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun builtin_platform_driver(cdns_plat_pcie_driver);
189