1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* IEEE-1284 operations for parport.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is for generic IEEE 1284 operations. The idea is that
5*4882a593Smuzhiyun * they are used by the low-level drivers. If they have a special way
6*4882a593Smuzhiyun * of doing something, they can provide their own routines (and put
7*4882a593Smuzhiyun * the function pointers in port->ops); if not, they can just use these
8*4882a593Smuzhiyun * as a fallback.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Note: Make no assumptions about hardware or architecture in this file!
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Author: Tim Waugh <tim@cyberelk.demon.co.uk>
13*4882a593Smuzhiyun * Fixed AUTOFD polarity in ecp_forward_to_reverse(). Fred Barnes, 1999
14*4882a593Smuzhiyun * Software emulated EPP fixes, Fred Barnes, 04/2001.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/parport.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/sched/signal.h>
22*4882a593Smuzhiyun #include <linux/uaccess.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #undef DEBUG /* undef me for production */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #ifdef CONFIG_LP_CONSOLE
27*4882a593Smuzhiyun #undef DEBUG /* Don't want a garbled console */
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*** *
31*4882a593Smuzhiyun * One-way data transfer functions. *
32*4882a593Smuzhiyun * ***/
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Compatibility mode. */
parport_ieee1284_write_compat(struct parport * port,const void * buffer,size_t len,int flags)35*4882a593Smuzhiyun size_t parport_ieee1284_write_compat (struct parport *port,
36*4882a593Smuzhiyun const void *buffer, size_t len,
37*4882a593Smuzhiyun int flags)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun int no_irq = 1;
40*4882a593Smuzhiyun ssize_t count = 0;
41*4882a593Smuzhiyun const unsigned char *addr = buffer;
42*4882a593Smuzhiyun unsigned char byte;
43*4882a593Smuzhiyun struct pardevice *dev = port->physport->cad;
44*4882a593Smuzhiyun unsigned char ctl = (PARPORT_CONTROL_SELECT
45*4882a593Smuzhiyun | PARPORT_CONTROL_INIT);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (port->irq != PARPORT_IRQ_NONE) {
48*4882a593Smuzhiyun parport_enable_irq (port);
49*4882a593Smuzhiyun no_irq = 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
53*4882a593Smuzhiyun parport_write_control (port, ctl);
54*4882a593Smuzhiyun parport_data_forward (port);
55*4882a593Smuzhiyun while (count < len) {
56*4882a593Smuzhiyun unsigned long expire = jiffies + dev->timeout;
57*4882a593Smuzhiyun long wait = msecs_to_jiffies(10);
58*4882a593Smuzhiyun unsigned char mask = (PARPORT_STATUS_ERROR
59*4882a593Smuzhiyun | PARPORT_STATUS_BUSY);
60*4882a593Smuzhiyun unsigned char val = (PARPORT_STATUS_ERROR
61*4882a593Smuzhiyun | PARPORT_STATUS_BUSY);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Wait until the peripheral's ready */
64*4882a593Smuzhiyun do {
65*4882a593Smuzhiyun /* Is the peripheral ready yet? */
66*4882a593Smuzhiyun if (!parport_wait_peripheral (port, mask, val))
67*4882a593Smuzhiyun /* Skip the loop */
68*4882a593Smuzhiyun goto ready;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Is the peripheral upset? */
71*4882a593Smuzhiyun if ((parport_read_status (port) &
72*4882a593Smuzhiyun (PARPORT_STATUS_PAPEROUT |
73*4882a593Smuzhiyun PARPORT_STATUS_SELECT |
74*4882a593Smuzhiyun PARPORT_STATUS_ERROR))
75*4882a593Smuzhiyun != (PARPORT_STATUS_SELECT |
76*4882a593Smuzhiyun PARPORT_STATUS_ERROR))
77*4882a593Smuzhiyun /* If nFault is asserted (i.e. no
78*4882a593Smuzhiyun * error) and PAPEROUT and SELECT are
79*4882a593Smuzhiyun * just red herrings, give the driver
80*4882a593Smuzhiyun * a chance to check it's happy with
81*4882a593Smuzhiyun * that before continuing. */
82*4882a593Smuzhiyun goto stop;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Have we run out of time? */
85*4882a593Smuzhiyun if (!time_before (jiffies, expire))
86*4882a593Smuzhiyun break;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Yield the port for a while. If this is the
89*4882a593Smuzhiyun first time around the loop, don't let go of
90*4882a593Smuzhiyun the port. This way, we find out if we have
91*4882a593Smuzhiyun our interrupt handler called. */
92*4882a593Smuzhiyun if (count && no_irq) {
93*4882a593Smuzhiyun parport_release (dev);
94*4882a593Smuzhiyun schedule_timeout_interruptible(wait);
95*4882a593Smuzhiyun parport_claim_or_block (dev);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun else
98*4882a593Smuzhiyun /* We must have the device claimed here */
99*4882a593Smuzhiyun parport_wait_event (port, wait);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Is there a signal pending? */
102*4882a593Smuzhiyun if (signal_pending (current))
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Wait longer next time. */
106*4882a593Smuzhiyun wait *= 2;
107*4882a593Smuzhiyun } while (time_before (jiffies, expire));
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (signal_pending (current))
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun pr_debug("%s: Timed out\n", port->name);
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ready:
116*4882a593Smuzhiyun /* Write the character to the data lines. */
117*4882a593Smuzhiyun byte = *addr++;
118*4882a593Smuzhiyun parport_write_data (port, byte);
119*4882a593Smuzhiyun udelay (1);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Pulse strobe. */
122*4882a593Smuzhiyun parport_write_control (port, ctl | PARPORT_CONTROL_STROBE);
123*4882a593Smuzhiyun udelay (1); /* strobe */
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun parport_write_control (port, ctl);
126*4882a593Smuzhiyun udelay (1); /* hold */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Assume the peripheral received it. */
129*4882a593Smuzhiyun count++;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Let another process run if it needs to. */
132*4882a593Smuzhiyun if (time_before (jiffies, expire))
133*4882a593Smuzhiyun if (!parport_yield_blocking (dev)
134*4882a593Smuzhiyun && need_resched())
135*4882a593Smuzhiyun schedule ();
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun stop:
138*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return count;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Nibble mode. */
parport_ieee1284_read_nibble(struct parport * port,void * buffer,size_t len,int flags)144*4882a593Smuzhiyun size_t parport_ieee1284_read_nibble (struct parport *port,
145*4882a593Smuzhiyun void *buffer, size_t len,
146*4882a593Smuzhiyun int flags)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun #ifndef CONFIG_PARPORT_1284
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun #else
151*4882a593Smuzhiyun unsigned char *buf = buffer;
152*4882a593Smuzhiyun int i;
153*4882a593Smuzhiyun unsigned char byte = 0;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun len *= 2; /* in nibbles */
156*4882a593Smuzhiyun for (i=0; i < len; i++) {
157*4882a593Smuzhiyun unsigned char nibble;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* Does the error line indicate end of data? */
160*4882a593Smuzhiyun if (((i & 1) == 0) &&
161*4882a593Smuzhiyun (parport_read_status(port) & PARPORT_STATUS_ERROR)) {
162*4882a593Smuzhiyun goto end_of_data;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Event 7: Set nAutoFd low. */
166*4882a593Smuzhiyun parport_frob_control (port,
167*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
168*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* Event 9: nAck goes low. */
171*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_REV_DATA;
172*4882a593Smuzhiyun if (parport_wait_peripheral (port,
173*4882a593Smuzhiyun PARPORT_STATUS_ACK, 0)) {
174*4882a593Smuzhiyun /* Timeout -- no more data? */
175*4882a593Smuzhiyun pr_debug("%s: Nibble timeout at event 9 (%d bytes)\n",
176*4882a593Smuzhiyun port->name, i / 2);
177*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0);
178*4882a593Smuzhiyun break;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* Read a nibble. */
183*4882a593Smuzhiyun nibble = parport_read_status (port) >> 3;
184*4882a593Smuzhiyun nibble &= ~8;
185*4882a593Smuzhiyun if ((nibble & 0x10) == 0)
186*4882a593Smuzhiyun nibble |= 8;
187*4882a593Smuzhiyun nibble &= 0xf;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Event 10: Set nAutoFd high. */
190*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Event 11: nAck goes high. */
193*4882a593Smuzhiyun if (parport_wait_peripheral (port,
194*4882a593Smuzhiyun PARPORT_STATUS_ACK,
195*4882a593Smuzhiyun PARPORT_STATUS_ACK)) {
196*4882a593Smuzhiyun /* Timeout -- no more data? */
197*4882a593Smuzhiyun pr_debug("%s: Nibble timeout at event 11\n",
198*4882a593Smuzhiyun port->name);
199*4882a593Smuzhiyun break;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (i & 1) {
203*4882a593Smuzhiyun /* Second nibble */
204*4882a593Smuzhiyun byte |= nibble << 4;
205*4882a593Smuzhiyun *buf++ = byte;
206*4882a593Smuzhiyun } else
207*4882a593Smuzhiyun byte = nibble;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun if (i == len) {
211*4882a593Smuzhiyun /* Read the last nibble without checking data avail. */
212*4882a593Smuzhiyun if (parport_read_status (port) & PARPORT_STATUS_ERROR) {
213*4882a593Smuzhiyun end_of_data:
214*4882a593Smuzhiyun pr_debug("%s: No more nibble data (%d bytes)\n",
215*4882a593Smuzhiyun port->name, i / 2);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* Go to reverse idle phase. */
218*4882a593Smuzhiyun parport_frob_control (port,
219*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
220*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
221*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun else
224*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun return i/2;
228*4882a593Smuzhiyun #endif /* IEEE1284 support */
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* Byte mode. */
parport_ieee1284_read_byte(struct parport * port,void * buffer,size_t len,int flags)232*4882a593Smuzhiyun size_t parport_ieee1284_read_byte (struct parport *port,
233*4882a593Smuzhiyun void *buffer, size_t len,
234*4882a593Smuzhiyun int flags)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun #ifndef CONFIG_PARPORT_1284
237*4882a593Smuzhiyun return 0;
238*4882a593Smuzhiyun #else
239*4882a593Smuzhiyun unsigned char *buf = buffer;
240*4882a593Smuzhiyun ssize_t count = 0;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun for (count = 0; count < len; count++) {
243*4882a593Smuzhiyun unsigned char byte;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* Data available? */
246*4882a593Smuzhiyun if (parport_read_status (port) & PARPORT_STATUS_ERROR) {
247*4882a593Smuzhiyun goto end_of_data;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* Event 14: Place data bus in high impedance state. */
251*4882a593Smuzhiyun parport_data_reverse (port);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* Event 7: Set nAutoFd low. */
254*4882a593Smuzhiyun parport_frob_control (port,
255*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
256*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* Event 9: nAck goes low. */
259*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA;
260*4882a593Smuzhiyun if (parport_wait_peripheral (port,
261*4882a593Smuzhiyun PARPORT_STATUS_ACK,
262*4882a593Smuzhiyun 0)) {
263*4882a593Smuzhiyun /* Timeout -- no more data? */
264*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD,
265*4882a593Smuzhiyun 0);
266*4882a593Smuzhiyun pr_debug("%s: Byte timeout at event 9\n", port->name);
267*4882a593Smuzhiyun break;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun byte = parport_read_data (port);
271*4882a593Smuzhiyun *buf++ = byte;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /* Event 10: Set nAutoFd high */
274*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /* Event 11: nAck goes high. */
277*4882a593Smuzhiyun if (parport_wait_peripheral (port,
278*4882a593Smuzhiyun PARPORT_STATUS_ACK,
279*4882a593Smuzhiyun PARPORT_STATUS_ACK)) {
280*4882a593Smuzhiyun /* Timeout -- no more data? */
281*4882a593Smuzhiyun pr_debug("%s: Byte timeout at event 11\n", port->name);
282*4882a593Smuzhiyun break;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* Event 16: Set nStrobe low. */
286*4882a593Smuzhiyun parport_frob_control (port,
287*4882a593Smuzhiyun PARPORT_CONTROL_STROBE,
288*4882a593Smuzhiyun PARPORT_CONTROL_STROBE);
289*4882a593Smuzhiyun udelay (5);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* Event 17: Set nStrobe high. */
292*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE, 0);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (count == len) {
296*4882a593Smuzhiyun /* Read the last byte without checking data avail. */
297*4882a593Smuzhiyun if (parport_read_status (port) & PARPORT_STATUS_ERROR) {
298*4882a593Smuzhiyun end_of_data:
299*4882a593Smuzhiyun pr_debug("%s: No more byte data (%zd bytes)\n",
300*4882a593Smuzhiyun port->name, count);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* Go to reverse idle phase. */
303*4882a593Smuzhiyun parport_frob_control (port,
304*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
305*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
306*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun else
309*4882a593Smuzhiyun port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun return count;
313*4882a593Smuzhiyun #endif /* IEEE1284 support */
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /*** *
317*4882a593Smuzhiyun * ECP Functions. *
318*4882a593Smuzhiyun * ***/
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun #ifdef CONFIG_PARPORT_1284
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun static inline
ecp_forward_to_reverse(struct parport * port)323*4882a593Smuzhiyun int ecp_forward_to_reverse (struct parport *port)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun int retval;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* Event 38: Set nAutoFd low */
328*4882a593Smuzhiyun parport_frob_control (port,
329*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
330*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
331*4882a593Smuzhiyun parport_data_reverse (port);
332*4882a593Smuzhiyun udelay (5);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Event 39: Set nInit low to initiate bus reversal */
335*4882a593Smuzhiyun parport_frob_control (port,
336*4882a593Smuzhiyun PARPORT_CONTROL_INIT,
337*4882a593Smuzhiyun 0);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* Event 40: PError goes low */
340*4882a593Smuzhiyun retval = parport_wait_peripheral (port,
341*4882a593Smuzhiyun PARPORT_STATUS_PAPEROUT, 0);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun if (!retval) {
344*4882a593Smuzhiyun pr_debug("%s: ECP direction: reverse\n", port->name);
345*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
346*4882a593Smuzhiyun } else {
347*4882a593Smuzhiyun pr_debug("%s: ECP direction: failed to reverse\n", port->name);
348*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return retval;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static inline
ecp_reverse_to_forward(struct parport * port)355*4882a593Smuzhiyun int ecp_reverse_to_forward (struct parport *port)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun int retval;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun /* Event 47: Set nInit high */
360*4882a593Smuzhiyun parport_frob_control (port,
361*4882a593Smuzhiyun PARPORT_CONTROL_INIT
362*4882a593Smuzhiyun | PARPORT_CONTROL_AUTOFD,
363*4882a593Smuzhiyun PARPORT_CONTROL_INIT
364*4882a593Smuzhiyun | PARPORT_CONTROL_AUTOFD);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* Event 49: PError goes high */
367*4882a593Smuzhiyun retval = parport_wait_peripheral (port,
368*4882a593Smuzhiyun PARPORT_STATUS_PAPEROUT,
369*4882a593Smuzhiyun PARPORT_STATUS_PAPEROUT);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (!retval) {
372*4882a593Smuzhiyun parport_data_forward (port);
373*4882a593Smuzhiyun pr_debug("%s: ECP direction: forward\n", port->name);
374*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
375*4882a593Smuzhiyun } else {
376*4882a593Smuzhiyun pr_debug("%s: ECP direction: failed to switch forward\n",
377*4882a593Smuzhiyun port->name);
378*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun return retval;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun #endif /* IEEE1284 support */
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* ECP mode, forward channel, data. */
parport_ieee1284_ecp_write_data(struct parport * port,const void * buffer,size_t len,int flags)388*4882a593Smuzhiyun size_t parport_ieee1284_ecp_write_data (struct parport *port,
389*4882a593Smuzhiyun const void *buffer, size_t len,
390*4882a593Smuzhiyun int flags)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun #ifndef CONFIG_PARPORT_1284
393*4882a593Smuzhiyun return 0;
394*4882a593Smuzhiyun #else
395*4882a593Smuzhiyun const unsigned char *buf = buffer;
396*4882a593Smuzhiyun size_t written;
397*4882a593Smuzhiyun int retry;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun port = port->physport;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE)
402*4882a593Smuzhiyun if (ecp_reverse_to_forward (port))
403*4882a593Smuzhiyun return 0;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_FWD_DATA;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* HostAck high (data, not command) */
408*4882a593Smuzhiyun parport_frob_control (port,
409*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD
410*4882a593Smuzhiyun | PARPORT_CONTROL_STROBE
411*4882a593Smuzhiyun | PARPORT_CONTROL_INIT,
412*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
413*4882a593Smuzhiyun for (written = 0; written < len; written++, buf++) {
414*4882a593Smuzhiyun unsigned long expire = jiffies + port->cad->timeout;
415*4882a593Smuzhiyun unsigned char byte;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun byte = *buf;
418*4882a593Smuzhiyun try_again:
419*4882a593Smuzhiyun parport_write_data (port, byte);
420*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE,
421*4882a593Smuzhiyun PARPORT_CONTROL_STROBE);
422*4882a593Smuzhiyun udelay (5);
423*4882a593Smuzhiyun for (retry = 0; retry < 100; retry++) {
424*4882a593Smuzhiyun if (!parport_wait_peripheral (port,
425*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 0))
426*4882a593Smuzhiyun goto success;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (signal_pending (current)) {
429*4882a593Smuzhiyun parport_frob_control (port,
430*4882a593Smuzhiyun PARPORT_CONTROL_STROBE,
431*4882a593Smuzhiyun 0);
432*4882a593Smuzhiyun break;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /* Time for Host Transfer Recovery (page 41 of IEEE1284) */
437*4882a593Smuzhiyun pr_debug("%s: ECP transfer stalled!\n", port->name);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT,
440*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
441*4882a593Smuzhiyun udelay (50);
442*4882a593Smuzhiyun if (parport_read_status (port) & PARPORT_STATUS_PAPEROUT) {
443*4882a593Smuzhiyun /* It's buggered. */
444*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
445*4882a593Smuzhiyun break;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
449*4882a593Smuzhiyun udelay (50);
450*4882a593Smuzhiyun if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT))
451*4882a593Smuzhiyun break;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun pr_debug("%s: Host transfer recovered\n", port->name);
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun if (time_after_eq (jiffies, expire)) break;
456*4882a593Smuzhiyun goto try_again;
457*4882a593Smuzhiyun success:
458*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE, 0);
459*4882a593Smuzhiyun udelay (5);
460*4882a593Smuzhiyun if (parport_wait_peripheral (port,
461*4882a593Smuzhiyun PARPORT_STATUS_BUSY,
462*4882a593Smuzhiyun PARPORT_STATUS_BUSY))
463*4882a593Smuzhiyun /* Peripheral hasn't accepted the data. */
464*4882a593Smuzhiyun break;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun return written;
470*4882a593Smuzhiyun #endif /* IEEE1284 support */
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /* ECP mode, reverse channel, data. */
parport_ieee1284_ecp_read_data(struct parport * port,void * buffer,size_t len,int flags)474*4882a593Smuzhiyun size_t parport_ieee1284_ecp_read_data (struct parport *port,
475*4882a593Smuzhiyun void *buffer, size_t len, int flags)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun #ifndef CONFIG_PARPORT_1284
478*4882a593Smuzhiyun return 0;
479*4882a593Smuzhiyun #else
480*4882a593Smuzhiyun struct pardevice *dev = port->cad;
481*4882a593Smuzhiyun unsigned char *buf = buffer;
482*4882a593Smuzhiyun int rle_count = 0; /* shut gcc up */
483*4882a593Smuzhiyun unsigned char ctl;
484*4882a593Smuzhiyun int rle = 0;
485*4882a593Smuzhiyun ssize_t count = 0;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun port = port->physport;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE)
490*4882a593Smuzhiyun if (ecp_forward_to_reverse (port))
491*4882a593Smuzhiyun return 0;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_REV_DATA;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun /* Set HostAck low to start accepting data. */
496*4882a593Smuzhiyun ctl = parport_read_control (port);
497*4882a593Smuzhiyun ctl &= ~(PARPORT_CONTROL_STROBE | PARPORT_CONTROL_INIT |
498*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
499*4882a593Smuzhiyun parport_write_control (port,
500*4882a593Smuzhiyun ctl | PARPORT_CONTROL_AUTOFD);
501*4882a593Smuzhiyun while (count < len) {
502*4882a593Smuzhiyun unsigned long expire = jiffies + dev->timeout;
503*4882a593Smuzhiyun unsigned char byte;
504*4882a593Smuzhiyun int command;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* Event 43: Peripheral sets nAck low. It can take as
507*4882a593Smuzhiyun long as it wants. */
508*4882a593Smuzhiyun while (parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0)) {
509*4882a593Smuzhiyun /* The peripheral hasn't given us data in
510*4882a593Smuzhiyun 35ms. If we have data to give back to the
511*4882a593Smuzhiyun caller, do it now. */
512*4882a593Smuzhiyun if (count)
513*4882a593Smuzhiyun goto out;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun /* If we've used up all the time we were allowed,
516*4882a593Smuzhiyun give up altogether. */
517*4882a593Smuzhiyun if (!time_before (jiffies, expire))
518*4882a593Smuzhiyun goto out;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun /* Yield the port for a while. */
521*4882a593Smuzhiyun if (dev->port->irq != PARPORT_IRQ_NONE) {
522*4882a593Smuzhiyun parport_release (dev);
523*4882a593Smuzhiyun schedule_timeout_interruptible(msecs_to_jiffies(40));
524*4882a593Smuzhiyun parport_claim_or_block (dev);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun else
527*4882a593Smuzhiyun /* We must have the device claimed here. */
528*4882a593Smuzhiyun parport_wait_event (port, msecs_to_jiffies(40));
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun /* Is there a signal pending? */
531*4882a593Smuzhiyun if (signal_pending (current))
532*4882a593Smuzhiyun goto out;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* Is this a command? */
536*4882a593Smuzhiyun if (rle)
537*4882a593Smuzhiyun /* The last byte was a run-length count, so
538*4882a593Smuzhiyun this can't be as well. */
539*4882a593Smuzhiyun command = 0;
540*4882a593Smuzhiyun else
541*4882a593Smuzhiyun command = (parport_read_status (port) &
542*4882a593Smuzhiyun PARPORT_STATUS_BUSY) ? 1 : 0;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun /* Read the data. */
545*4882a593Smuzhiyun byte = parport_read_data (port);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun /* If this is a channel command, rather than an RLE
548*4882a593Smuzhiyun command or a normal data byte, don't accept it. */
549*4882a593Smuzhiyun if (command) {
550*4882a593Smuzhiyun if (byte & 0x80) {
551*4882a593Smuzhiyun pr_debug("%s: stopping short at channel command (%02x)\n",
552*4882a593Smuzhiyun port->name, byte);
553*4882a593Smuzhiyun goto out;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun else if (port->ieee1284.mode != IEEE1284_MODE_ECPRLE)
556*4882a593Smuzhiyun pr_debug("%s: device illegally using RLE; accepting anyway\n",
557*4882a593Smuzhiyun port->name);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun rle_count = byte + 1;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun /* Are we allowed to read that many bytes? */
562*4882a593Smuzhiyun if (rle_count > (len - count)) {
563*4882a593Smuzhiyun pr_debug("%s: leaving %d RLE bytes for next time\n",
564*4882a593Smuzhiyun port->name, rle_count);
565*4882a593Smuzhiyun break;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun rle = 1;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /* Event 44: Set HostAck high, acknowledging handshake. */
572*4882a593Smuzhiyun parport_write_control (port, ctl);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun /* Event 45: The peripheral has 35ms to set nAck high. */
575*4882a593Smuzhiyun if (parport_wait_peripheral (port, PARPORT_STATUS_ACK,
576*4882a593Smuzhiyun PARPORT_STATUS_ACK)) {
577*4882a593Smuzhiyun /* It's gone wrong. Return what data we have
578*4882a593Smuzhiyun to the caller. */
579*4882a593Smuzhiyun pr_debug("ECP read timed out at 45\n");
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun if (command)
582*4882a593Smuzhiyun pr_warn("%s: command ignored (%02x)\n",
583*4882a593Smuzhiyun port->name, byte);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun break;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun /* Event 46: Set HostAck low and accept the data. */
589*4882a593Smuzhiyun parport_write_control (port,
590*4882a593Smuzhiyun ctl | PARPORT_CONTROL_AUTOFD);
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun /* If we just read a run-length count, fetch the data. */
593*4882a593Smuzhiyun if (command)
594*4882a593Smuzhiyun continue;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun /* If this is the byte after a run-length count, decompress. */
597*4882a593Smuzhiyun if (rle) {
598*4882a593Smuzhiyun rle = 0;
599*4882a593Smuzhiyun memset (buf, byte, rle_count);
600*4882a593Smuzhiyun buf += rle_count;
601*4882a593Smuzhiyun count += rle_count;
602*4882a593Smuzhiyun pr_debug("%s: decompressed to %d bytes\n",
603*4882a593Smuzhiyun port->name, rle_count);
604*4882a593Smuzhiyun } else {
605*4882a593Smuzhiyun /* Normal data byte. */
606*4882a593Smuzhiyun *buf = byte;
607*4882a593Smuzhiyun buf++, count++;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun out:
612*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
613*4882a593Smuzhiyun return count;
614*4882a593Smuzhiyun #endif /* IEEE1284 support */
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun /* ECP mode, forward channel, commands. */
parport_ieee1284_ecp_write_addr(struct parport * port,const void * buffer,size_t len,int flags)618*4882a593Smuzhiyun size_t parport_ieee1284_ecp_write_addr (struct parport *port,
619*4882a593Smuzhiyun const void *buffer, size_t len,
620*4882a593Smuzhiyun int flags)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun #ifndef CONFIG_PARPORT_1284
623*4882a593Smuzhiyun return 0;
624*4882a593Smuzhiyun #else
625*4882a593Smuzhiyun const unsigned char *buf = buffer;
626*4882a593Smuzhiyun size_t written;
627*4882a593Smuzhiyun int retry;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun port = port->physport;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE)
632*4882a593Smuzhiyun if (ecp_reverse_to_forward (port))
633*4882a593Smuzhiyun return 0;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_FWD_DATA;
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun /* HostAck low (command, not data) */
638*4882a593Smuzhiyun parport_frob_control (port,
639*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD
640*4882a593Smuzhiyun | PARPORT_CONTROL_STROBE
641*4882a593Smuzhiyun | PARPORT_CONTROL_INIT,
642*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD
643*4882a593Smuzhiyun | PARPORT_CONTROL_INIT);
644*4882a593Smuzhiyun for (written = 0; written < len; written++, buf++) {
645*4882a593Smuzhiyun unsigned long expire = jiffies + port->cad->timeout;
646*4882a593Smuzhiyun unsigned char byte;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun byte = *buf;
649*4882a593Smuzhiyun try_again:
650*4882a593Smuzhiyun parport_write_data (port, byte);
651*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE,
652*4882a593Smuzhiyun PARPORT_CONTROL_STROBE);
653*4882a593Smuzhiyun udelay (5);
654*4882a593Smuzhiyun for (retry = 0; retry < 100; retry++) {
655*4882a593Smuzhiyun if (!parport_wait_peripheral (port,
656*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 0))
657*4882a593Smuzhiyun goto success;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun if (signal_pending (current)) {
660*4882a593Smuzhiyun parport_frob_control (port,
661*4882a593Smuzhiyun PARPORT_CONTROL_STROBE,
662*4882a593Smuzhiyun 0);
663*4882a593Smuzhiyun break;
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun /* Time for Host Transfer Recovery (page 41 of IEEE1284) */
668*4882a593Smuzhiyun pr_debug("%s: ECP transfer stalled!\n", port->name);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT,
671*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
672*4882a593Smuzhiyun udelay (50);
673*4882a593Smuzhiyun if (parport_read_status (port) & PARPORT_STATUS_PAPEROUT) {
674*4882a593Smuzhiyun /* It's buggered. */
675*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
676*4882a593Smuzhiyun break;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
680*4882a593Smuzhiyun udelay (50);
681*4882a593Smuzhiyun if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT))
682*4882a593Smuzhiyun break;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun pr_debug("%s: Host transfer recovered\n", port->name);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun if (time_after_eq (jiffies, expire)) break;
687*4882a593Smuzhiyun goto try_again;
688*4882a593Smuzhiyun success:
689*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE, 0);
690*4882a593Smuzhiyun udelay (5);
691*4882a593Smuzhiyun if (parport_wait_peripheral (port,
692*4882a593Smuzhiyun PARPORT_STATUS_BUSY,
693*4882a593Smuzhiyun PARPORT_STATUS_BUSY))
694*4882a593Smuzhiyun /* Peripheral hasn't accepted the data. */
695*4882a593Smuzhiyun break;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun return written;
701*4882a593Smuzhiyun #endif /* IEEE1284 support */
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun /*** *
705*4882a593Smuzhiyun * EPP functions. *
706*4882a593Smuzhiyun * ***/
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun /* EPP mode, forward channel, data. */
parport_ieee1284_epp_write_data(struct parport * port,const void * buffer,size_t len,int flags)709*4882a593Smuzhiyun size_t parport_ieee1284_epp_write_data (struct parport *port,
710*4882a593Smuzhiyun const void *buffer, size_t len,
711*4882a593Smuzhiyun int flags)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun unsigned char *bp = (unsigned char *) buffer;
714*4882a593Smuzhiyun size_t ret = 0;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun /* set EPP idle state (just to make sure) with strobe low */
717*4882a593Smuzhiyun parport_frob_control (port,
718*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
719*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD |
720*4882a593Smuzhiyun PARPORT_CONTROL_SELECT |
721*4882a593Smuzhiyun PARPORT_CONTROL_INIT,
722*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
723*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
724*4882a593Smuzhiyun port->ops->data_forward (port);
725*4882a593Smuzhiyun for (; len > 0; len--, bp++) {
726*4882a593Smuzhiyun /* Event 62: Write data and set autofd low */
727*4882a593Smuzhiyun parport_write_data (port, *bp);
728*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD,
729*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun /* Event 58: wait for busy (nWait) to go high */
732*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY, 0, 10))
733*4882a593Smuzhiyun break;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun /* Event 63: set nAutoFd (nDStrb) high */
736*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0);
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /* Event 60: wait for busy (nWait) to go low */
739*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY,
740*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 5))
741*4882a593Smuzhiyun break;
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun ret++;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun /* Event 61: set strobe (nWrite) high */
747*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE, 0);
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun return ret;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun /* EPP mode, reverse channel, data. */
parport_ieee1284_epp_read_data(struct parport * port,void * buffer,size_t len,int flags)753*4882a593Smuzhiyun size_t parport_ieee1284_epp_read_data (struct parport *port,
754*4882a593Smuzhiyun void *buffer, size_t len,
755*4882a593Smuzhiyun int flags)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun unsigned char *bp = (unsigned char *) buffer;
758*4882a593Smuzhiyun unsigned ret = 0;
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun /* set EPP idle state (just to make sure) with strobe high */
761*4882a593Smuzhiyun parport_frob_control (port,
762*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
763*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD |
764*4882a593Smuzhiyun PARPORT_CONTROL_SELECT |
765*4882a593Smuzhiyun PARPORT_CONTROL_INIT,
766*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
767*4882a593Smuzhiyun port->ops->data_reverse (port);
768*4882a593Smuzhiyun for (; len > 0; len--, bp++) {
769*4882a593Smuzhiyun /* Event 67: set nAutoFd (nDStrb) low */
770*4882a593Smuzhiyun parport_frob_control (port,
771*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD,
772*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD);
773*4882a593Smuzhiyun /* Event 58: wait for Busy to go high */
774*4882a593Smuzhiyun if (parport_wait_peripheral (port, PARPORT_STATUS_BUSY, 0)) {
775*4882a593Smuzhiyun break;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun *bp = parport_read_data (port);
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun /* Event 63: set nAutoFd (nDStrb) high */
781*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0);
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun /* Event 60: wait for Busy to go low */
784*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY,
785*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 5)) {
786*4882a593Smuzhiyun break;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun ret++;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun port->ops->data_forward (port);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun return ret;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun /* EPP mode, forward channel, addresses. */
parport_ieee1284_epp_write_addr(struct parport * port,const void * buffer,size_t len,int flags)797*4882a593Smuzhiyun size_t parport_ieee1284_epp_write_addr (struct parport *port,
798*4882a593Smuzhiyun const void *buffer, size_t len,
799*4882a593Smuzhiyun int flags)
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun unsigned char *bp = (unsigned char *) buffer;
802*4882a593Smuzhiyun size_t ret = 0;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun /* set EPP idle state (just to make sure) with strobe low */
805*4882a593Smuzhiyun parport_frob_control (port,
806*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
807*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD |
808*4882a593Smuzhiyun PARPORT_CONTROL_SELECT |
809*4882a593Smuzhiyun PARPORT_CONTROL_INIT,
810*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
811*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
812*4882a593Smuzhiyun port->ops->data_forward (port);
813*4882a593Smuzhiyun for (; len > 0; len--, bp++) {
814*4882a593Smuzhiyun /* Event 56: Write data and set nAStrb low. */
815*4882a593Smuzhiyun parport_write_data (port, *bp);
816*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_SELECT,
817*4882a593Smuzhiyun PARPORT_CONTROL_SELECT);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /* Event 58: wait for busy (nWait) to go high */
820*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY, 0, 10))
821*4882a593Smuzhiyun break;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun /* Event 59: set nAStrb high */
824*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_SELECT, 0);
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun /* Event 60: wait for busy (nWait) to go low */
827*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY,
828*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 5))
829*4882a593Smuzhiyun break;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun ret++;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun /* Event 61: set strobe (nWrite) high */
835*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_STROBE, 0);
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun return ret;
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /* EPP mode, reverse channel, addresses. */
parport_ieee1284_epp_read_addr(struct parport * port,void * buffer,size_t len,int flags)841*4882a593Smuzhiyun size_t parport_ieee1284_epp_read_addr (struct parport *port,
842*4882a593Smuzhiyun void *buffer, size_t len,
843*4882a593Smuzhiyun int flags)
844*4882a593Smuzhiyun {
845*4882a593Smuzhiyun unsigned char *bp = (unsigned char *) buffer;
846*4882a593Smuzhiyun unsigned ret = 0;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun /* Set EPP idle state (just to make sure) with strobe high */
849*4882a593Smuzhiyun parport_frob_control (port,
850*4882a593Smuzhiyun PARPORT_CONTROL_STROBE |
851*4882a593Smuzhiyun PARPORT_CONTROL_AUTOFD |
852*4882a593Smuzhiyun PARPORT_CONTROL_SELECT |
853*4882a593Smuzhiyun PARPORT_CONTROL_INIT,
854*4882a593Smuzhiyun PARPORT_CONTROL_INIT);
855*4882a593Smuzhiyun port->ops->data_reverse (port);
856*4882a593Smuzhiyun for (; len > 0; len--, bp++) {
857*4882a593Smuzhiyun /* Event 64: set nSelectIn (nAStrb) low */
858*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_SELECT,
859*4882a593Smuzhiyun PARPORT_CONTROL_SELECT);
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun /* Event 58: wait for Busy to go high */
862*4882a593Smuzhiyun if (parport_wait_peripheral (port, PARPORT_STATUS_BUSY, 0)) {
863*4882a593Smuzhiyun break;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun *bp = parport_read_data (port);
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun /* Event 59: set nSelectIn (nAStrb) high */
869*4882a593Smuzhiyun parport_frob_control (port, PARPORT_CONTROL_SELECT,
870*4882a593Smuzhiyun 0);
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /* Event 60: wait for Busy to go low */
873*4882a593Smuzhiyun if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY,
874*4882a593Smuzhiyun PARPORT_STATUS_BUSY, 5))
875*4882a593Smuzhiyun break;
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun ret++;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun port->ops->data_forward (port);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun return ret;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_ecp_write_data);
885*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_ecp_read_data);
886*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_ecp_write_addr);
887*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_write_compat);
888*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_read_nibble);
889*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_read_byte);
890*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_epp_write_data);
891*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_epp_read_data);
892*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_epp_write_addr);
893*4882a593Smuzhiyun EXPORT_SYMBOL(parport_ieee1284_epp_read_addr);
894