1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Allwinner sunXi SoCs Security ID support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013 Oliver Schinagl <oliver@schinagl.nl>
6*4882a593Smuzhiyun * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/iopoll.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/random.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Registers and special values for doing register-based SID readout on H3 */
21*4882a593Smuzhiyun #define SUN8I_SID_PRCTL 0x40
22*4882a593Smuzhiyun #define SUN8I_SID_RDKEY 0x60
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define SUN8I_SID_OFFSET_MASK 0x1FF
25*4882a593Smuzhiyun #define SUN8I_SID_OFFSET_SHIFT 16
26*4882a593Smuzhiyun #define SUN8I_SID_OP_LOCK (0xAC << 8)
27*4882a593Smuzhiyun #define SUN8I_SID_READ BIT(1)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct sunxi_sid_cfg {
30*4882a593Smuzhiyun u32 value_offset;
31*4882a593Smuzhiyun u32 size;
32*4882a593Smuzhiyun bool need_register_readout;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct sunxi_sid {
36*4882a593Smuzhiyun void __iomem *base;
37*4882a593Smuzhiyun u32 value_offset;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
sunxi_sid_read(void * context,unsigned int offset,void * val,size_t bytes)40*4882a593Smuzhiyun static int sunxi_sid_read(void *context, unsigned int offset,
41*4882a593Smuzhiyun void *val, size_t bytes)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct sunxi_sid *sid = context;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
sun8i_sid_register_readout(const struct sunxi_sid * sid,const unsigned int offset,u32 * out)50*4882a593Smuzhiyun static int sun8i_sid_register_readout(const struct sunxi_sid *sid,
51*4882a593Smuzhiyun const unsigned int offset,
52*4882a593Smuzhiyun u32 *out)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 reg_val;
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Set word, lock access, and set read command */
58*4882a593Smuzhiyun reg_val = (offset & SUN8I_SID_OFFSET_MASK)
59*4882a593Smuzhiyun << SUN8I_SID_OFFSET_SHIFT;
60*4882a593Smuzhiyun reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ;
61*4882a593Smuzhiyun writel(reg_val, sid->base + SUN8I_SID_PRCTL);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val,
64*4882a593Smuzhiyun !(reg_val & SUN8I_SID_READ), 100, 250000);
65*4882a593Smuzhiyun if (ret)
66*4882a593Smuzhiyun return ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (out)
69*4882a593Smuzhiyun *out = readl(sid->base + SUN8I_SID_RDKEY);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun writel(0, sid->base + SUN8I_SID_PRCTL);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * On Allwinner H3, the value on the 0x200 offset of the SID controller seems
78*4882a593Smuzhiyun * to be not reliable at all.
79*4882a593Smuzhiyun * Read by the registers instead.
80*4882a593Smuzhiyun */
sun8i_sid_read_by_reg(void * context,unsigned int offset,void * val,size_t bytes)81*4882a593Smuzhiyun static int sun8i_sid_read_by_reg(void *context, unsigned int offset,
82*4882a593Smuzhiyun void *val, size_t bytes)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct sunxi_sid *sid = context;
85*4882a593Smuzhiyun u32 word;
86*4882a593Smuzhiyun int ret;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* .stride = 4 so offset is guaranteed to be aligned */
89*4882a593Smuzhiyun while (bytes >= 4) {
90*4882a593Smuzhiyun ret = sun8i_sid_register_readout(sid, offset, val);
91*4882a593Smuzhiyun if (ret)
92*4882a593Smuzhiyun return ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun val += 4;
95*4882a593Smuzhiyun offset += 4;
96*4882a593Smuzhiyun bytes -= 4;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (!bytes)
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Handle any trailing bytes */
103*4882a593Smuzhiyun ret = sun8i_sid_register_readout(sid, offset, &word);
104*4882a593Smuzhiyun if (ret)
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun memcpy(val, &word, bytes);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
sunxi_sid_probe(struct platform_device * pdev)112*4882a593Smuzhiyun static int sunxi_sid_probe(struct platform_device *pdev)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun struct device *dev = &pdev->dev;
115*4882a593Smuzhiyun struct resource *res;
116*4882a593Smuzhiyun struct nvmem_config *nvmem_cfg;
117*4882a593Smuzhiyun struct nvmem_device *nvmem;
118*4882a593Smuzhiyun struct sunxi_sid *sid;
119*4882a593Smuzhiyun int size;
120*4882a593Smuzhiyun char *randomness;
121*4882a593Smuzhiyun const struct sunxi_sid_cfg *cfg;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun sid = devm_kzalloc(dev, sizeof(*sid), GFP_KERNEL);
124*4882a593Smuzhiyun if (!sid)
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun cfg = of_device_get_match_data(dev);
128*4882a593Smuzhiyun if (!cfg)
129*4882a593Smuzhiyun return -EINVAL;
130*4882a593Smuzhiyun sid->value_offset = cfg->value_offset;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133*4882a593Smuzhiyun sid->base = devm_ioremap_resource(dev, res);
134*4882a593Smuzhiyun if (IS_ERR(sid->base))
135*4882a593Smuzhiyun return PTR_ERR(sid->base);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun size = cfg->size;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun nvmem_cfg = devm_kzalloc(dev, sizeof(*nvmem_cfg), GFP_KERNEL);
140*4882a593Smuzhiyun if (!nvmem_cfg)
141*4882a593Smuzhiyun return -ENOMEM;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun nvmem_cfg->dev = dev;
144*4882a593Smuzhiyun nvmem_cfg->name = "sunxi-sid";
145*4882a593Smuzhiyun nvmem_cfg->read_only = true;
146*4882a593Smuzhiyun nvmem_cfg->size = cfg->size;
147*4882a593Smuzhiyun nvmem_cfg->word_size = 1;
148*4882a593Smuzhiyun nvmem_cfg->stride = 4;
149*4882a593Smuzhiyun nvmem_cfg->priv = sid;
150*4882a593Smuzhiyun if (cfg->need_register_readout)
151*4882a593Smuzhiyun nvmem_cfg->reg_read = sun8i_sid_read_by_reg;
152*4882a593Smuzhiyun else
153*4882a593Smuzhiyun nvmem_cfg->reg_read = sunxi_sid_read;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun nvmem = devm_nvmem_register(dev, nvmem_cfg);
156*4882a593Smuzhiyun if (IS_ERR(nvmem))
157*4882a593Smuzhiyun return PTR_ERR(nvmem);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun randomness = kzalloc(size, GFP_KERNEL);
160*4882a593Smuzhiyun if (!randomness)
161*4882a593Smuzhiyun return -ENOMEM;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun nvmem_cfg->reg_read(sid, 0, randomness, size);
164*4882a593Smuzhiyun add_device_randomness(randomness, size);
165*4882a593Smuzhiyun kfree(randomness);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun platform_set_drvdata(pdev, nvmem);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun static const struct sunxi_sid_cfg sun4i_a10_cfg = {
173*4882a593Smuzhiyun .size = 0x10,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static const struct sunxi_sid_cfg sun7i_a20_cfg = {
177*4882a593Smuzhiyun .size = 0x200,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static const struct sunxi_sid_cfg sun8i_h3_cfg = {
181*4882a593Smuzhiyun .value_offset = 0x200,
182*4882a593Smuzhiyun .size = 0x100,
183*4882a593Smuzhiyun .need_register_readout = true,
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static const struct sunxi_sid_cfg sun50i_a64_cfg = {
187*4882a593Smuzhiyun .value_offset = 0x200,
188*4882a593Smuzhiyun .size = 0x100,
189*4882a593Smuzhiyun .need_register_readout = true,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static const struct sunxi_sid_cfg sun50i_h6_cfg = {
193*4882a593Smuzhiyun .value_offset = 0x200,
194*4882a593Smuzhiyun .size = 0x200,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static const struct of_device_id sunxi_sid_of_match[] = {
198*4882a593Smuzhiyun { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
199*4882a593Smuzhiyun { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
200*4882a593Smuzhiyun { .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
201*4882a593Smuzhiyun { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
202*4882a593Smuzhiyun { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
203*4882a593Smuzhiyun { .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
204*4882a593Smuzhiyun { .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
205*4882a593Smuzhiyun {/* sentinel */},
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun static struct platform_driver sunxi_sid_driver = {
210*4882a593Smuzhiyun .probe = sunxi_sid_probe,
211*4882a593Smuzhiyun .driver = {
212*4882a593Smuzhiyun .name = "eeprom-sunxi-sid",
213*4882a593Smuzhiyun .of_match_table = sunxi_sid_of_match,
214*4882a593Smuzhiyun },
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun module_platform_driver(sunxi_sid_driver);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun MODULE_AUTHOR("Oliver Schinagl <oliver@schinagl.nl>");
219*4882a593Smuzhiyun MODULE_DESCRIPTION("Allwinner sunxi security id driver");
220*4882a593Smuzhiyun MODULE_LICENSE("GPL");
221