xref: /OK3568_Linux_fs/kernel/drivers/nvmem/sprd-efuse.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) 2019 Spreadtrum Communications Inc.
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/clk.h>
5*4882a593Smuzhiyun #include <linux/delay.h>
6*4882a593Smuzhiyun #include <linux/hwspinlock.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define SPRD_EFUSE_ENABLE		0x20
14*4882a593Smuzhiyun #define SPRD_EFUSE_ERR_FLAG		0x24
15*4882a593Smuzhiyun #define SPRD_EFUSE_ERR_CLR		0x28
16*4882a593Smuzhiyun #define SPRD_EFUSE_MAGIC_NUM		0x2c
17*4882a593Smuzhiyun #define SPRD_EFUSE_FW_CFG		0x50
18*4882a593Smuzhiyun #define SPRD_EFUSE_PW_SWT		0x54
19*4882a593Smuzhiyun #define SPRD_EFUSE_MEM(val)		(0x1000 + ((val) << 2))
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define SPRD_EFUSE_VDD_EN		BIT(0)
22*4882a593Smuzhiyun #define SPRD_EFUSE_AUTO_CHECK_EN	BIT(1)
23*4882a593Smuzhiyun #define SPRD_EFUSE_DOUBLE_EN		BIT(2)
24*4882a593Smuzhiyun #define SPRD_EFUSE_MARGIN_RD_EN		BIT(3)
25*4882a593Smuzhiyun #define SPRD_EFUSE_LOCK_WR_EN		BIT(4)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define SPRD_EFUSE_ERR_CLR_MASK		GENMASK(13, 0)
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define SPRD_EFUSE_ENK1_ON		BIT(0)
30*4882a593Smuzhiyun #define SPRD_EFUSE_ENK2_ON		BIT(1)
31*4882a593Smuzhiyun #define SPRD_EFUSE_PROG_EN		BIT(2)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define SPRD_EFUSE_MAGIC_NUMBER		0x8810
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* Block width (bytes) definitions */
36*4882a593Smuzhiyun #define SPRD_EFUSE_BLOCK_WIDTH		4
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun  * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40*4882a593Smuzhiyun  * and we can only access the normal efuse in kernel. So define the normal
41*4882a593Smuzhiyun  * block offset index and normal block numbers.
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun #define SPRD_EFUSE_NORMAL_BLOCK_NUMS	24
44*4882a593Smuzhiyun #define SPRD_EFUSE_NORMAL_BLOCK_OFFSET	72
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* Timeout (ms) for the trylock of hardware spinlocks */
47*4882a593Smuzhiyun #define SPRD_EFUSE_HWLOCK_TIMEOUT	5000
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun  * Since different Spreadtrum SoC chip can have different normal block numbers
51*4882a593Smuzhiyun  * and offset. And some SoC can support block double feature, which means
52*4882a593Smuzhiyun  * when reading or writing data to efuse memory, the controller can save double
53*4882a593Smuzhiyun  * data in case one data become incorrect after a long period.
54*4882a593Smuzhiyun  *
55*4882a593Smuzhiyun  * Thus we should save them in the device data structure.
56*4882a593Smuzhiyun  */
57*4882a593Smuzhiyun struct sprd_efuse_variant_data {
58*4882a593Smuzhiyun 	u32 blk_nums;
59*4882a593Smuzhiyun 	u32 blk_offset;
60*4882a593Smuzhiyun 	bool blk_double;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun struct sprd_efuse {
64*4882a593Smuzhiyun 	struct device *dev;
65*4882a593Smuzhiyun 	struct clk *clk;
66*4882a593Smuzhiyun 	struct hwspinlock *hwlock;
67*4882a593Smuzhiyun 	struct mutex mutex;
68*4882a593Smuzhiyun 	void __iomem *base;
69*4882a593Smuzhiyun 	const struct sprd_efuse_variant_data *data;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static const struct sprd_efuse_variant_data ums312_data = {
73*4882a593Smuzhiyun 	.blk_nums = SPRD_EFUSE_NORMAL_BLOCK_NUMS,
74*4882a593Smuzhiyun 	.blk_offset = SPRD_EFUSE_NORMAL_BLOCK_OFFSET,
75*4882a593Smuzhiyun 	.blk_double = false,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun  * On Spreadtrum platform, we have multi-subsystems will access the unique
80*4882a593Smuzhiyun  * efuse controller, so we need one hardware spinlock to synchronize between
81*4882a593Smuzhiyun  * the multiple subsystems.
82*4882a593Smuzhiyun  */
sprd_efuse_lock(struct sprd_efuse * efuse)83*4882a593Smuzhiyun static int sprd_efuse_lock(struct sprd_efuse *efuse)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	int ret;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	mutex_lock(&efuse->mutex);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	ret = hwspin_lock_timeout_raw(efuse->hwlock,
90*4882a593Smuzhiyun 				      SPRD_EFUSE_HWLOCK_TIMEOUT);
91*4882a593Smuzhiyun 	if (ret) {
92*4882a593Smuzhiyun 		dev_err(efuse->dev, "timeout get the hwspinlock\n");
93*4882a593Smuzhiyun 		mutex_unlock(&efuse->mutex);
94*4882a593Smuzhiyun 		return ret;
95*4882a593Smuzhiyun 	}
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
sprd_efuse_unlock(struct sprd_efuse * efuse)100*4882a593Smuzhiyun static void sprd_efuse_unlock(struct sprd_efuse *efuse)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	hwspin_unlock_raw(efuse->hwlock);
103*4882a593Smuzhiyun 	mutex_unlock(&efuse->mutex);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
sprd_efuse_set_prog_power(struct sprd_efuse * efuse,bool en)106*4882a593Smuzhiyun static void sprd_efuse_set_prog_power(struct sprd_efuse *efuse, bool en)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (en)
111*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_ENK2_ON;
112*4882a593Smuzhiyun 	else
113*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_ENK1_ON;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* Open or close efuse power need wait 1000us to make power stable. */
118*4882a593Smuzhiyun 	usleep_range(1000, 1200);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (en)
121*4882a593Smuzhiyun 		val |= SPRD_EFUSE_ENK1_ON;
122*4882a593Smuzhiyun 	else
123*4882a593Smuzhiyun 		val |= SPRD_EFUSE_ENK2_ON;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	/* Open or close efuse power need wait 1000us to make power stable. */
128*4882a593Smuzhiyun 	usleep_range(1000, 1200);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
sprd_efuse_set_read_power(struct sprd_efuse * efuse,bool en)131*4882a593Smuzhiyun static void sprd_efuse_set_read_power(struct sprd_efuse *efuse, bool en)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (en)
136*4882a593Smuzhiyun 		val |= SPRD_EFUSE_VDD_EN;
137*4882a593Smuzhiyun 	else
138*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_VDD_EN;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_ENABLE);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* Open or close efuse power need wait 1000us to make power stable. */
143*4882a593Smuzhiyun 	usleep_range(1000, 1200);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
sprd_efuse_set_prog_lock(struct sprd_efuse * efuse,bool en)146*4882a593Smuzhiyun static void sprd_efuse_set_prog_lock(struct sprd_efuse *efuse, bool en)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (en)
151*4882a593Smuzhiyun 		val |= SPRD_EFUSE_LOCK_WR_EN;
152*4882a593Smuzhiyun 	else
153*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_LOCK_WR_EN;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_ENABLE);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
sprd_efuse_set_auto_check(struct sprd_efuse * efuse,bool en)158*4882a593Smuzhiyun static void sprd_efuse_set_auto_check(struct sprd_efuse *efuse, bool en)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (en)
163*4882a593Smuzhiyun 		val |= SPRD_EFUSE_AUTO_CHECK_EN;
164*4882a593Smuzhiyun 	else
165*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_AUTO_CHECK_EN;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_ENABLE);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
sprd_efuse_set_data_double(struct sprd_efuse * efuse,bool en)170*4882a593Smuzhiyun static void sprd_efuse_set_data_double(struct sprd_efuse *efuse, bool en)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	if (en)
175*4882a593Smuzhiyun 		val |= SPRD_EFUSE_DOUBLE_EN;
176*4882a593Smuzhiyun 	else
177*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_DOUBLE_EN;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_ENABLE);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
sprd_efuse_set_prog_en(struct sprd_efuse * efuse,bool en)182*4882a593Smuzhiyun static void sprd_efuse_set_prog_en(struct sprd_efuse *efuse, bool en)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	if (en)
187*4882a593Smuzhiyun 		val |= SPRD_EFUSE_PROG_EN;
188*4882a593Smuzhiyun 	else
189*4882a593Smuzhiyun 		val &= ~SPRD_EFUSE_PROG_EN;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
sprd_efuse_raw_prog(struct sprd_efuse * efuse,u32 blk,bool doub,bool lock,u32 * data)194*4882a593Smuzhiyun static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub,
195*4882a593Smuzhiyun 			       bool lock, u32 *data)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	u32 status;
198*4882a593Smuzhiyun 	int ret = 0;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/*
201*4882a593Smuzhiyun 	 * We need set the correct magic number before writing the efuse to
202*4882a593Smuzhiyun 	 * allow programming, and block other programming until we clear the
203*4882a593Smuzhiyun 	 * magic number.
204*4882a593Smuzhiyun 	 */
205*4882a593Smuzhiyun 	writel(SPRD_EFUSE_MAGIC_NUMBER,
206*4882a593Smuzhiyun 	       efuse->base + SPRD_EFUSE_MAGIC_NUM);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	/*
209*4882a593Smuzhiyun 	 * Power on the efuse, enable programme and enable double data
210*4882a593Smuzhiyun 	 * if asked.
211*4882a593Smuzhiyun 	 */
212*4882a593Smuzhiyun 	sprd_efuse_set_prog_power(efuse, true);
213*4882a593Smuzhiyun 	sprd_efuse_set_prog_en(efuse, true);
214*4882a593Smuzhiyun 	sprd_efuse_set_data_double(efuse, doub);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/*
217*4882a593Smuzhiyun 	 * Enable the auto-check function to validate if the programming is
218*4882a593Smuzhiyun 	 * successful.
219*4882a593Smuzhiyun 	 */
220*4882a593Smuzhiyun 	if (lock)
221*4882a593Smuzhiyun 		sprd_efuse_set_auto_check(efuse, true);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	writel(*data, efuse->base + SPRD_EFUSE_MEM(blk));
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/* Disable auto-check and data double after programming */
226*4882a593Smuzhiyun 	if (lock)
227*4882a593Smuzhiyun 		sprd_efuse_set_auto_check(efuse, false);
228*4882a593Smuzhiyun 	sprd_efuse_set_data_double(efuse, false);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/*
231*4882a593Smuzhiyun 	 * Check the efuse error status, if the programming is successful,
232*4882a593Smuzhiyun 	 * we should lock this efuse block to avoid programming again.
233*4882a593Smuzhiyun 	 */
234*4882a593Smuzhiyun 	status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
235*4882a593Smuzhiyun 	if (status) {
236*4882a593Smuzhiyun 		dev_err(efuse->dev,
237*4882a593Smuzhiyun 			"write error status %d of block %d\n", ret, blk);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 		writel(SPRD_EFUSE_ERR_CLR_MASK,
240*4882a593Smuzhiyun 		       efuse->base + SPRD_EFUSE_ERR_CLR);
241*4882a593Smuzhiyun 		ret = -EBUSY;
242*4882a593Smuzhiyun 	} else if (lock) {
243*4882a593Smuzhiyun 		sprd_efuse_set_prog_lock(efuse, lock);
244*4882a593Smuzhiyun 		writel(0, efuse->base + SPRD_EFUSE_MEM(blk));
245*4882a593Smuzhiyun 		sprd_efuse_set_prog_lock(efuse, false);
246*4882a593Smuzhiyun 	}
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	sprd_efuse_set_prog_power(efuse, false);
249*4882a593Smuzhiyun 	writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	return ret;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
sprd_efuse_raw_read(struct sprd_efuse * efuse,int blk,u32 * val,bool doub)254*4882a593Smuzhiyun static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val,
255*4882a593Smuzhiyun 			       bool doub)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	u32 status;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/*
260*4882a593Smuzhiyun 	 * Need power on the efuse before reading data from efuse, and will
261*4882a593Smuzhiyun 	 * power off the efuse after reading process.
262*4882a593Smuzhiyun 	 */
263*4882a593Smuzhiyun 	sprd_efuse_set_read_power(efuse, true);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	/* Enable double data if asked */
266*4882a593Smuzhiyun 	sprd_efuse_set_data_double(efuse, doub);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/* Start to read data from efuse block */
269*4882a593Smuzhiyun 	*val = readl(efuse->base + SPRD_EFUSE_MEM(blk));
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Disable double data */
272*4882a593Smuzhiyun 	sprd_efuse_set_data_double(efuse, false);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/* Power off the efuse */
275*4882a593Smuzhiyun 	sprd_efuse_set_read_power(efuse, false);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	/*
278*4882a593Smuzhiyun 	 * Check the efuse error status and clear them if there are some
279*4882a593Smuzhiyun 	 * errors occurred.
280*4882a593Smuzhiyun 	 */
281*4882a593Smuzhiyun 	status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
282*4882a593Smuzhiyun 	if (status) {
283*4882a593Smuzhiyun 		dev_err(efuse->dev,
284*4882a593Smuzhiyun 			"read error status %d of block %d\n", status, blk);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		writel(SPRD_EFUSE_ERR_CLR_MASK,
287*4882a593Smuzhiyun 		       efuse->base + SPRD_EFUSE_ERR_CLR);
288*4882a593Smuzhiyun 		return -EBUSY;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return 0;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
sprd_efuse_read(void * context,u32 offset,void * val,size_t bytes)294*4882a593Smuzhiyun static int sprd_efuse_read(void *context, u32 offset, void *val, size_t bytes)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun 	struct sprd_efuse *efuse = context;
297*4882a593Smuzhiyun 	bool blk_double = efuse->data->blk_double;
298*4882a593Smuzhiyun 	u32 index = offset / SPRD_EFUSE_BLOCK_WIDTH + efuse->data->blk_offset;
299*4882a593Smuzhiyun 	u32 blk_offset = (offset % SPRD_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
300*4882a593Smuzhiyun 	u32 data;
301*4882a593Smuzhiyun 	int ret;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	ret = sprd_efuse_lock(efuse);
304*4882a593Smuzhiyun 	if (ret)
305*4882a593Smuzhiyun 		return ret;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	ret = clk_prepare_enable(efuse->clk);
308*4882a593Smuzhiyun 	if (ret)
309*4882a593Smuzhiyun 		goto unlock;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	ret = sprd_efuse_raw_read(efuse, index, &data, blk_double);
312*4882a593Smuzhiyun 	if (!ret) {
313*4882a593Smuzhiyun 		data >>= blk_offset;
314*4882a593Smuzhiyun 		memcpy(val, &data, bytes);
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	clk_disable_unprepare(efuse->clk);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun unlock:
320*4882a593Smuzhiyun 	sprd_efuse_unlock(efuse);
321*4882a593Smuzhiyun 	return ret;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
sprd_efuse_write(void * context,u32 offset,void * val,size_t bytes)324*4882a593Smuzhiyun static int sprd_efuse_write(void *context, u32 offset, void *val, size_t bytes)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct sprd_efuse *efuse = context;
327*4882a593Smuzhiyun 	bool blk_double = efuse->data->blk_double;
328*4882a593Smuzhiyun 	bool lock;
329*4882a593Smuzhiyun 	int ret;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	ret = sprd_efuse_lock(efuse);
332*4882a593Smuzhiyun 	if (ret)
333*4882a593Smuzhiyun 		return ret;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	ret = clk_prepare_enable(efuse->clk);
336*4882a593Smuzhiyun 	if (ret)
337*4882a593Smuzhiyun 		goto unlock;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	/*
340*4882a593Smuzhiyun 	 * If the writing bytes are equal with the block width, which means the
341*4882a593Smuzhiyun 	 * whole block will be programmed. For this case, we should not allow
342*4882a593Smuzhiyun 	 * this block to be programmed again by locking this block.
343*4882a593Smuzhiyun 	 *
344*4882a593Smuzhiyun 	 * If the block was programmed partially, we should allow this block to
345*4882a593Smuzhiyun 	 * be programmed again.
346*4882a593Smuzhiyun 	 */
347*4882a593Smuzhiyun 	if (bytes < SPRD_EFUSE_BLOCK_WIDTH)
348*4882a593Smuzhiyun 		lock = false;
349*4882a593Smuzhiyun 	else
350*4882a593Smuzhiyun 		lock = true;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	ret = sprd_efuse_raw_prog(efuse, offset, blk_double, lock, val);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	clk_disable_unprepare(efuse->clk);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun unlock:
357*4882a593Smuzhiyun 	sprd_efuse_unlock(efuse);
358*4882a593Smuzhiyun 	return ret;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
sprd_efuse_probe(struct platform_device * pdev)361*4882a593Smuzhiyun static int sprd_efuse_probe(struct platform_device *pdev)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
364*4882a593Smuzhiyun 	struct nvmem_device *nvmem;
365*4882a593Smuzhiyun 	struct nvmem_config econfig = { };
366*4882a593Smuzhiyun 	struct sprd_efuse *efuse;
367*4882a593Smuzhiyun 	const struct sprd_efuse_variant_data *pdata;
368*4882a593Smuzhiyun 	int ret;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	pdata = of_device_get_match_data(&pdev->dev);
371*4882a593Smuzhiyun 	if (!pdata) {
372*4882a593Smuzhiyun 		dev_err(&pdev->dev, "No matching driver data found\n");
373*4882a593Smuzhiyun 		return -EINVAL;
374*4882a593Smuzhiyun 	}
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
377*4882a593Smuzhiyun 	if (!efuse)
378*4882a593Smuzhiyun 		return -ENOMEM;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	efuse->base = devm_platform_ioremap_resource(pdev, 0);
381*4882a593Smuzhiyun 	if (IS_ERR(efuse->base))
382*4882a593Smuzhiyun 		return PTR_ERR(efuse->base);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	ret = of_hwspin_lock_get_id(np, 0);
385*4882a593Smuzhiyun 	if (ret < 0) {
386*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to get hwlock id\n");
387*4882a593Smuzhiyun 		return ret;
388*4882a593Smuzhiyun 	}
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
391*4882a593Smuzhiyun 	if (!efuse->hwlock) {
392*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to request hwlock\n");
393*4882a593Smuzhiyun 		return -ENXIO;
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	efuse->clk = devm_clk_get(&pdev->dev, "enable");
397*4882a593Smuzhiyun 	if (IS_ERR(efuse->clk)) {
398*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to get enable clock\n");
399*4882a593Smuzhiyun 		return PTR_ERR(efuse->clk);
400*4882a593Smuzhiyun 	}
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	mutex_init(&efuse->mutex);
403*4882a593Smuzhiyun 	efuse->dev = &pdev->dev;
404*4882a593Smuzhiyun 	efuse->data = pdata;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	econfig.stride = 1;
407*4882a593Smuzhiyun 	econfig.word_size = 1;
408*4882a593Smuzhiyun 	econfig.read_only = false;
409*4882a593Smuzhiyun 	econfig.name = "sprd-efuse";
410*4882a593Smuzhiyun 	econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
411*4882a593Smuzhiyun 	econfig.reg_read = sprd_efuse_read;
412*4882a593Smuzhiyun 	econfig.reg_write = sprd_efuse_write;
413*4882a593Smuzhiyun 	econfig.priv = efuse;
414*4882a593Smuzhiyun 	econfig.dev = &pdev->dev;
415*4882a593Smuzhiyun 	nvmem = devm_nvmem_register(&pdev->dev, &econfig);
416*4882a593Smuzhiyun 	if (IS_ERR(nvmem)) {
417*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register nvmem\n");
418*4882a593Smuzhiyun 		return PTR_ERR(nvmem);
419*4882a593Smuzhiyun 	}
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	return 0;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun static const struct of_device_id sprd_efuse_of_match[] = {
425*4882a593Smuzhiyun 	{ .compatible = "sprd,ums312-efuse", .data = &ums312_data },
426*4882a593Smuzhiyun 	{ }
427*4882a593Smuzhiyun };
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun static struct platform_driver sprd_efuse_driver = {
430*4882a593Smuzhiyun 	.probe = sprd_efuse_probe,
431*4882a593Smuzhiyun 	.driver = {
432*4882a593Smuzhiyun 		.name = "sprd-efuse",
433*4882a593Smuzhiyun 		.of_match_table = sprd_efuse_of_match,
434*4882a593Smuzhiyun 	},
435*4882a593Smuzhiyun };
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun module_platform_driver(sprd_efuse_driver);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
440*4882a593Smuzhiyun MODULE_DESCRIPTION("Spreadtrum AP efuse driver");
441*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
442