1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
4*4882a593Smuzhiyun * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define IMX6Q_SNVS_HPLR 0x00
14*4882a593Smuzhiyun #define IMX6Q_SNVS_LPLR 0x34
15*4882a593Smuzhiyun #define IMX6Q_SNVS_LPGPR 0x68
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define IMX7D_SNVS_HPLR 0x00
18*4882a593Smuzhiyun #define IMX7D_SNVS_LPLR 0x34
19*4882a593Smuzhiyun #define IMX7D_SNVS_LPGPR 0x90
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define IMX_GPR_SL BIT(5)
22*4882a593Smuzhiyun #define IMX_GPR_HL BIT(5)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct snvs_lpgpr_cfg {
25*4882a593Smuzhiyun int offset;
26*4882a593Smuzhiyun int offset_hplr;
27*4882a593Smuzhiyun int offset_lplr;
28*4882a593Smuzhiyun int size;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct snvs_lpgpr_priv {
32*4882a593Smuzhiyun struct device_d *dev;
33*4882a593Smuzhiyun struct regmap *regmap;
34*4882a593Smuzhiyun struct nvmem_config cfg;
35*4882a593Smuzhiyun const struct snvs_lpgpr_cfg *dcfg;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
39*4882a593Smuzhiyun .offset = IMX6Q_SNVS_LPGPR,
40*4882a593Smuzhiyun .offset_hplr = IMX6Q_SNVS_HPLR,
41*4882a593Smuzhiyun .offset_lplr = IMX6Q_SNVS_LPLR,
42*4882a593Smuzhiyun .size = 4,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = {
46*4882a593Smuzhiyun .offset = IMX7D_SNVS_LPGPR,
47*4882a593Smuzhiyun .offset_hplr = IMX7D_SNVS_HPLR,
48*4882a593Smuzhiyun .offset_lplr = IMX7D_SNVS_LPLR,
49*4882a593Smuzhiyun .size = 16,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
snvs_lpgpr_write(void * context,unsigned int offset,void * val,size_t bytes)52*4882a593Smuzhiyun static int snvs_lpgpr_write(void *context, unsigned int offset, void *val,
53*4882a593Smuzhiyun size_t bytes)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct snvs_lpgpr_priv *priv = context;
56*4882a593Smuzhiyun const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
57*4882a593Smuzhiyun unsigned int lock_reg;
58*4882a593Smuzhiyun int ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg);
61*4882a593Smuzhiyun if (ret < 0)
62*4882a593Smuzhiyun return ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (lock_reg & IMX_GPR_SL)
65*4882a593Smuzhiyun return -EPERM;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg);
68*4882a593Smuzhiyun if (ret < 0)
69*4882a593Smuzhiyun return ret;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (lock_reg & IMX_GPR_HL)
72*4882a593Smuzhiyun return -EPERM;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val,
75*4882a593Smuzhiyun bytes / 4);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
snvs_lpgpr_read(void * context,unsigned int offset,void * val,size_t bytes)78*4882a593Smuzhiyun static int snvs_lpgpr_read(void *context, unsigned int offset, void *val,
79*4882a593Smuzhiyun size_t bytes)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct snvs_lpgpr_priv *priv = context;
82*4882a593Smuzhiyun const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return regmap_bulk_read(priv->regmap, dcfg->offset + offset,
85*4882a593Smuzhiyun val, bytes / 4);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
snvs_lpgpr_probe(struct platform_device * pdev)88*4882a593Smuzhiyun static int snvs_lpgpr_probe(struct platform_device *pdev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct device *dev = &pdev->dev;
91*4882a593Smuzhiyun struct device_node *node = dev->of_node;
92*4882a593Smuzhiyun struct device_node *syscon_node;
93*4882a593Smuzhiyun struct snvs_lpgpr_priv *priv;
94*4882a593Smuzhiyun struct nvmem_config *cfg;
95*4882a593Smuzhiyun struct nvmem_device *nvmem;
96*4882a593Smuzhiyun const struct snvs_lpgpr_cfg *dcfg;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (!node)
99*4882a593Smuzhiyun return -ENOENT;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
102*4882a593Smuzhiyun if (!priv)
103*4882a593Smuzhiyun return -ENOMEM;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun dcfg = of_device_get_match_data(dev);
106*4882a593Smuzhiyun if (!dcfg)
107*4882a593Smuzhiyun return -EINVAL;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun syscon_node = of_get_parent(node);
110*4882a593Smuzhiyun if (!syscon_node)
111*4882a593Smuzhiyun return -ENODEV;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun priv->regmap = syscon_node_to_regmap(syscon_node);
114*4882a593Smuzhiyun of_node_put(syscon_node);
115*4882a593Smuzhiyun if (IS_ERR(priv->regmap))
116*4882a593Smuzhiyun return PTR_ERR(priv->regmap);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun priv->dcfg = dcfg;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun cfg = &priv->cfg;
121*4882a593Smuzhiyun cfg->priv = priv;
122*4882a593Smuzhiyun cfg->name = dev_name(dev);
123*4882a593Smuzhiyun cfg->dev = dev;
124*4882a593Smuzhiyun cfg->stride = 4;
125*4882a593Smuzhiyun cfg->word_size = 4;
126*4882a593Smuzhiyun cfg->size = dcfg->size,
127*4882a593Smuzhiyun cfg->owner = THIS_MODULE;
128*4882a593Smuzhiyun cfg->reg_read = snvs_lpgpr_read;
129*4882a593Smuzhiyun cfg->reg_write = snvs_lpgpr_write;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun nvmem = devm_nvmem_register(dev, cfg);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(nvmem);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun static const struct of_device_id snvs_lpgpr_dt_ids[] = {
137*4882a593Smuzhiyun { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
138*4882a593Smuzhiyun { .compatible = "fsl,imx6ul-snvs-lpgpr",
139*4882a593Smuzhiyun .data = &snvs_lpgpr_cfg_imx6q },
140*4882a593Smuzhiyun { .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d },
141*4882a593Smuzhiyun { },
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static struct platform_driver snvs_lpgpr_driver = {
146*4882a593Smuzhiyun .probe = snvs_lpgpr_probe,
147*4882a593Smuzhiyun .driver = {
148*4882a593Smuzhiyun .name = "snvs_lpgpr",
149*4882a593Smuzhiyun .of_match_table = snvs_lpgpr_dt_ids,
150*4882a593Smuzhiyun },
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun module_platform_driver(snvs_lpgpr_driver);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
155*4882a593Smuzhiyun MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Storage");
156*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
157