1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun /*
4*4882a593Smuzhiyun * EEPROM driver for RAVE SP
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2018 Zodiac Inflight Innovations
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mfd/rave-sp.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/sizes.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /**
18*4882a593Smuzhiyun * enum rave_sp_eeprom_access_type - Supported types of EEPROM access
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * @RAVE_SP_EEPROM_WRITE: EEPROM write
21*4882a593Smuzhiyun * @RAVE_SP_EEPROM_READ: EEPROM read
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun enum rave_sp_eeprom_access_type {
24*4882a593Smuzhiyun RAVE_SP_EEPROM_WRITE = 0,
25*4882a593Smuzhiyun RAVE_SP_EEPROM_READ = 1,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun * enum rave_sp_eeprom_header_size - EEPROM command header sizes
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * @RAVE_SP_EEPROM_HEADER_SMALL: EEPROM header size for "small" devices (< 8K)
32*4882a593Smuzhiyun * @RAVE_SP_EEPROM_HEADER_BIG: EEPROM header size for "big" devices (> 8K)
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun enum rave_sp_eeprom_header_size {
35*4882a593Smuzhiyun RAVE_SP_EEPROM_HEADER_SMALL = 4U,
36*4882a593Smuzhiyun RAVE_SP_EEPROM_HEADER_BIG = 5U,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun #define RAVE_SP_EEPROM_HEADER_MAX RAVE_SP_EEPROM_HEADER_BIG
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define RAVE_SP_EEPROM_PAGE_SIZE 32U
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /**
43*4882a593Smuzhiyun * struct rave_sp_eeprom_page - RAVE SP EEPROM page
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * @type: Access type (see enum rave_sp_eeprom_access_type)
46*4882a593Smuzhiyun * @success: Success flag (Success = 1, Failure = 0)
47*4882a593Smuzhiyun * @data: Read data
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun * Note this structure corresponds to RSP_*_EEPROM payload from RAVE
50*4882a593Smuzhiyun * SP ICD
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun struct rave_sp_eeprom_page {
53*4882a593Smuzhiyun u8 type;
54*4882a593Smuzhiyun u8 success;
55*4882a593Smuzhiyun u8 data[RAVE_SP_EEPROM_PAGE_SIZE];
56*4882a593Smuzhiyun } __packed;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /**
59*4882a593Smuzhiyun * struct rave_sp_eeprom - RAVE SP EEPROM device
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * @sp: Pointer to parent RAVE SP device
62*4882a593Smuzhiyun * @mutex: Lock protecting access to EEPROM
63*4882a593Smuzhiyun * @address: EEPROM device address
64*4882a593Smuzhiyun * @header_size: Size of EEPROM command header for this device
65*4882a593Smuzhiyun * @dev: Pointer to corresponding struct device used for logging
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun struct rave_sp_eeprom {
68*4882a593Smuzhiyun struct rave_sp *sp;
69*4882a593Smuzhiyun struct mutex mutex;
70*4882a593Smuzhiyun u8 address;
71*4882a593Smuzhiyun unsigned int header_size;
72*4882a593Smuzhiyun struct device *dev;
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /**
76*4882a593Smuzhiyun * rave_sp_eeprom_io - Low-level part of EEPROM page access
77*4882a593Smuzhiyun *
78*4882a593Smuzhiyun * @eeprom: EEPROM device to write to
79*4882a593Smuzhiyun * @type: EEPROM access type (read or write)
80*4882a593Smuzhiyun * @idx: number of the EEPROM page
81*4882a593Smuzhiyun * @page: Data to write or buffer to store result (via page->data)
82*4882a593Smuzhiyun *
83*4882a593Smuzhiyun * This function does all of the low-level work required to perform a
84*4882a593Smuzhiyun * EEPROM access. This includes formatting correct command payload,
85*4882a593Smuzhiyun * sending it and checking received results.
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * Returns zero in case of success or negative error code in
88*4882a593Smuzhiyun * case of failure.
89*4882a593Smuzhiyun */
rave_sp_eeprom_io(struct rave_sp_eeprom * eeprom,enum rave_sp_eeprom_access_type type,u16 idx,struct rave_sp_eeprom_page * page)90*4882a593Smuzhiyun static int rave_sp_eeprom_io(struct rave_sp_eeprom *eeprom,
91*4882a593Smuzhiyun enum rave_sp_eeprom_access_type type,
92*4882a593Smuzhiyun u16 idx,
93*4882a593Smuzhiyun struct rave_sp_eeprom_page *page)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun const bool is_write = type == RAVE_SP_EEPROM_WRITE;
96*4882a593Smuzhiyun const unsigned int data_size = is_write ? sizeof(page->data) : 0;
97*4882a593Smuzhiyun const unsigned int cmd_size = eeprom->header_size + data_size;
98*4882a593Smuzhiyun const unsigned int rsp_size =
99*4882a593Smuzhiyun is_write ? sizeof(*page) - sizeof(page->data) : sizeof(*page);
100*4882a593Smuzhiyun unsigned int offset = 0;
101*4882a593Smuzhiyun u8 cmd[RAVE_SP_EEPROM_HEADER_MAX + sizeof(page->data)];
102*4882a593Smuzhiyun int ret;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (WARN_ON(cmd_size > sizeof(cmd)))
105*4882a593Smuzhiyun return -EINVAL;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun cmd[offset++] = eeprom->address;
108*4882a593Smuzhiyun cmd[offset++] = 0;
109*4882a593Smuzhiyun cmd[offset++] = type;
110*4882a593Smuzhiyun cmd[offset++] = idx;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * If there's still room in this command's header it means we
114*4882a593Smuzhiyun * are talkin to EEPROM that uses 16-bit page numbers and we
115*4882a593Smuzhiyun * have to specify index's MSB in payload as well.
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun if (offset < eeprom->header_size)
118*4882a593Smuzhiyun cmd[offset++] = idx >> 8;
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun * Copy our data to write to command buffer first. In case of
121*4882a593Smuzhiyun * a read data_size should be zero and memcpy would become a
122*4882a593Smuzhiyun * no-op
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun memcpy(&cmd[offset], page->data, data_size);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun ret = rave_sp_exec(eeprom->sp, cmd, cmd_size, page, rsp_size);
127*4882a593Smuzhiyun if (ret)
128*4882a593Smuzhiyun return ret;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (page->type != type)
131*4882a593Smuzhiyun return -EPROTO;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (!page->success)
134*4882a593Smuzhiyun return -EIO;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /**
140*4882a593Smuzhiyun * rave_sp_eeprom_page_access - Access single EEPROM page
141*4882a593Smuzhiyun *
142*4882a593Smuzhiyun * @eeprom: EEPROM device to access
143*4882a593Smuzhiyun * @type: Access type to perform (read or write)
144*4882a593Smuzhiyun * @offset: Offset within EEPROM to access
145*4882a593Smuzhiyun * @data: Data buffer
146*4882a593Smuzhiyun * @data_len: Size of the data buffer
147*4882a593Smuzhiyun *
148*4882a593Smuzhiyun * This function performs a generic access to a single page or a
149*4882a593Smuzhiyun * portion thereof. Requested access MUST NOT cross the EEPROM page
150*4882a593Smuzhiyun * boundary.
151*4882a593Smuzhiyun *
152*4882a593Smuzhiyun * Returns zero in case of success or negative error code in
153*4882a593Smuzhiyun * case of failure.
154*4882a593Smuzhiyun */
155*4882a593Smuzhiyun static int
rave_sp_eeprom_page_access(struct rave_sp_eeprom * eeprom,enum rave_sp_eeprom_access_type type,unsigned int offset,u8 * data,size_t data_len)156*4882a593Smuzhiyun rave_sp_eeprom_page_access(struct rave_sp_eeprom *eeprom,
157*4882a593Smuzhiyun enum rave_sp_eeprom_access_type type,
158*4882a593Smuzhiyun unsigned int offset, u8 *data,
159*4882a593Smuzhiyun size_t data_len)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun const unsigned int page_offset = offset % RAVE_SP_EEPROM_PAGE_SIZE;
162*4882a593Smuzhiyun const unsigned int page_nr = offset / RAVE_SP_EEPROM_PAGE_SIZE;
163*4882a593Smuzhiyun struct rave_sp_eeprom_page page;
164*4882a593Smuzhiyun int ret;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun * This function will not work if data access we've been asked
168*4882a593Smuzhiyun * to do is crossing EEPROM page boundary. Normally this
169*4882a593Smuzhiyun * should never happen and getting here would indicate a bug
170*4882a593Smuzhiyun * in the code.
171*4882a593Smuzhiyun */
172*4882a593Smuzhiyun if (WARN_ON(data_len > sizeof(page.data) - page_offset))
173*4882a593Smuzhiyun return -EINVAL;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (type == RAVE_SP_EEPROM_WRITE) {
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun * If doing a partial write we need to do a read first
178*4882a593Smuzhiyun * to fill the rest of the page with correct data.
179*4882a593Smuzhiyun */
180*4882a593Smuzhiyun if (data_len < RAVE_SP_EEPROM_PAGE_SIZE) {
181*4882a593Smuzhiyun ret = rave_sp_eeprom_io(eeprom, RAVE_SP_EEPROM_READ,
182*4882a593Smuzhiyun page_nr, &page);
183*4882a593Smuzhiyun if (ret)
184*4882a593Smuzhiyun return ret;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun memcpy(&page.data[page_offset], data, data_len);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = rave_sp_eeprom_io(eeprom, type, page_nr, &page);
191*4882a593Smuzhiyun if (ret)
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /*
195*4882a593Smuzhiyun * Since we receive the result of the read via 'page.data'
196*4882a593Smuzhiyun * buffer we need to copy that to 'data'
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun if (type == RAVE_SP_EEPROM_READ)
199*4882a593Smuzhiyun memcpy(data, &page.data[page_offset], data_len);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /**
205*4882a593Smuzhiyun * rave_sp_eeprom_access - Access EEPROM data
206*4882a593Smuzhiyun *
207*4882a593Smuzhiyun * @eeprom: EEPROM device to access
208*4882a593Smuzhiyun * @type: Access type to perform (read or write)
209*4882a593Smuzhiyun * @offset: Offset within EEPROM to access
210*4882a593Smuzhiyun * @data: Data buffer
211*4882a593Smuzhiyun * @data_len: Size of the data buffer
212*4882a593Smuzhiyun *
213*4882a593Smuzhiyun * This function performs a generic access (either read or write) at
214*4882a593Smuzhiyun * arbitrary offset (not necessary page aligned) of arbitrary length
215*4882a593Smuzhiyun * (is not constrained by EEPROM page size).
216*4882a593Smuzhiyun *
217*4882a593Smuzhiyun * Returns zero in case of success or negative error code in case of
218*4882a593Smuzhiyun * failure.
219*4882a593Smuzhiyun */
rave_sp_eeprom_access(struct rave_sp_eeprom * eeprom,enum rave_sp_eeprom_access_type type,unsigned int offset,u8 * data,unsigned int data_len)220*4882a593Smuzhiyun static int rave_sp_eeprom_access(struct rave_sp_eeprom *eeprom,
221*4882a593Smuzhiyun enum rave_sp_eeprom_access_type type,
222*4882a593Smuzhiyun unsigned int offset, u8 *data,
223*4882a593Smuzhiyun unsigned int data_len)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun unsigned int residue;
226*4882a593Smuzhiyun unsigned int chunk;
227*4882a593Smuzhiyun unsigned int head;
228*4882a593Smuzhiyun int ret;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun mutex_lock(&eeprom->mutex);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun head = offset % RAVE_SP_EEPROM_PAGE_SIZE;
233*4882a593Smuzhiyun residue = data_len;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun do {
236*4882a593Smuzhiyun /*
237*4882a593Smuzhiyun * First iteration, if we are doing an access that is
238*4882a593Smuzhiyun * not 32-byte aligned, we need to access only data up
239*4882a593Smuzhiyun * to a page boundary to avoid corssing it in
240*4882a593Smuzhiyun * rave_sp_eeprom_page_access()
241*4882a593Smuzhiyun */
242*4882a593Smuzhiyun if (unlikely(head)) {
243*4882a593Smuzhiyun chunk = RAVE_SP_EEPROM_PAGE_SIZE - head;
244*4882a593Smuzhiyun /*
245*4882a593Smuzhiyun * This can only happen once per
246*4882a593Smuzhiyun * rave_sp_eeprom_access() call, so we set
247*4882a593Smuzhiyun * head to zero to process all the other
248*4882a593Smuzhiyun * iterations normally.
249*4882a593Smuzhiyun */
250*4882a593Smuzhiyun head = 0;
251*4882a593Smuzhiyun } else {
252*4882a593Smuzhiyun chunk = RAVE_SP_EEPROM_PAGE_SIZE;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * We should never read more that 'residue' bytes
257*4882a593Smuzhiyun */
258*4882a593Smuzhiyun chunk = min(chunk, residue);
259*4882a593Smuzhiyun ret = rave_sp_eeprom_page_access(eeprom, type, offset,
260*4882a593Smuzhiyun data, chunk);
261*4882a593Smuzhiyun if (ret)
262*4882a593Smuzhiyun goto out;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun residue -= chunk;
265*4882a593Smuzhiyun offset += chunk;
266*4882a593Smuzhiyun data += chunk;
267*4882a593Smuzhiyun } while (residue);
268*4882a593Smuzhiyun out:
269*4882a593Smuzhiyun mutex_unlock(&eeprom->mutex);
270*4882a593Smuzhiyun return ret;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
rave_sp_eeprom_reg_read(void * eeprom,unsigned int offset,void * val,size_t bytes)273*4882a593Smuzhiyun static int rave_sp_eeprom_reg_read(void *eeprom, unsigned int offset,
274*4882a593Smuzhiyun void *val, size_t bytes)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun return rave_sp_eeprom_access(eeprom, RAVE_SP_EEPROM_READ,
277*4882a593Smuzhiyun offset, val, bytes);
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
rave_sp_eeprom_reg_write(void * eeprom,unsigned int offset,void * val,size_t bytes)280*4882a593Smuzhiyun static int rave_sp_eeprom_reg_write(void *eeprom, unsigned int offset,
281*4882a593Smuzhiyun void *val, size_t bytes)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun return rave_sp_eeprom_access(eeprom, RAVE_SP_EEPROM_WRITE,
284*4882a593Smuzhiyun offset, val, bytes);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
rave_sp_eeprom_probe(struct platform_device * pdev)287*4882a593Smuzhiyun static int rave_sp_eeprom_probe(struct platform_device *pdev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun struct device *dev = &pdev->dev;
290*4882a593Smuzhiyun struct rave_sp *sp = dev_get_drvdata(dev->parent);
291*4882a593Smuzhiyun struct device_node *np = dev->of_node;
292*4882a593Smuzhiyun struct nvmem_config config = { 0 };
293*4882a593Smuzhiyun struct rave_sp_eeprom *eeprom;
294*4882a593Smuzhiyun struct nvmem_device *nvmem;
295*4882a593Smuzhiyun u32 reg[2], size;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg))) {
298*4882a593Smuzhiyun dev_err(dev, "Failed to parse \"reg\" property\n");
299*4882a593Smuzhiyun return -EINVAL;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun size = reg[1];
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun * Per ICD, we have no more than 2 bytes to specify EEPROM
305*4882a593Smuzhiyun * page.
306*4882a593Smuzhiyun */
307*4882a593Smuzhiyun if (size > U16_MAX * RAVE_SP_EEPROM_PAGE_SIZE) {
308*4882a593Smuzhiyun dev_err(dev, "Specified size is too big\n");
309*4882a593Smuzhiyun return -EINVAL;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
313*4882a593Smuzhiyun if (!eeprom)
314*4882a593Smuzhiyun return -ENOMEM;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun eeprom->address = reg[0];
317*4882a593Smuzhiyun eeprom->sp = sp;
318*4882a593Smuzhiyun eeprom->dev = dev;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (size > SZ_8K)
321*4882a593Smuzhiyun eeprom->header_size = RAVE_SP_EEPROM_HEADER_BIG;
322*4882a593Smuzhiyun else
323*4882a593Smuzhiyun eeprom->header_size = RAVE_SP_EEPROM_HEADER_SMALL;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun mutex_init(&eeprom->mutex);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun config.id = -1;
328*4882a593Smuzhiyun of_property_read_string(np, "zii,eeprom-name", &config.name);
329*4882a593Smuzhiyun config.priv = eeprom;
330*4882a593Smuzhiyun config.dev = dev;
331*4882a593Smuzhiyun config.size = size;
332*4882a593Smuzhiyun config.reg_read = rave_sp_eeprom_reg_read;
333*4882a593Smuzhiyun config.reg_write = rave_sp_eeprom_reg_write;
334*4882a593Smuzhiyun config.word_size = 1;
335*4882a593Smuzhiyun config.stride = 1;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun nvmem = devm_nvmem_register(dev, &config);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(nvmem);
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun static const struct of_device_id rave_sp_eeprom_of_match[] = {
343*4882a593Smuzhiyun { .compatible = "zii,rave-sp-eeprom" },
344*4882a593Smuzhiyun {}
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rave_sp_eeprom_of_match);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun static struct platform_driver rave_sp_eeprom_driver = {
349*4882a593Smuzhiyun .probe = rave_sp_eeprom_probe,
350*4882a593Smuzhiyun .driver = {
351*4882a593Smuzhiyun .name = KBUILD_MODNAME,
352*4882a593Smuzhiyun .of_match_table = rave_sp_eeprom_of_match,
353*4882a593Smuzhiyun },
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun module_platform_driver(rave_sp_eeprom_driver);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun MODULE_LICENSE("GPL");
358*4882a593Smuzhiyun MODULE_AUTHOR("Andrey Vostrikov <andrey.vostrikov@cogentembedded.com>");
359*4882a593Smuzhiyun MODULE_AUTHOR("Nikita Yushchenko <nikita.yoush@cogentembedded.com>");
360*4882a593Smuzhiyun MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>");
361*4882a593Smuzhiyun MODULE_DESCRIPTION("RAVE SP EEPROM driver");
362