1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017, 2020-2021, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/device.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_platform.h>
10*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SDAM_MEM_START 0x40
14*4882a593Smuzhiyun #define REGISTER_MAP_ID 0x40
15*4882a593Smuzhiyun #define REGISTER_MAP_VERSION 0x41
16*4882a593Smuzhiyun #define SDAM_SIZE 0x44
17*4882a593Smuzhiyun #define SDAM_PBS_TRIG_SET 0xE5
18*4882a593Smuzhiyun #define SDAM_PBS_TRIG_CLR 0xE6
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct sdam_chip {
21*4882a593Smuzhiyun struct regmap *regmap;
22*4882a593Smuzhiyun struct nvmem_config sdam_config;
23*4882a593Smuzhiyun unsigned int base;
24*4882a593Smuzhiyun unsigned int size;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* read only register offsets */
28*4882a593Smuzhiyun static const u8 sdam_ro_map[] = {
29*4882a593Smuzhiyun REGISTER_MAP_ID,
30*4882a593Smuzhiyun REGISTER_MAP_VERSION,
31*4882a593Smuzhiyun SDAM_SIZE
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
sdam_is_valid(struct sdam_chip * sdam,unsigned int offset,size_t len)34*4882a593Smuzhiyun static bool sdam_is_valid(struct sdam_chip *sdam, unsigned int offset,
35*4882a593Smuzhiyun size_t len)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun unsigned int sdam_mem_end = SDAM_MEM_START + sdam->size - 1;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (!len)
40*4882a593Smuzhiyun return false;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (offset >= SDAM_MEM_START && offset <= sdam_mem_end
43*4882a593Smuzhiyun && (offset + len - 1) <= sdam_mem_end)
44*4882a593Smuzhiyun return true;
45*4882a593Smuzhiyun else if ((offset == SDAM_PBS_TRIG_SET || offset == SDAM_PBS_TRIG_CLR)
46*4882a593Smuzhiyun && (len == 1))
47*4882a593Smuzhiyun return true;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return false;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
sdam_is_ro(unsigned int offset,size_t len)52*4882a593Smuzhiyun static bool sdam_is_ro(unsigned int offset, size_t len)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun int i;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sdam_ro_map); i++)
57*4882a593Smuzhiyun if (offset <= sdam_ro_map[i] && (offset + len) > sdam_ro_map[i])
58*4882a593Smuzhiyun return true;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return false;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
sdam_read(void * priv,unsigned int offset,void * val,size_t bytes)63*4882a593Smuzhiyun static int sdam_read(void *priv, unsigned int offset, void *val,
64*4882a593Smuzhiyun size_t bytes)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct sdam_chip *sdam = priv;
67*4882a593Smuzhiyun struct device *dev = sdam->sdam_config.dev;
68*4882a593Smuzhiyun int rc;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (!sdam_is_valid(sdam, offset, bytes)) {
71*4882a593Smuzhiyun dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
72*4882a593Smuzhiyun offset, bytes);
73*4882a593Smuzhiyun return -EINVAL;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun rc = regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes);
77*4882a593Smuzhiyun if (rc < 0)
78*4882a593Smuzhiyun dev_err(dev, "Failed to read SDAM offset %#x len=%zd, rc=%d\n",
79*4882a593Smuzhiyun offset, bytes, rc);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return rc;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
sdam_write(void * priv,unsigned int offset,void * val,size_t bytes)84*4882a593Smuzhiyun static int sdam_write(void *priv, unsigned int offset, void *val,
85*4882a593Smuzhiyun size_t bytes)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct sdam_chip *sdam = priv;
88*4882a593Smuzhiyun struct device *dev = sdam->sdam_config.dev;
89*4882a593Smuzhiyun int rc;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (!sdam_is_valid(sdam, offset, bytes)) {
92*4882a593Smuzhiyun dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
93*4882a593Smuzhiyun offset, bytes);
94*4882a593Smuzhiyun return -EINVAL;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (sdam_is_ro(offset, bytes)) {
98*4882a593Smuzhiyun dev_err(dev, "Invalid write offset %#x len=%zd\n",
99*4882a593Smuzhiyun offset, bytes);
100*4882a593Smuzhiyun return -EINVAL;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun rc = regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes);
104*4882a593Smuzhiyun if (rc < 0)
105*4882a593Smuzhiyun dev_err(dev, "Failed to write SDAM offset %#x len=%zd, rc=%d\n",
106*4882a593Smuzhiyun offset, bytes, rc);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return rc;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
sdam_probe(struct platform_device * pdev)111*4882a593Smuzhiyun static int sdam_probe(struct platform_device *pdev)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct sdam_chip *sdam;
114*4882a593Smuzhiyun struct nvmem_device *nvmem;
115*4882a593Smuzhiyun unsigned int val;
116*4882a593Smuzhiyun int rc;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun sdam = devm_kzalloc(&pdev->dev, sizeof(*sdam), GFP_KERNEL);
119*4882a593Smuzhiyun if (!sdam)
120*4882a593Smuzhiyun return -ENOMEM;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun sdam->regmap = dev_get_regmap(pdev->dev.parent, NULL);
123*4882a593Smuzhiyun if (!sdam->regmap) {
124*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get regmap handle\n");
125*4882a593Smuzhiyun return -ENXIO;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun rc = of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base);
129*4882a593Smuzhiyun if (rc < 0) {
130*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get SDAM base, rc=%d\n", rc);
131*4882a593Smuzhiyun return -EINVAL;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun rc = regmap_read(sdam->regmap, sdam->base + SDAM_SIZE, &val);
135*4882a593Smuzhiyun if (rc < 0) {
136*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to read SDAM_SIZE rc=%d\n", rc);
137*4882a593Smuzhiyun return -EINVAL;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun sdam->size = val * 32;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun sdam->sdam_config.dev = &pdev->dev;
142*4882a593Smuzhiyun sdam->sdam_config.name = "spmi_sdam";
143*4882a593Smuzhiyun sdam->sdam_config.id = NVMEM_DEVID_AUTO;
144*4882a593Smuzhiyun sdam->sdam_config.owner = THIS_MODULE,
145*4882a593Smuzhiyun sdam->sdam_config.stride = 1;
146*4882a593Smuzhiyun sdam->sdam_config.word_size = 1;
147*4882a593Smuzhiyun sdam->sdam_config.reg_read = sdam_read;
148*4882a593Smuzhiyun sdam->sdam_config.reg_write = sdam_write;
149*4882a593Smuzhiyun sdam->sdam_config.priv = sdam;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun nvmem = devm_nvmem_register(&pdev->dev, &sdam->sdam_config);
152*4882a593Smuzhiyun if (IS_ERR(nvmem)) {
153*4882a593Smuzhiyun dev_err(&pdev->dev,
154*4882a593Smuzhiyun "Failed to register SDAM nvmem device rc=%ld\n",
155*4882a593Smuzhiyun PTR_ERR(nvmem));
156*4882a593Smuzhiyun return -ENXIO;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun dev_dbg(&pdev->dev,
159*4882a593Smuzhiyun "SDAM base=%#x size=%u registered successfully\n",
160*4882a593Smuzhiyun sdam->base, sdam->size);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun static const struct of_device_id sdam_match_table[] = {
166*4882a593Smuzhiyun { .compatible = "qcom,spmi-sdam" },
167*4882a593Smuzhiyun {},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct platform_driver sdam_driver = {
171*4882a593Smuzhiyun .driver = {
172*4882a593Smuzhiyun .name = "qcom,spmi-sdam",
173*4882a593Smuzhiyun .of_match_table = sdam_match_table,
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun .probe = sdam_probe,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
sdam_init(void)178*4882a593Smuzhiyun static int __init sdam_init(void)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun return platform_driver_register(&sdam_driver);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun subsys_initcall(sdam_init);
183*4882a593Smuzhiyun
sdam_exit(void)184*4882a593Smuzhiyun static void __exit sdam_exit(void)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun return platform_driver_unregister(&sdam_driver);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun module_exit(sdam_exit);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun MODULE_DESCRIPTION("QCOM SPMI SDAM driver");
191*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
192