1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NXP LPC18xx/43xx OTP memory NVMEM driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2016 Joachim Eastwood <manabian@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on the imx ocotp driver,
8*4882a593Smuzhiyun * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * TODO: add support for writing OTP register via API in boot ROM.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
23*4882a593Smuzhiyun * at offset 0 from the base.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Bank 0 contains the part ID for Flashless devices and is reseverd for
26*4882a593Smuzhiyun * devices with Flash.
27*4882a593Smuzhiyun * Bank 1/2 is generale purpose or AES key storage for secure devices.
28*4882a593Smuzhiyun * Bank 3 contains control data, USB ID and generale purpose words.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun #define LPC18XX_OTP_NUM_BANKS 4
31*4882a593Smuzhiyun #define LPC18XX_OTP_WORDS_PER_BANK 4
32*4882a593Smuzhiyun #define LPC18XX_OTP_WORD_SIZE sizeof(u32)
33*4882a593Smuzhiyun #define LPC18XX_OTP_SIZE (LPC18XX_OTP_NUM_BANKS * \
34*4882a593Smuzhiyun LPC18XX_OTP_WORDS_PER_BANK * \
35*4882a593Smuzhiyun LPC18XX_OTP_WORD_SIZE)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun struct lpc18xx_otp {
38*4882a593Smuzhiyun void __iomem *base;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
lpc18xx_otp_read(void * context,unsigned int offset,void * val,size_t bytes)41*4882a593Smuzhiyun static int lpc18xx_otp_read(void *context, unsigned int offset,
42*4882a593Smuzhiyun void *val, size_t bytes)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct lpc18xx_otp *otp = context;
45*4882a593Smuzhiyun unsigned int count = bytes >> 2;
46*4882a593Smuzhiyun u32 index = offset >> 2;
47*4882a593Smuzhiyun u32 *buf = val;
48*4882a593Smuzhiyun int i;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (count > (LPC18XX_OTP_SIZE - index))
51*4882a593Smuzhiyun count = LPC18XX_OTP_SIZE - index;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun for (i = index; i < (index + count); i++)
54*4882a593Smuzhiyun *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct nvmem_config lpc18xx_otp_nvmem_config = {
60*4882a593Smuzhiyun .name = "lpc18xx-otp",
61*4882a593Smuzhiyun .read_only = true,
62*4882a593Smuzhiyun .word_size = LPC18XX_OTP_WORD_SIZE,
63*4882a593Smuzhiyun .stride = LPC18XX_OTP_WORD_SIZE,
64*4882a593Smuzhiyun .reg_read = lpc18xx_otp_read,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
lpc18xx_otp_probe(struct platform_device * pdev)67*4882a593Smuzhiyun static int lpc18xx_otp_probe(struct platform_device *pdev)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct nvmem_device *nvmem;
70*4882a593Smuzhiyun struct lpc18xx_otp *otp;
71*4882a593Smuzhiyun struct resource *res;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL);
74*4882a593Smuzhiyun if (!otp)
75*4882a593Smuzhiyun return -ENOMEM;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
78*4882a593Smuzhiyun otp->base = devm_ioremap_resource(&pdev->dev, res);
79*4882a593Smuzhiyun if (IS_ERR(otp->base))
80*4882a593Smuzhiyun return PTR_ERR(otp->base);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun lpc18xx_otp_nvmem_config.size = LPC18XX_OTP_SIZE;
83*4882a593Smuzhiyun lpc18xx_otp_nvmem_config.dev = &pdev->dev;
84*4882a593Smuzhiyun lpc18xx_otp_nvmem_config.priv = otp;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun nvmem = devm_nvmem_register(&pdev->dev, &lpc18xx_otp_nvmem_config);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(nvmem);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const struct of_device_id lpc18xx_otp_dt_ids[] = {
92*4882a593Smuzhiyun { .compatible = "nxp,lpc1850-otp" },
93*4882a593Smuzhiyun { },
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lpc18xx_otp_dt_ids);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static struct platform_driver lpc18xx_otp_driver = {
98*4882a593Smuzhiyun .probe = lpc18xx_otp_probe,
99*4882a593Smuzhiyun .driver = {
100*4882a593Smuzhiyun .name = "lpc18xx_otp",
101*4882a593Smuzhiyun .of_match_table = lpc18xx_otp_dt_ids,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun module_platform_driver(lpc18xx_otp_driver);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun MODULE_AUTHOR("Joachim Eastwoood <manabian@gmail.com>");
107*4882a593Smuzhiyun MODULE_DESCRIPTION("NXP LPC18xx OTP NVMEM driver");
108*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
109