1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NVM Express device driver
4*4882a593Smuzhiyun * Copyright (c) 2011-2014, Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/blkdev.h>
8*4882a593Smuzhiyun #include <linux/blk-mq.h>
9*4882a593Smuzhiyun #include <linux/compat.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <linux/hdreg.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/backing-dev.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/pr.h>
19*4882a593Smuzhiyun #include <linux/ptrace.h>
20*4882a593Smuzhiyun #include <linux/nvme_ioctl.h>
21*4882a593Smuzhiyun #include <linux/pm_qos.h>
22*4882a593Smuzhiyun #include <asm/unaligned.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "nvme.h"
25*4882a593Smuzhiyun #include "fabrics.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define CREATE_TRACE_POINTS
28*4882a593Smuzhiyun #include "trace.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define NVME_MINORS (1U << MINORBITS)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun unsigned int admin_timeout = 60;
33*4882a593Smuzhiyun module_param(admin_timeout, uint, 0644);
34*4882a593Smuzhiyun MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
35*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(admin_timeout);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun unsigned int nvme_io_timeout = 30;
38*4882a593Smuzhiyun module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
39*4882a593Smuzhiyun MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
40*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_io_timeout);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static unsigned char shutdown_timeout = 5;
43*4882a593Smuzhiyun module_param(shutdown_timeout, byte, 0644);
44*4882a593Smuzhiyun MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static u8 nvme_max_retries = 5;
47*4882a593Smuzhiyun module_param_named(max_retries, nvme_max_retries, byte, 0644);
48*4882a593Smuzhiyun MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static unsigned long default_ps_max_latency_us = 100000;
51*4882a593Smuzhiyun module_param(default_ps_max_latency_us, ulong, 0644);
52*4882a593Smuzhiyun MODULE_PARM_DESC(default_ps_max_latency_us,
53*4882a593Smuzhiyun "max power saving latency for new devices; use PM QOS to change per device");
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static bool force_apst;
56*4882a593Smuzhiyun module_param(force_apst, bool, 0644);
57*4882a593Smuzhiyun MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static bool streams;
60*4882a593Smuzhiyun module_param(streams, bool, 0644);
61*4882a593Smuzhiyun MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * nvme_wq - hosts nvme related works that are not reset or delete
65*4882a593Smuzhiyun * nvme_reset_wq - hosts nvme reset works
66*4882a593Smuzhiyun * nvme_delete_wq - hosts nvme delete works
67*4882a593Smuzhiyun *
68*4882a593Smuzhiyun * nvme_wq will host works such as scan, aen handling, fw activation,
69*4882a593Smuzhiyun * keep-alive, periodic reconnects etc. nvme_reset_wq
70*4882a593Smuzhiyun * runs reset works which also flush works hosted on nvme_wq for
71*4882a593Smuzhiyun * serialization purposes. nvme_delete_wq host controller deletion
72*4882a593Smuzhiyun * works which flush reset works for serialization.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun struct workqueue_struct *nvme_wq;
75*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_wq);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct workqueue_struct *nvme_reset_wq;
78*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_reset_wq);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun struct workqueue_struct *nvme_delete_wq;
81*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_delete_wq);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static LIST_HEAD(nvme_subsystems);
84*4882a593Smuzhiyun static DEFINE_MUTEX(nvme_subsystems_lock);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static DEFINE_IDA(nvme_instance_ida);
87*4882a593Smuzhiyun static dev_t nvme_chr_devt;
88*4882a593Smuzhiyun static struct class *nvme_class;
89*4882a593Smuzhiyun static struct class *nvme_subsys_class;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static void nvme_put_subsystem(struct nvme_subsystem *subsys);
92*4882a593Smuzhiyun static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
93*4882a593Smuzhiyun unsigned nsid);
94*4882a593Smuzhiyun
nvme_update_bdev_size(struct gendisk * disk)95*4882a593Smuzhiyun static void nvme_update_bdev_size(struct gendisk *disk)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct block_device *bdev = bdget_disk(disk, 0);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (bdev) {
100*4882a593Smuzhiyun bd_set_nr_sectors(bdev, get_capacity(disk));
101*4882a593Smuzhiyun bdput(bdev);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * Prepare a queue for teardown.
107*4882a593Smuzhiyun *
108*4882a593Smuzhiyun * This must forcibly unquiesce queues to avoid blocking dispatch, and only set
109*4882a593Smuzhiyun * the capacity to 0 after that to avoid blocking dispatchers that may be
110*4882a593Smuzhiyun * holding bd_butex. This will end buffered writers dirtying pages that can't
111*4882a593Smuzhiyun * be synced.
112*4882a593Smuzhiyun */
nvme_set_queue_dying(struct nvme_ns * ns)113*4882a593Smuzhiyun static void nvme_set_queue_dying(struct nvme_ns *ns)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun if (test_and_set_bit(NVME_NS_DEAD, &ns->flags))
116*4882a593Smuzhiyun return;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun blk_set_queue_dying(ns->queue);
119*4882a593Smuzhiyun blk_mq_unquiesce_queue(ns->queue);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun set_capacity(ns->disk, 0);
122*4882a593Smuzhiyun nvme_update_bdev_size(ns->disk);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
nvme_queue_scan(struct nvme_ctrl * ctrl)125*4882a593Smuzhiyun static void nvme_queue_scan(struct nvme_ctrl *ctrl)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun /*
128*4882a593Smuzhiyun * Only new queue scan work when admin and IO queues are both alive
129*4882a593Smuzhiyun */
130*4882a593Smuzhiyun if (ctrl->state == NVME_CTRL_LIVE && ctrl->tagset)
131*4882a593Smuzhiyun queue_work(nvme_wq, &ctrl->scan_work);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * Use this function to proceed with scheduling reset_work for a controller
136*4882a593Smuzhiyun * that had previously been set to the resetting state. This is intended for
137*4882a593Smuzhiyun * code paths that can't be interrupted by other reset attempts. A hot removal
138*4882a593Smuzhiyun * may prevent this from succeeding.
139*4882a593Smuzhiyun */
nvme_try_sched_reset(struct nvme_ctrl * ctrl)140*4882a593Smuzhiyun int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun if (ctrl->state != NVME_CTRL_RESETTING)
143*4882a593Smuzhiyun return -EBUSY;
144*4882a593Smuzhiyun if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
145*4882a593Smuzhiyun return -EBUSY;
146*4882a593Smuzhiyun return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
149*4882a593Smuzhiyun
nvme_reset_ctrl(struct nvme_ctrl * ctrl)150*4882a593Smuzhiyun int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
153*4882a593Smuzhiyun return -EBUSY;
154*4882a593Smuzhiyun if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
155*4882a593Smuzhiyun return -EBUSY;
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
159*4882a593Smuzhiyun
nvme_reset_ctrl_sync(struct nvme_ctrl * ctrl)160*4882a593Smuzhiyun int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun int ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ret = nvme_reset_ctrl(ctrl);
165*4882a593Smuzhiyun if (!ret) {
166*4882a593Smuzhiyun flush_work(&ctrl->reset_work);
167*4882a593Smuzhiyun if (ctrl->state != NVME_CTRL_LIVE)
168*4882a593Smuzhiyun ret = -ENETRESET;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return ret;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
174*4882a593Smuzhiyun
nvme_do_delete_ctrl(struct nvme_ctrl * ctrl)175*4882a593Smuzhiyun static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun dev_info(ctrl->device,
178*4882a593Smuzhiyun "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun flush_work(&ctrl->reset_work);
181*4882a593Smuzhiyun nvme_stop_ctrl(ctrl);
182*4882a593Smuzhiyun nvme_remove_namespaces(ctrl);
183*4882a593Smuzhiyun ctrl->ops->delete_ctrl(ctrl);
184*4882a593Smuzhiyun nvme_uninit_ctrl(ctrl);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
nvme_delete_ctrl_work(struct work_struct * work)187*4882a593Smuzhiyun static void nvme_delete_ctrl_work(struct work_struct *work)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
190*4882a593Smuzhiyun container_of(work, struct nvme_ctrl, delete_work);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun nvme_do_delete_ctrl(ctrl);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
nvme_delete_ctrl(struct nvme_ctrl * ctrl)195*4882a593Smuzhiyun int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
198*4882a593Smuzhiyun return -EBUSY;
199*4882a593Smuzhiyun if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
200*4882a593Smuzhiyun return -EBUSY;
201*4882a593Smuzhiyun return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
204*4882a593Smuzhiyun
nvme_delete_ctrl_sync(struct nvme_ctrl * ctrl)205*4882a593Smuzhiyun static void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun * Keep a reference until nvme_do_delete_ctrl() complete,
209*4882a593Smuzhiyun * since ->delete_ctrl can free the controller.
210*4882a593Smuzhiyun */
211*4882a593Smuzhiyun nvme_get_ctrl(ctrl);
212*4882a593Smuzhiyun if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
213*4882a593Smuzhiyun nvme_do_delete_ctrl(ctrl);
214*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
nvme_error_status(u16 status)217*4882a593Smuzhiyun static blk_status_t nvme_error_status(u16 status)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun switch (status & 0x7ff) {
220*4882a593Smuzhiyun case NVME_SC_SUCCESS:
221*4882a593Smuzhiyun return BLK_STS_OK;
222*4882a593Smuzhiyun case NVME_SC_CAP_EXCEEDED:
223*4882a593Smuzhiyun return BLK_STS_NOSPC;
224*4882a593Smuzhiyun case NVME_SC_LBA_RANGE:
225*4882a593Smuzhiyun case NVME_SC_CMD_INTERRUPTED:
226*4882a593Smuzhiyun case NVME_SC_NS_NOT_READY:
227*4882a593Smuzhiyun return BLK_STS_TARGET;
228*4882a593Smuzhiyun case NVME_SC_BAD_ATTRIBUTES:
229*4882a593Smuzhiyun case NVME_SC_ONCS_NOT_SUPPORTED:
230*4882a593Smuzhiyun case NVME_SC_INVALID_OPCODE:
231*4882a593Smuzhiyun case NVME_SC_INVALID_FIELD:
232*4882a593Smuzhiyun case NVME_SC_INVALID_NS:
233*4882a593Smuzhiyun return BLK_STS_NOTSUPP;
234*4882a593Smuzhiyun case NVME_SC_WRITE_FAULT:
235*4882a593Smuzhiyun case NVME_SC_READ_ERROR:
236*4882a593Smuzhiyun case NVME_SC_UNWRITTEN_BLOCK:
237*4882a593Smuzhiyun case NVME_SC_ACCESS_DENIED:
238*4882a593Smuzhiyun case NVME_SC_READ_ONLY:
239*4882a593Smuzhiyun case NVME_SC_COMPARE_FAILED:
240*4882a593Smuzhiyun return BLK_STS_MEDIUM;
241*4882a593Smuzhiyun case NVME_SC_GUARD_CHECK:
242*4882a593Smuzhiyun case NVME_SC_APPTAG_CHECK:
243*4882a593Smuzhiyun case NVME_SC_REFTAG_CHECK:
244*4882a593Smuzhiyun case NVME_SC_INVALID_PI:
245*4882a593Smuzhiyun return BLK_STS_PROTECTION;
246*4882a593Smuzhiyun case NVME_SC_RESERVATION_CONFLICT:
247*4882a593Smuzhiyun return BLK_STS_NEXUS;
248*4882a593Smuzhiyun case NVME_SC_HOST_PATH_ERROR:
249*4882a593Smuzhiyun return BLK_STS_TRANSPORT;
250*4882a593Smuzhiyun case NVME_SC_ZONE_TOO_MANY_ACTIVE:
251*4882a593Smuzhiyun return BLK_STS_ZONE_ACTIVE_RESOURCE;
252*4882a593Smuzhiyun case NVME_SC_ZONE_TOO_MANY_OPEN:
253*4882a593Smuzhiyun return BLK_STS_ZONE_OPEN_RESOURCE;
254*4882a593Smuzhiyun default:
255*4882a593Smuzhiyun return BLK_STS_IOERR;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
nvme_retry_req(struct request * req)259*4882a593Smuzhiyun static void nvme_retry_req(struct request *req)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun struct nvme_ns *ns = req->q->queuedata;
262*4882a593Smuzhiyun unsigned long delay = 0;
263*4882a593Smuzhiyun u16 crd;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* The mask and shift result must be <= 3 */
266*4882a593Smuzhiyun crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
267*4882a593Smuzhiyun if (ns && crd)
268*4882a593Smuzhiyun delay = ns->ctrl->crdt[crd - 1] * 100;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun nvme_req(req)->retries++;
271*4882a593Smuzhiyun blk_mq_requeue_request(req, false);
272*4882a593Smuzhiyun blk_mq_delay_kick_requeue_list(req->q, delay);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun enum nvme_disposition {
276*4882a593Smuzhiyun COMPLETE,
277*4882a593Smuzhiyun RETRY,
278*4882a593Smuzhiyun FAILOVER,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
nvme_decide_disposition(struct request * req)281*4882a593Smuzhiyun static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun if (likely(nvme_req(req)->status == 0))
284*4882a593Smuzhiyun return COMPLETE;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if (blk_noretry_request(req) ||
287*4882a593Smuzhiyun (nvme_req(req)->status & NVME_SC_DNR) ||
288*4882a593Smuzhiyun nvme_req(req)->retries >= nvme_max_retries)
289*4882a593Smuzhiyun return COMPLETE;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (req->cmd_flags & REQ_NVME_MPATH) {
292*4882a593Smuzhiyun if (nvme_is_path_error(nvme_req(req)->status) ||
293*4882a593Smuzhiyun blk_queue_dying(req->q))
294*4882a593Smuzhiyun return FAILOVER;
295*4882a593Smuzhiyun } else {
296*4882a593Smuzhiyun if (blk_queue_dying(req->q))
297*4882a593Smuzhiyun return COMPLETE;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return RETRY;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
nvme_end_req(struct request * req)303*4882a593Smuzhiyun static inline void nvme_end_req(struct request *req)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun blk_status_t status = nvme_error_status(nvme_req(req)->status);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
308*4882a593Smuzhiyun req_op(req) == REQ_OP_ZONE_APPEND)
309*4882a593Smuzhiyun req->__sector = nvme_lba_to_sect(req->q->queuedata,
310*4882a593Smuzhiyun le64_to_cpu(nvme_req(req)->result.u64));
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun nvme_trace_bio_complete(req, status);
313*4882a593Smuzhiyun blk_mq_end_request(req, status);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
nvme_complete_rq(struct request * req)316*4882a593Smuzhiyun void nvme_complete_rq(struct request *req)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun trace_nvme_complete_rq(req);
319*4882a593Smuzhiyun nvme_cleanup_cmd(req);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun if (nvme_req(req)->ctrl->kas)
322*4882a593Smuzhiyun nvme_req(req)->ctrl->comp_seen = true;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun switch (nvme_decide_disposition(req)) {
325*4882a593Smuzhiyun case COMPLETE:
326*4882a593Smuzhiyun nvme_end_req(req);
327*4882a593Smuzhiyun return;
328*4882a593Smuzhiyun case RETRY:
329*4882a593Smuzhiyun nvme_retry_req(req);
330*4882a593Smuzhiyun return;
331*4882a593Smuzhiyun case FAILOVER:
332*4882a593Smuzhiyun nvme_failover_req(req);
333*4882a593Smuzhiyun return;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_complete_rq);
337*4882a593Smuzhiyun
nvme_cancel_request(struct request * req,void * data,bool reserved)338*4882a593Smuzhiyun bool nvme_cancel_request(struct request *req, void *data, bool reserved)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
341*4882a593Smuzhiyun "Cancelling I/O %d", req->tag);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /* don't abort one completed request */
344*4882a593Smuzhiyun if (blk_mq_request_completed(req))
345*4882a593Smuzhiyun return true;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
348*4882a593Smuzhiyun nvme_req(req)->flags |= NVME_REQ_CANCELLED;
349*4882a593Smuzhiyun blk_mq_complete_request(req);
350*4882a593Smuzhiyun return true;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_cancel_request);
353*4882a593Smuzhiyun
nvme_cancel_tagset(struct nvme_ctrl * ctrl)354*4882a593Smuzhiyun void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun if (ctrl->tagset) {
357*4882a593Smuzhiyun blk_mq_tagset_busy_iter(ctrl->tagset,
358*4882a593Smuzhiyun nvme_cancel_request, ctrl);
359*4882a593Smuzhiyun blk_mq_tagset_wait_completed_request(ctrl->tagset);
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
363*4882a593Smuzhiyun
nvme_cancel_admin_tagset(struct nvme_ctrl * ctrl)364*4882a593Smuzhiyun void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun if (ctrl->admin_tagset) {
367*4882a593Smuzhiyun blk_mq_tagset_busy_iter(ctrl->admin_tagset,
368*4882a593Smuzhiyun nvme_cancel_request, ctrl);
369*4882a593Smuzhiyun blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
373*4882a593Smuzhiyun
nvme_change_ctrl_state(struct nvme_ctrl * ctrl,enum nvme_ctrl_state new_state)374*4882a593Smuzhiyun bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
375*4882a593Smuzhiyun enum nvme_ctrl_state new_state)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun enum nvme_ctrl_state old_state;
378*4882a593Smuzhiyun unsigned long flags;
379*4882a593Smuzhiyun bool changed = false;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun spin_lock_irqsave(&ctrl->lock, flags);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun old_state = ctrl->state;
384*4882a593Smuzhiyun switch (new_state) {
385*4882a593Smuzhiyun case NVME_CTRL_LIVE:
386*4882a593Smuzhiyun switch (old_state) {
387*4882a593Smuzhiyun case NVME_CTRL_NEW:
388*4882a593Smuzhiyun case NVME_CTRL_RESETTING:
389*4882a593Smuzhiyun case NVME_CTRL_CONNECTING:
390*4882a593Smuzhiyun changed = true;
391*4882a593Smuzhiyun fallthrough;
392*4882a593Smuzhiyun default:
393*4882a593Smuzhiyun break;
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun break;
396*4882a593Smuzhiyun case NVME_CTRL_RESETTING:
397*4882a593Smuzhiyun switch (old_state) {
398*4882a593Smuzhiyun case NVME_CTRL_NEW:
399*4882a593Smuzhiyun case NVME_CTRL_LIVE:
400*4882a593Smuzhiyun changed = true;
401*4882a593Smuzhiyun fallthrough;
402*4882a593Smuzhiyun default:
403*4882a593Smuzhiyun break;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun break;
406*4882a593Smuzhiyun case NVME_CTRL_CONNECTING:
407*4882a593Smuzhiyun switch (old_state) {
408*4882a593Smuzhiyun case NVME_CTRL_NEW:
409*4882a593Smuzhiyun case NVME_CTRL_RESETTING:
410*4882a593Smuzhiyun changed = true;
411*4882a593Smuzhiyun fallthrough;
412*4882a593Smuzhiyun default:
413*4882a593Smuzhiyun break;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun break;
416*4882a593Smuzhiyun case NVME_CTRL_DELETING:
417*4882a593Smuzhiyun switch (old_state) {
418*4882a593Smuzhiyun case NVME_CTRL_LIVE:
419*4882a593Smuzhiyun case NVME_CTRL_RESETTING:
420*4882a593Smuzhiyun case NVME_CTRL_CONNECTING:
421*4882a593Smuzhiyun changed = true;
422*4882a593Smuzhiyun fallthrough;
423*4882a593Smuzhiyun default:
424*4882a593Smuzhiyun break;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun case NVME_CTRL_DELETING_NOIO:
428*4882a593Smuzhiyun switch (old_state) {
429*4882a593Smuzhiyun case NVME_CTRL_DELETING:
430*4882a593Smuzhiyun case NVME_CTRL_DEAD:
431*4882a593Smuzhiyun changed = true;
432*4882a593Smuzhiyun fallthrough;
433*4882a593Smuzhiyun default:
434*4882a593Smuzhiyun break;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun break;
437*4882a593Smuzhiyun case NVME_CTRL_DEAD:
438*4882a593Smuzhiyun switch (old_state) {
439*4882a593Smuzhiyun case NVME_CTRL_DELETING:
440*4882a593Smuzhiyun changed = true;
441*4882a593Smuzhiyun fallthrough;
442*4882a593Smuzhiyun default:
443*4882a593Smuzhiyun break;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun break;
446*4882a593Smuzhiyun default:
447*4882a593Smuzhiyun break;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (changed) {
451*4882a593Smuzhiyun ctrl->state = new_state;
452*4882a593Smuzhiyun wake_up_all(&ctrl->state_wq);
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun spin_unlock_irqrestore(&ctrl->lock, flags);
456*4882a593Smuzhiyun if (changed && ctrl->state == NVME_CTRL_LIVE)
457*4882a593Smuzhiyun nvme_kick_requeue_lists(ctrl);
458*4882a593Smuzhiyun return changed;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /*
463*4882a593Smuzhiyun * Returns true for sink states that can't ever transition back to live.
464*4882a593Smuzhiyun */
nvme_state_terminal(struct nvme_ctrl * ctrl)465*4882a593Smuzhiyun static bool nvme_state_terminal(struct nvme_ctrl *ctrl)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun switch (ctrl->state) {
468*4882a593Smuzhiyun case NVME_CTRL_NEW:
469*4882a593Smuzhiyun case NVME_CTRL_LIVE:
470*4882a593Smuzhiyun case NVME_CTRL_RESETTING:
471*4882a593Smuzhiyun case NVME_CTRL_CONNECTING:
472*4882a593Smuzhiyun return false;
473*4882a593Smuzhiyun case NVME_CTRL_DELETING:
474*4882a593Smuzhiyun case NVME_CTRL_DELETING_NOIO:
475*4882a593Smuzhiyun case NVME_CTRL_DEAD:
476*4882a593Smuzhiyun return true;
477*4882a593Smuzhiyun default:
478*4882a593Smuzhiyun WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state);
479*4882a593Smuzhiyun return true;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun /*
484*4882a593Smuzhiyun * Waits for the controller state to be resetting, or returns false if it is
485*4882a593Smuzhiyun * not possible to ever transition to that state.
486*4882a593Smuzhiyun */
nvme_wait_reset(struct nvme_ctrl * ctrl)487*4882a593Smuzhiyun bool nvme_wait_reset(struct nvme_ctrl *ctrl)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun wait_event(ctrl->state_wq,
490*4882a593Smuzhiyun nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
491*4882a593Smuzhiyun nvme_state_terminal(ctrl));
492*4882a593Smuzhiyun return ctrl->state == NVME_CTRL_RESETTING;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_wait_reset);
495*4882a593Smuzhiyun
nvme_free_ns_head(struct kref * ref)496*4882a593Smuzhiyun static void nvme_free_ns_head(struct kref *ref)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun struct nvme_ns_head *head =
499*4882a593Smuzhiyun container_of(ref, struct nvme_ns_head, ref);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun nvme_mpath_remove_disk(head);
502*4882a593Smuzhiyun ida_simple_remove(&head->subsys->ns_ida, head->instance);
503*4882a593Smuzhiyun cleanup_srcu_struct(&head->srcu);
504*4882a593Smuzhiyun nvme_put_subsystem(head->subsys);
505*4882a593Smuzhiyun kfree(head);
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
nvme_put_ns_head(struct nvme_ns_head * head)508*4882a593Smuzhiyun static void nvme_put_ns_head(struct nvme_ns_head *head)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun kref_put(&head->ref, nvme_free_ns_head);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
nvme_free_ns(struct kref * kref)513*4882a593Smuzhiyun static void nvme_free_ns(struct kref *kref)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun if (ns->ndev)
518*4882a593Smuzhiyun nvme_nvm_unregister(ns);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun put_disk(ns->disk);
521*4882a593Smuzhiyun nvme_put_ns_head(ns->head);
522*4882a593Smuzhiyun nvme_put_ctrl(ns->ctrl);
523*4882a593Smuzhiyun kfree(ns);
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
nvme_put_ns(struct nvme_ns * ns)526*4882a593Smuzhiyun void nvme_put_ns(struct nvme_ns *ns)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun kref_put(&ns->kref, nvme_free_ns);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
531*4882a593Smuzhiyun
nvme_clear_nvme_request(struct request * req)532*4882a593Smuzhiyun static inline void nvme_clear_nvme_request(struct request *req)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun nvme_req(req)->retries = 0;
535*4882a593Smuzhiyun nvme_req(req)->flags = 0;
536*4882a593Smuzhiyun req->rq_flags |= RQF_DONTPREP;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
nvme_req_op(struct nvme_command * cmd)539*4882a593Smuzhiyun static inline unsigned int nvme_req_op(struct nvme_command *cmd)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
nvme_init_request(struct request * req,struct nvme_command * cmd)544*4882a593Smuzhiyun static inline void nvme_init_request(struct request *req,
545*4882a593Smuzhiyun struct nvme_command *cmd)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun if (req->q->queuedata)
548*4882a593Smuzhiyun req->timeout = NVME_IO_TIMEOUT;
549*4882a593Smuzhiyun else /* no queuedata implies admin queue */
550*4882a593Smuzhiyun req->timeout = ADMIN_TIMEOUT;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun req->cmd_flags |= REQ_FAILFAST_DRIVER;
553*4882a593Smuzhiyun nvme_clear_nvme_request(req);
554*4882a593Smuzhiyun nvme_req(req)->cmd = cmd;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun
nvme_alloc_request(struct request_queue * q,struct nvme_command * cmd,blk_mq_req_flags_t flags)557*4882a593Smuzhiyun struct request *nvme_alloc_request(struct request_queue *q,
558*4882a593Smuzhiyun struct nvme_command *cmd, blk_mq_req_flags_t flags)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun struct request *req;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun req = blk_mq_alloc_request(q, nvme_req_op(cmd), flags);
563*4882a593Smuzhiyun if (!IS_ERR(req))
564*4882a593Smuzhiyun nvme_init_request(req, cmd);
565*4882a593Smuzhiyun return req;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_alloc_request);
568*4882a593Smuzhiyun
nvme_alloc_request_qid(struct request_queue * q,struct nvme_command * cmd,blk_mq_req_flags_t flags,int qid)569*4882a593Smuzhiyun struct request *nvme_alloc_request_qid(struct request_queue *q,
570*4882a593Smuzhiyun struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun struct request *req;
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), flags,
575*4882a593Smuzhiyun qid ? qid - 1 : 0);
576*4882a593Smuzhiyun if (!IS_ERR(req))
577*4882a593Smuzhiyun nvme_init_request(req, cmd);
578*4882a593Smuzhiyun return req;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_alloc_request_qid);
581*4882a593Smuzhiyun
nvme_toggle_streams(struct nvme_ctrl * ctrl,bool enable)582*4882a593Smuzhiyun static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct nvme_command c;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun c.directive.opcode = nvme_admin_directive_send;
589*4882a593Smuzhiyun c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
590*4882a593Smuzhiyun c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
591*4882a593Smuzhiyun c.directive.dtype = NVME_DIR_IDENTIFY;
592*4882a593Smuzhiyun c.directive.tdtype = NVME_DIR_STREAMS;
593*4882a593Smuzhiyun c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
nvme_disable_streams(struct nvme_ctrl * ctrl)598*4882a593Smuzhiyun static int nvme_disable_streams(struct nvme_ctrl *ctrl)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun return nvme_toggle_streams(ctrl, false);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
nvme_enable_streams(struct nvme_ctrl * ctrl)603*4882a593Smuzhiyun static int nvme_enable_streams(struct nvme_ctrl *ctrl)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun return nvme_toggle_streams(ctrl, true);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
nvme_get_stream_params(struct nvme_ctrl * ctrl,struct streams_directive_params * s,u32 nsid)608*4882a593Smuzhiyun static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
609*4882a593Smuzhiyun struct streams_directive_params *s, u32 nsid)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun struct nvme_command c;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
614*4882a593Smuzhiyun memset(s, 0, sizeof(*s));
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun c.directive.opcode = nvme_admin_directive_recv;
617*4882a593Smuzhiyun c.directive.nsid = cpu_to_le32(nsid);
618*4882a593Smuzhiyun c.directive.numd = cpu_to_le32(nvme_bytes_to_numd(sizeof(*s)));
619*4882a593Smuzhiyun c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
620*4882a593Smuzhiyun c.directive.dtype = NVME_DIR_STREAMS;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
nvme_configure_directives(struct nvme_ctrl * ctrl)625*4882a593Smuzhiyun static int nvme_configure_directives(struct nvme_ctrl *ctrl)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun struct streams_directive_params s;
628*4882a593Smuzhiyun int ret;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
631*4882a593Smuzhiyun return 0;
632*4882a593Smuzhiyun if (!streams)
633*4882a593Smuzhiyun return 0;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun ret = nvme_enable_streams(ctrl);
636*4882a593Smuzhiyun if (ret)
637*4882a593Smuzhiyun return ret;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
640*4882a593Smuzhiyun if (ret)
641*4882a593Smuzhiyun goto out_disable_stream;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun ctrl->nssa = le16_to_cpu(s.nssa);
644*4882a593Smuzhiyun if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
645*4882a593Smuzhiyun dev_info(ctrl->device, "too few streams (%u) available\n",
646*4882a593Smuzhiyun ctrl->nssa);
647*4882a593Smuzhiyun goto out_disable_stream;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun ctrl->nr_streams = min_t(u16, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
651*4882a593Smuzhiyun dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
652*4882a593Smuzhiyun return 0;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun out_disable_stream:
655*4882a593Smuzhiyun nvme_disable_streams(ctrl);
656*4882a593Smuzhiyun return ret;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun /*
660*4882a593Smuzhiyun * Check if 'req' has a write hint associated with it. If it does, assign
661*4882a593Smuzhiyun * a valid namespace stream to the write.
662*4882a593Smuzhiyun */
nvme_assign_write_stream(struct nvme_ctrl * ctrl,struct request * req,u16 * control,u32 * dsmgmt)663*4882a593Smuzhiyun static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
664*4882a593Smuzhiyun struct request *req, u16 *control,
665*4882a593Smuzhiyun u32 *dsmgmt)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun enum rw_hint streamid = req->write_hint;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
670*4882a593Smuzhiyun streamid = 0;
671*4882a593Smuzhiyun else {
672*4882a593Smuzhiyun streamid--;
673*4882a593Smuzhiyun if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
674*4882a593Smuzhiyun return;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun *control |= NVME_RW_DTYPE_STREAMS;
677*4882a593Smuzhiyun *dsmgmt |= streamid << 16;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun if (streamid < ARRAY_SIZE(req->q->write_hints))
681*4882a593Smuzhiyun req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
nvme_setup_passthrough(struct request * req,struct nvme_command * cmd)684*4882a593Smuzhiyun static inline void nvme_setup_passthrough(struct request *req,
685*4882a593Smuzhiyun struct nvme_command *cmd)
686*4882a593Smuzhiyun {
687*4882a593Smuzhiyun memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
688*4882a593Smuzhiyun /* passthru commands should let the driver set the SGL flags */
689*4882a593Smuzhiyun cmd->common.flags &= ~NVME_CMD_SGL_ALL;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
nvme_setup_flush(struct nvme_ns * ns,struct nvme_command * cmnd)692*4882a593Smuzhiyun static inline void nvme_setup_flush(struct nvme_ns *ns,
693*4882a593Smuzhiyun struct nvme_command *cmnd)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun cmnd->common.opcode = nvme_cmd_flush;
696*4882a593Smuzhiyun cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
nvme_setup_discard(struct nvme_ns * ns,struct request * req,struct nvme_command * cmnd)699*4882a593Smuzhiyun static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
700*4882a593Smuzhiyun struct nvme_command *cmnd)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
703*4882a593Smuzhiyun struct nvme_dsm_range *range;
704*4882a593Smuzhiyun struct bio *bio;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun /*
707*4882a593Smuzhiyun * Some devices do not consider the DSM 'Number of Ranges' field when
708*4882a593Smuzhiyun * determining how much data to DMA. Always allocate memory for maximum
709*4882a593Smuzhiyun * number of segments to prevent device reading beyond end of buffer.
710*4882a593Smuzhiyun */
711*4882a593Smuzhiyun static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
714*4882a593Smuzhiyun if (!range) {
715*4882a593Smuzhiyun /*
716*4882a593Smuzhiyun * If we fail allocation our range, fallback to the controller
717*4882a593Smuzhiyun * discard page. If that's also busy, it's safe to return
718*4882a593Smuzhiyun * busy, as we know we can make progress once that's freed.
719*4882a593Smuzhiyun */
720*4882a593Smuzhiyun if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
721*4882a593Smuzhiyun return BLK_STS_RESOURCE;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun range = page_address(ns->ctrl->discard_page);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun __rq_for_each_bio(bio, req) {
727*4882a593Smuzhiyun u64 slba = nvme_sect_to_lba(ns, bio->bi_iter.bi_sector);
728*4882a593Smuzhiyun u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (n < segments) {
731*4882a593Smuzhiyun range[n].cattr = cpu_to_le32(0);
732*4882a593Smuzhiyun range[n].nlb = cpu_to_le32(nlb);
733*4882a593Smuzhiyun range[n].slba = cpu_to_le64(slba);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun n++;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun if (WARN_ON_ONCE(n != segments)) {
739*4882a593Smuzhiyun if (virt_to_page(range) == ns->ctrl->discard_page)
740*4882a593Smuzhiyun clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
741*4882a593Smuzhiyun else
742*4882a593Smuzhiyun kfree(range);
743*4882a593Smuzhiyun return BLK_STS_IOERR;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun cmnd->dsm.opcode = nvme_cmd_dsm;
747*4882a593Smuzhiyun cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
748*4882a593Smuzhiyun cmnd->dsm.nr = cpu_to_le32(segments - 1);
749*4882a593Smuzhiyun cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun req->special_vec.bv_page = virt_to_page(range);
752*4882a593Smuzhiyun req->special_vec.bv_offset = offset_in_page(range);
753*4882a593Smuzhiyun req->special_vec.bv_len = alloc_size;
754*4882a593Smuzhiyun req->rq_flags |= RQF_SPECIAL_PAYLOAD;
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return BLK_STS_OK;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
nvme_setup_write_zeroes(struct nvme_ns * ns,struct request * req,struct nvme_command * cmnd)759*4882a593Smuzhiyun static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
760*4882a593Smuzhiyun struct request *req, struct nvme_command *cmnd)
761*4882a593Smuzhiyun {
762*4882a593Smuzhiyun if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
763*4882a593Smuzhiyun return nvme_setup_discard(ns, req, cmnd);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
766*4882a593Smuzhiyun cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
767*4882a593Smuzhiyun cmnd->write_zeroes.slba =
768*4882a593Smuzhiyun cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
769*4882a593Smuzhiyun cmnd->write_zeroes.length =
770*4882a593Smuzhiyun cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
771*4882a593Smuzhiyun if (nvme_ns_has_pi(ns))
772*4882a593Smuzhiyun cmnd->write_zeroes.control = cpu_to_le16(NVME_RW_PRINFO_PRACT);
773*4882a593Smuzhiyun else
774*4882a593Smuzhiyun cmnd->write_zeroes.control = 0;
775*4882a593Smuzhiyun return BLK_STS_OK;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
nvme_setup_rw(struct nvme_ns * ns,struct request * req,struct nvme_command * cmnd,enum nvme_opcode op)778*4882a593Smuzhiyun static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
779*4882a593Smuzhiyun struct request *req, struct nvme_command *cmnd,
780*4882a593Smuzhiyun enum nvme_opcode op)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
783*4882a593Smuzhiyun u16 control = 0;
784*4882a593Smuzhiyun u32 dsmgmt = 0;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun if (req->cmd_flags & REQ_FUA)
787*4882a593Smuzhiyun control |= NVME_RW_FUA;
788*4882a593Smuzhiyun if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
789*4882a593Smuzhiyun control |= NVME_RW_LR;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun if (req->cmd_flags & REQ_RAHEAD)
792*4882a593Smuzhiyun dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun cmnd->rw.opcode = op;
795*4882a593Smuzhiyun cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
796*4882a593Smuzhiyun cmnd->rw.slba = cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
797*4882a593Smuzhiyun cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
800*4882a593Smuzhiyun nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (ns->ms) {
803*4882a593Smuzhiyun /*
804*4882a593Smuzhiyun * If formated with metadata, the block layer always provides a
805*4882a593Smuzhiyun * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
806*4882a593Smuzhiyun * we enable the PRACT bit for protection information or set the
807*4882a593Smuzhiyun * namespace capacity to zero to prevent any I/O.
808*4882a593Smuzhiyun */
809*4882a593Smuzhiyun if (!blk_integrity_rq(req)) {
810*4882a593Smuzhiyun if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
811*4882a593Smuzhiyun return BLK_STS_NOTSUPP;
812*4882a593Smuzhiyun control |= NVME_RW_PRINFO_PRACT;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun switch (ns->pi_type) {
816*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE3:
817*4882a593Smuzhiyun control |= NVME_RW_PRINFO_PRCHK_GUARD;
818*4882a593Smuzhiyun break;
819*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE1:
820*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE2:
821*4882a593Smuzhiyun control |= NVME_RW_PRINFO_PRCHK_GUARD |
822*4882a593Smuzhiyun NVME_RW_PRINFO_PRCHK_REF;
823*4882a593Smuzhiyun if (op == nvme_cmd_zone_append)
824*4882a593Smuzhiyun control |= NVME_RW_APPEND_PIREMAP;
825*4882a593Smuzhiyun cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
826*4882a593Smuzhiyun break;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun cmnd->rw.control = cpu_to_le16(control);
831*4882a593Smuzhiyun cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
832*4882a593Smuzhiyun return 0;
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
nvme_cleanup_cmd(struct request * req)835*4882a593Smuzhiyun void nvme_cleanup_cmd(struct request *req)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
838*4882a593Smuzhiyun struct nvme_ns *ns = req->rq_disk->private_data;
839*4882a593Smuzhiyun struct page *page = req->special_vec.bv_page;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun if (page == ns->ctrl->discard_page)
842*4882a593Smuzhiyun clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
843*4882a593Smuzhiyun else
844*4882a593Smuzhiyun kfree(page_address(page) + req->special_vec.bv_offset);
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
848*4882a593Smuzhiyun
nvme_setup_cmd(struct nvme_ns * ns,struct request * req,struct nvme_command * cmd)849*4882a593Smuzhiyun blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
850*4882a593Smuzhiyun struct nvme_command *cmd)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
853*4882a593Smuzhiyun blk_status_t ret = BLK_STS_OK;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if (!(req->rq_flags & RQF_DONTPREP))
856*4882a593Smuzhiyun nvme_clear_nvme_request(req);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun memset(cmd, 0, sizeof(*cmd));
859*4882a593Smuzhiyun switch (req_op(req)) {
860*4882a593Smuzhiyun case REQ_OP_DRV_IN:
861*4882a593Smuzhiyun case REQ_OP_DRV_OUT:
862*4882a593Smuzhiyun nvme_setup_passthrough(req, cmd);
863*4882a593Smuzhiyun break;
864*4882a593Smuzhiyun case REQ_OP_FLUSH:
865*4882a593Smuzhiyun nvme_setup_flush(ns, cmd);
866*4882a593Smuzhiyun break;
867*4882a593Smuzhiyun case REQ_OP_ZONE_RESET_ALL:
868*4882a593Smuzhiyun case REQ_OP_ZONE_RESET:
869*4882a593Smuzhiyun ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
870*4882a593Smuzhiyun break;
871*4882a593Smuzhiyun case REQ_OP_ZONE_OPEN:
872*4882a593Smuzhiyun ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
873*4882a593Smuzhiyun break;
874*4882a593Smuzhiyun case REQ_OP_ZONE_CLOSE:
875*4882a593Smuzhiyun ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
876*4882a593Smuzhiyun break;
877*4882a593Smuzhiyun case REQ_OP_ZONE_FINISH:
878*4882a593Smuzhiyun ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
879*4882a593Smuzhiyun break;
880*4882a593Smuzhiyun case REQ_OP_WRITE_ZEROES:
881*4882a593Smuzhiyun ret = nvme_setup_write_zeroes(ns, req, cmd);
882*4882a593Smuzhiyun break;
883*4882a593Smuzhiyun case REQ_OP_DISCARD:
884*4882a593Smuzhiyun ret = nvme_setup_discard(ns, req, cmd);
885*4882a593Smuzhiyun break;
886*4882a593Smuzhiyun case REQ_OP_READ:
887*4882a593Smuzhiyun ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
888*4882a593Smuzhiyun break;
889*4882a593Smuzhiyun case REQ_OP_WRITE:
890*4882a593Smuzhiyun ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
891*4882a593Smuzhiyun break;
892*4882a593Smuzhiyun case REQ_OP_ZONE_APPEND:
893*4882a593Smuzhiyun ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
894*4882a593Smuzhiyun break;
895*4882a593Smuzhiyun default:
896*4882a593Smuzhiyun WARN_ON_ONCE(1);
897*4882a593Smuzhiyun return BLK_STS_IOERR;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN))
901*4882a593Smuzhiyun nvme_req(req)->genctr++;
902*4882a593Smuzhiyun cmd->common.command_id = nvme_cid(req);
903*4882a593Smuzhiyun trace_nvme_setup_cmd(req, cmd);
904*4882a593Smuzhiyun return ret;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_setup_cmd);
907*4882a593Smuzhiyun
nvme_end_sync_rq(struct request * rq,blk_status_t error)908*4882a593Smuzhiyun static void nvme_end_sync_rq(struct request *rq, blk_status_t error)
909*4882a593Smuzhiyun {
910*4882a593Smuzhiyun struct completion *waiting = rq->end_io_data;
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun rq->end_io_data = NULL;
913*4882a593Smuzhiyun complete(waiting);
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
nvme_execute_rq_polled(struct request_queue * q,struct gendisk * bd_disk,struct request * rq,int at_head)916*4882a593Smuzhiyun static void nvme_execute_rq_polled(struct request_queue *q,
917*4882a593Smuzhiyun struct gendisk *bd_disk, struct request *rq, int at_head)
918*4882a593Smuzhiyun {
919*4882a593Smuzhiyun DECLARE_COMPLETION_ONSTACK(wait);
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun WARN_ON_ONCE(!test_bit(QUEUE_FLAG_POLL, &q->queue_flags));
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun rq->cmd_flags |= REQ_HIPRI;
924*4882a593Smuzhiyun rq->end_io_data = &wait;
925*4882a593Smuzhiyun blk_execute_rq_nowait(q, bd_disk, rq, at_head, nvme_end_sync_rq);
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun while (!completion_done(&wait)) {
928*4882a593Smuzhiyun blk_poll(q, request_to_qc_t(rq->mq_hctx, rq), true);
929*4882a593Smuzhiyun cond_resched();
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun /*
934*4882a593Smuzhiyun * Returns 0 on success. If the result is negative, it's a Linux error code;
935*4882a593Smuzhiyun * if the result is positive, it's an NVM Express status code
936*4882a593Smuzhiyun */
__nvme_submit_sync_cmd(struct request_queue * q,struct nvme_command * cmd,union nvme_result * result,void * buffer,unsigned bufflen,unsigned timeout,int qid,int at_head,blk_mq_req_flags_t flags,bool poll)937*4882a593Smuzhiyun int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
938*4882a593Smuzhiyun union nvme_result *result, void *buffer, unsigned bufflen,
939*4882a593Smuzhiyun unsigned timeout, int qid, int at_head,
940*4882a593Smuzhiyun blk_mq_req_flags_t flags, bool poll)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun struct request *req;
943*4882a593Smuzhiyun int ret;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun if (qid == NVME_QID_ANY)
946*4882a593Smuzhiyun req = nvme_alloc_request(q, cmd, flags);
947*4882a593Smuzhiyun else
948*4882a593Smuzhiyun req = nvme_alloc_request_qid(q, cmd, flags, qid);
949*4882a593Smuzhiyun if (IS_ERR(req))
950*4882a593Smuzhiyun return PTR_ERR(req);
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun if (timeout)
953*4882a593Smuzhiyun req->timeout = timeout;
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun if (buffer && bufflen) {
956*4882a593Smuzhiyun ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
957*4882a593Smuzhiyun if (ret)
958*4882a593Smuzhiyun goto out;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun if (poll)
962*4882a593Smuzhiyun nvme_execute_rq_polled(req->q, NULL, req, at_head);
963*4882a593Smuzhiyun else
964*4882a593Smuzhiyun blk_execute_rq(req->q, NULL, req, at_head);
965*4882a593Smuzhiyun if (result)
966*4882a593Smuzhiyun *result = nvme_req(req)->result;
967*4882a593Smuzhiyun if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
968*4882a593Smuzhiyun ret = -EINTR;
969*4882a593Smuzhiyun else
970*4882a593Smuzhiyun ret = nvme_req(req)->status;
971*4882a593Smuzhiyun out:
972*4882a593Smuzhiyun blk_mq_free_request(req);
973*4882a593Smuzhiyun return ret;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
976*4882a593Smuzhiyun
nvme_submit_sync_cmd(struct request_queue * q,struct nvme_command * cmd,void * buffer,unsigned bufflen)977*4882a593Smuzhiyun int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
978*4882a593Smuzhiyun void *buffer, unsigned bufflen)
979*4882a593Smuzhiyun {
980*4882a593Smuzhiyun return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
981*4882a593Smuzhiyun NVME_QID_ANY, 0, 0, false);
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
984*4882a593Smuzhiyun
nvme_add_user_metadata(struct bio * bio,void __user * ubuf,unsigned len,u32 seed,bool write)985*4882a593Smuzhiyun static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
986*4882a593Smuzhiyun unsigned len, u32 seed, bool write)
987*4882a593Smuzhiyun {
988*4882a593Smuzhiyun struct bio_integrity_payload *bip;
989*4882a593Smuzhiyun int ret = -ENOMEM;
990*4882a593Smuzhiyun void *buf;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun buf = kmalloc(len, GFP_KERNEL);
993*4882a593Smuzhiyun if (!buf)
994*4882a593Smuzhiyun goto out;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun ret = -EFAULT;
997*4882a593Smuzhiyun if (write && copy_from_user(buf, ubuf, len))
998*4882a593Smuzhiyun goto out_free_meta;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
1001*4882a593Smuzhiyun if (IS_ERR(bip)) {
1002*4882a593Smuzhiyun ret = PTR_ERR(bip);
1003*4882a593Smuzhiyun goto out_free_meta;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun bip->bip_iter.bi_size = len;
1007*4882a593Smuzhiyun bip->bip_iter.bi_sector = seed;
1008*4882a593Smuzhiyun ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
1009*4882a593Smuzhiyun offset_in_page(buf));
1010*4882a593Smuzhiyun if (ret == len)
1011*4882a593Smuzhiyun return buf;
1012*4882a593Smuzhiyun ret = -ENOMEM;
1013*4882a593Smuzhiyun out_free_meta:
1014*4882a593Smuzhiyun kfree(buf);
1015*4882a593Smuzhiyun out:
1016*4882a593Smuzhiyun return ERR_PTR(ret);
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun
nvme_known_admin_effects(u8 opcode)1019*4882a593Smuzhiyun static u32 nvme_known_admin_effects(u8 opcode)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun switch (opcode) {
1022*4882a593Smuzhiyun case nvme_admin_format_nvm:
1023*4882a593Smuzhiyun return NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_NCC |
1024*4882a593Smuzhiyun NVME_CMD_EFFECTS_CSE_MASK;
1025*4882a593Smuzhiyun case nvme_admin_sanitize_nvm:
1026*4882a593Smuzhiyun return NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK;
1027*4882a593Smuzhiyun default:
1028*4882a593Smuzhiyun break;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun return 0;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun
nvme_command_effects(struct nvme_ctrl * ctrl,struct nvme_ns * ns,u8 opcode)1033*4882a593Smuzhiyun u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun u32 effects = 0;
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun if (ns) {
1038*4882a593Smuzhiyun if (ns->head->effects)
1039*4882a593Smuzhiyun effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
1040*4882a593Smuzhiyun if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
1041*4882a593Smuzhiyun dev_warn(ctrl->device,
1042*4882a593Smuzhiyun "IO command:%02x has unhandled effects:%08x\n",
1043*4882a593Smuzhiyun opcode, effects);
1044*4882a593Smuzhiyun return 0;
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun if (ctrl->effects)
1048*4882a593Smuzhiyun effects = le32_to_cpu(ctrl->effects->acs[opcode]);
1049*4882a593Smuzhiyun effects |= nvme_known_admin_effects(opcode);
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun return effects;
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1054*4882a593Smuzhiyun
nvme_passthru_start(struct nvme_ctrl * ctrl,struct nvme_ns * ns,u8 opcode)1055*4882a593Smuzhiyun static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1056*4882a593Smuzhiyun u8 opcode)
1057*4882a593Smuzhiyun {
1058*4882a593Smuzhiyun u32 effects = nvme_command_effects(ctrl, ns, opcode);
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun /*
1061*4882a593Smuzhiyun * For simplicity, IO to all namespaces is quiesced even if the command
1062*4882a593Smuzhiyun * effects say only one namespace is affected.
1063*4882a593Smuzhiyun */
1064*4882a593Smuzhiyun if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
1065*4882a593Smuzhiyun mutex_lock(&ctrl->scan_lock);
1066*4882a593Smuzhiyun mutex_lock(&ctrl->subsys->lock);
1067*4882a593Smuzhiyun nvme_mpath_start_freeze(ctrl->subsys);
1068*4882a593Smuzhiyun nvme_mpath_wait_freeze(ctrl->subsys);
1069*4882a593Smuzhiyun nvme_start_freeze(ctrl);
1070*4882a593Smuzhiyun nvme_wait_freeze(ctrl);
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun return effects;
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun
nvme_passthru_end(struct nvme_ctrl * ctrl,u32 effects)1075*4882a593Smuzhiyun static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
1078*4882a593Smuzhiyun nvme_unfreeze(ctrl);
1079*4882a593Smuzhiyun nvme_mpath_unfreeze(ctrl->subsys);
1080*4882a593Smuzhiyun mutex_unlock(&ctrl->subsys->lock);
1081*4882a593Smuzhiyun nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
1082*4882a593Smuzhiyun mutex_unlock(&ctrl->scan_lock);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun if (effects & NVME_CMD_EFFECTS_CCC)
1085*4882a593Smuzhiyun nvme_init_identify(ctrl);
1086*4882a593Smuzhiyun if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1087*4882a593Smuzhiyun nvme_queue_scan(ctrl);
1088*4882a593Smuzhiyun flush_work(&ctrl->scan_work);
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun
nvme_execute_passthru_rq(struct request * rq)1092*4882a593Smuzhiyun void nvme_execute_passthru_rq(struct request *rq)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun struct nvme_command *cmd = nvme_req(rq)->cmd;
1095*4882a593Smuzhiyun struct nvme_ctrl *ctrl = nvme_req(rq)->ctrl;
1096*4882a593Smuzhiyun struct nvme_ns *ns = rq->q->queuedata;
1097*4882a593Smuzhiyun struct gendisk *disk = ns ? ns->disk : NULL;
1098*4882a593Smuzhiyun u32 effects;
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun effects = nvme_passthru_start(ctrl, ns, cmd->common.opcode);
1101*4882a593Smuzhiyun blk_execute_rq(rq->q, disk, rq, 0);
1102*4882a593Smuzhiyun nvme_passthru_end(ctrl, effects);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun EXPORT_SYMBOL_NS_GPL(nvme_execute_passthru_rq, NVME_TARGET_PASSTHRU);
1105*4882a593Smuzhiyun
nvme_submit_user_cmd(struct request_queue * q,struct nvme_command * cmd,void __user * ubuffer,unsigned bufflen,void __user * meta_buffer,unsigned meta_len,u32 meta_seed,u64 * result,unsigned timeout)1106*4882a593Smuzhiyun static int nvme_submit_user_cmd(struct request_queue *q,
1107*4882a593Smuzhiyun struct nvme_command *cmd, void __user *ubuffer,
1108*4882a593Smuzhiyun unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
1109*4882a593Smuzhiyun u32 meta_seed, u64 *result, unsigned timeout)
1110*4882a593Smuzhiyun {
1111*4882a593Smuzhiyun bool write = nvme_is_write(cmd);
1112*4882a593Smuzhiyun struct nvme_ns *ns = q->queuedata;
1113*4882a593Smuzhiyun struct gendisk *disk = ns ? ns->disk : NULL;
1114*4882a593Smuzhiyun struct request *req;
1115*4882a593Smuzhiyun struct bio *bio = NULL;
1116*4882a593Smuzhiyun void *meta = NULL;
1117*4882a593Smuzhiyun int ret;
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun req = nvme_alloc_request(q, cmd, 0);
1120*4882a593Smuzhiyun if (IS_ERR(req))
1121*4882a593Smuzhiyun return PTR_ERR(req);
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun if (timeout)
1124*4882a593Smuzhiyun req->timeout = timeout;
1125*4882a593Smuzhiyun nvme_req(req)->flags |= NVME_REQ_USERCMD;
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun if (ubuffer && bufflen) {
1128*4882a593Smuzhiyun ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1129*4882a593Smuzhiyun GFP_KERNEL);
1130*4882a593Smuzhiyun if (ret)
1131*4882a593Smuzhiyun goto out;
1132*4882a593Smuzhiyun bio = req->bio;
1133*4882a593Smuzhiyun bio->bi_disk = disk;
1134*4882a593Smuzhiyun if (disk && meta_buffer && meta_len) {
1135*4882a593Smuzhiyun meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
1136*4882a593Smuzhiyun meta_seed, write);
1137*4882a593Smuzhiyun if (IS_ERR(meta)) {
1138*4882a593Smuzhiyun ret = PTR_ERR(meta);
1139*4882a593Smuzhiyun goto out_unmap;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun req->cmd_flags |= REQ_INTEGRITY;
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun nvme_execute_passthru_rq(req);
1146*4882a593Smuzhiyun if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
1147*4882a593Smuzhiyun ret = -EINTR;
1148*4882a593Smuzhiyun else
1149*4882a593Smuzhiyun ret = nvme_req(req)->status;
1150*4882a593Smuzhiyun if (result)
1151*4882a593Smuzhiyun *result = le64_to_cpu(nvme_req(req)->result.u64);
1152*4882a593Smuzhiyun if (meta && !ret && !write) {
1153*4882a593Smuzhiyun if (copy_to_user(meta_buffer, meta, meta_len))
1154*4882a593Smuzhiyun ret = -EFAULT;
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun kfree(meta);
1157*4882a593Smuzhiyun out_unmap:
1158*4882a593Smuzhiyun if (bio)
1159*4882a593Smuzhiyun blk_rq_unmap_user(bio);
1160*4882a593Smuzhiyun out:
1161*4882a593Smuzhiyun blk_mq_free_request(req);
1162*4882a593Smuzhiyun return ret;
1163*4882a593Smuzhiyun }
1164*4882a593Smuzhiyun
nvme_keep_alive_end_io(struct request * rq,blk_status_t status)1165*4882a593Smuzhiyun static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
1166*4882a593Smuzhiyun {
1167*4882a593Smuzhiyun struct nvme_ctrl *ctrl = rq->end_io_data;
1168*4882a593Smuzhiyun unsigned long flags;
1169*4882a593Smuzhiyun bool startka = false;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun blk_mq_free_request(rq);
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun if (status) {
1174*4882a593Smuzhiyun dev_err(ctrl->device,
1175*4882a593Smuzhiyun "failed nvme_keep_alive_end_io error=%d\n",
1176*4882a593Smuzhiyun status);
1177*4882a593Smuzhiyun return;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun ctrl->comp_seen = false;
1181*4882a593Smuzhiyun spin_lock_irqsave(&ctrl->lock, flags);
1182*4882a593Smuzhiyun if (ctrl->state == NVME_CTRL_LIVE ||
1183*4882a593Smuzhiyun ctrl->state == NVME_CTRL_CONNECTING)
1184*4882a593Smuzhiyun startka = true;
1185*4882a593Smuzhiyun spin_unlock_irqrestore(&ctrl->lock, flags);
1186*4882a593Smuzhiyun if (startka)
1187*4882a593Smuzhiyun queue_delayed_work(nvme_wq, &ctrl->ka_work, ctrl->kato * HZ);
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun
nvme_keep_alive(struct nvme_ctrl * ctrl)1190*4882a593Smuzhiyun static int nvme_keep_alive(struct nvme_ctrl *ctrl)
1191*4882a593Smuzhiyun {
1192*4882a593Smuzhiyun struct request *rq;
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd,
1195*4882a593Smuzhiyun BLK_MQ_REQ_RESERVED);
1196*4882a593Smuzhiyun if (IS_ERR(rq))
1197*4882a593Smuzhiyun return PTR_ERR(rq);
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun rq->timeout = ctrl->kato * HZ;
1200*4882a593Smuzhiyun rq->end_io_data = ctrl;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun return 0;
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
nvme_keep_alive_work(struct work_struct * work)1207*4882a593Smuzhiyun static void nvme_keep_alive_work(struct work_struct *work)
1208*4882a593Smuzhiyun {
1209*4882a593Smuzhiyun struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1210*4882a593Smuzhiyun struct nvme_ctrl, ka_work);
1211*4882a593Smuzhiyun bool comp_seen = ctrl->comp_seen;
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1214*4882a593Smuzhiyun dev_dbg(ctrl->device,
1215*4882a593Smuzhiyun "reschedule traffic based keep-alive timer\n");
1216*4882a593Smuzhiyun ctrl->comp_seen = false;
1217*4882a593Smuzhiyun queue_delayed_work(nvme_wq, &ctrl->ka_work, ctrl->kato * HZ);
1218*4882a593Smuzhiyun return;
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun if (nvme_keep_alive(ctrl)) {
1222*4882a593Smuzhiyun /* allocation failure, reset the controller */
1223*4882a593Smuzhiyun dev_err(ctrl->device, "keep-alive failed\n");
1224*4882a593Smuzhiyun nvme_reset_ctrl(ctrl);
1225*4882a593Smuzhiyun return;
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun
nvme_start_keep_alive(struct nvme_ctrl * ctrl)1229*4882a593Smuzhiyun static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
1230*4882a593Smuzhiyun {
1231*4882a593Smuzhiyun if (unlikely(ctrl->kato == 0))
1232*4882a593Smuzhiyun return;
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun queue_delayed_work(nvme_wq, &ctrl->ka_work, ctrl->kato * HZ);
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
nvme_stop_keep_alive(struct nvme_ctrl * ctrl)1237*4882a593Smuzhiyun void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun if (unlikely(ctrl->kato == 0))
1240*4882a593Smuzhiyun return;
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun cancel_delayed_work_sync(&ctrl->ka_work);
1243*4882a593Smuzhiyun }
1244*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun /*
1247*4882a593Smuzhiyun * In NVMe 1.0 the CNS field was just a binary controller or namespace
1248*4882a593Smuzhiyun * flag, thus sending any new CNS opcodes has a big chance of not working.
1249*4882a593Smuzhiyun * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1250*4882a593Smuzhiyun * (but not for any later version).
1251*4882a593Smuzhiyun */
nvme_ctrl_limited_cns(struct nvme_ctrl * ctrl)1252*4882a593Smuzhiyun static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1255*4882a593Smuzhiyun return ctrl->vs < NVME_VS(1, 2, 0);
1256*4882a593Smuzhiyun return ctrl->vs < NVME_VS(1, 1, 0);
1257*4882a593Smuzhiyun }
1258*4882a593Smuzhiyun
nvme_identify_ctrl(struct nvme_ctrl * dev,struct nvme_id_ctrl ** id)1259*4882a593Smuzhiyun static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
1260*4882a593Smuzhiyun {
1261*4882a593Smuzhiyun struct nvme_command c = { };
1262*4882a593Smuzhiyun int error;
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1265*4882a593Smuzhiyun c.identify.opcode = nvme_admin_identify;
1266*4882a593Smuzhiyun c.identify.cns = NVME_ID_CNS_CTRL;
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1269*4882a593Smuzhiyun if (!*id)
1270*4882a593Smuzhiyun return -ENOMEM;
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1273*4882a593Smuzhiyun sizeof(struct nvme_id_ctrl));
1274*4882a593Smuzhiyun if (error)
1275*4882a593Smuzhiyun kfree(*id);
1276*4882a593Smuzhiyun return error;
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
nvme_multi_css(struct nvme_ctrl * ctrl)1279*4882a593Smuzhiyun static bool nvme_multi_css(struct nvme_ctrl *ctrl)
1280*4882a593Smuzhiyun {
1281*4882a593Smuzhiyun return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI;
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun
nvme_process_ns_desc(struct nvme_ctrl * ctrl,struct nvme_ns_ids * ids,struct nvme_ns_id_desc * cur,bool * csi_seen)1284*4882a593Smuzhiyun static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
1285*4882a593Smuzhiyun struct nvme_ns_id_desc *cur, bool *csi_seen)
1286*4882a593Smuzhiyun {
1287*4882a593Smuzhiyun const char *warn_str = "ctrl returned bogus length:";
1288*4882a593Smuzhiyun void *data = cur;
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun switch (cur->nidt) {
1291*4882a593Smuzhiyun case NVME_NIDT_EUI64:
1292*4882a593Smuzhiyun if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1293*4882a593Smuzhiyun dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1294*4882a593Smuzhiyun warn_str, cur->nidl);
1295*4882a593Smuzhiyun return -1;
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1298*4882a593Smuzhiyun return NVME_NIDT_EUI64_LEN;
1299*4882a593Smuzhiyun memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1300*4882a593Smuzhiyun return NVME_NIDT_EUI64_LEN;
1301*4882a593Smuzhiyun case NVME_NIDT_NGUID:
1302*4882a593Smuzhiyun if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1303*4882a593Smuzhiyun dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1304*4882a593Smuzhiyun warn_str, cur->nidl);
1305*4882a593Smuzhiyun return -1;
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1308*4882a593Smuzhiyun return NVME_NIDT_NGUID_LEN;
1309*4882a593Smuzhiyun memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1310*4882a593Smuzhiyun return NVME_NIDT_NGUID_LEN;
1311*4882a593Smuzhiyun case NVME_NIDT_UUID:
1312*4882a593Smuzhiyun if (cur->nidl != NVME_NIDT_UUID_LEN) {
1313*4882a593Smuzhiyun dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1314*4882a593Smuzhiyun warn_str, cur->nidl);
1315*4882a593Smuzhiyun return -1;
1316*4882a593Smuzhiyun }
1317*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1318*4882a593Smuzhiyun return NVME_NIDT_UUID_LEN;
1319*4882a593Smuzhiyun uuid_copy(&ids->uuid, data + sizeof(*cur));
1320*4882a593Smuzhiyun return NVME_NIDT_UUID_LEN;
1321*4882a593Smuzhiyun case NVME_NIDT_CSI:
1322*4882a593Smuzhiyun if (cur->nidl != NVME_NIDT_CSI_LEN) {
1323*4882a593Smuzhiyun dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1324*4882a593Smuzhiyun warn_str, cur->nidl);
1325*4882a593Smuzhiyun return -1;
1326*4882a593Smuzhiyun }
1327*4882a593Smuzhiyun memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1328*4882a593Smuzhiyun *csi_seen = true;
1329*4882a593Smuzhiyun return NVME_NIDT_CSI_LEN;
1330*4882a593Smuzhiyun default:
1331*4882a593Smuzhiyun /* Skip unknown types */
1332*4882a593Smuzhiyun return cur->nidl;
1333*4882a593Smuzhiyun }
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun
nvme_identify_ns_descs(struct nvme_ctrl * ctrl,unsigned nsid,struct nvme_ns_ids * ids)1336*4882a593Smuzhiyun static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
1337*4882a593Smuzhiyun struct nvme_ns_ids *ids)
1338*4882a593Smuzhiyun {
1339*4882a593Smuzhiyun struct nvme_command c = { };
1340*4882a593Smuzhiyun bool csi_seen = false;
1341*4882a593Smuzhiyun int status, pos, len;
1342*4882a593Smuzhiyun void *data;
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1345*4882a593Smuzhiyun return 0;
1346*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1347*4882a593Smuzhiyun return 0;
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun c.identify.opcode = nvme_admin_identify;
1350*4882a593Smuzhiyun c.identify.nsid = cpu_to_le32(nsid);
1351*4882a593Smuzhiyun c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1354*4882a593Smuzhiyun if (!data)
1355*4882a593Smuzhiyun return -ENOMEM;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
1358*4882a593Smuzhiyun NVME_IDENTIFY_DATA_SIZE);
1359*4882a593Smuzhiyun if (status) {
1360*4882a593Smuzhiyun dev_warn(ctrl->device,
1361*4882a593Smuzhiyun "Identify Descriptors failed (%d)\n", status);
1362*4882a593Smuzhiyun goto free_data;
1363*4882a593Smuzhiyun }
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1366*4882a593Smuzhiyun struct nvme_ns_id_desc *cur = data + pos;
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun if (cur->nidl == 0)
1369*4882a593Smuzhiyun break;
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun len = nvme_process_ns_desc(ctrl, ids, cur, &csi_seen);
1372*4882a593Smuzhiyun if (len < 0)
1373*4882a593Smuzhiyun break;
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun len += sizeof(*cur);
1376*4882a593Smuzhiyun }
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun if (nvme_multi_css(ctrl) && !csi_seen) {
1379*4882a593Smuzhiyun dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1380*4882a593Smuzhiyun nsid);
1381*4882a593Smuzhiyun status = -EINVAL;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun free_data:
1385*4882a593Smuzhiyun kfree(data);
1386*4882a593Smuzhiyun return status;
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun
nvme_identify_ns(struct nvme_ctrl * ctrl,unsigned nsid,struct nvme_ns_ids * ids,struct nvme_id_ns ** id)1389*4882a593Smuzhiyun static int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1390*4882a593Smuzhiyun struct nvme_ns_ids *ids, struct nvme_id_ns **id)
1391*4882a593Smuzhiyun {
1392*4882a593Smuzhiyun struct nvme_command c = { };
1393*4882a593Smuzhiyun int error;
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1396*4882a593Smuzhiyun c.identify.opcode = nvme_admin_identify;
1397*4882a593Smuzhiyun c.identify.nsid = cpu_to_le32(nsid);
1398*4882a593Smuzhiyun c.identify.cns = NVME_ID_CNS_NS;
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun *id = kmalloc(sizeof(**id), GFP_KERNEL);
1401*4882a593Smuzhiyun if (!*id)
1402*4882a593Smuzhiyun return -ENOMEM;
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
1405*4882a593Smuzhiyun if (error) {
1406*4882a593Smuzhiyun dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
1407*4882a593Smuzhiyun goto out_free_id;
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun error = NVME_SC_INVALID_NS | NVME_SC_DNR;
1411*4882a593Smuzhiyun if ((*id)->ncap == 0) /* namespace not allocated or attached */
1412*4882a593Smuzhiyun goto out_free_id;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) {
1416*4882a593Smuzhiyun dev_info(ctrl->device,
1417*4882a593Smuzhiyun "Ignoring bogus Namespace Identifiers\n");
1418*4882a593Smuzhiyun } else {
1419*4882a593Smuzhiyun if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1420*4882a593Smuzhiyun !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1421*4882a593Smuzhiyun memcpy(ids->eui64, (*id)->eui64, sizeof(ids->eui64));
1422*4882a593Smuzhiyun if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1423*4882a593Smuzhiyun !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1424*4882a593Smuzhiyun memcpy(ids->nguid, (*id)->nguid, sizeof(ids->nguid));
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun return 0;
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun out_free_id:
1430*4882a593Smuzhiyun kfree(*id);
1431*4882a593Smuzhiyun return error;
1432*4882a593Smuzhiyun }
1433*4882a593Smuzhiyun
nvme_features(struct nvme_ctrl * dev,u8 op,unsigned int fid,unsigned int dword11,void * buffer,size_t buflen,u32 * result)1434*4882a593Smuzhiyun static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1435*4882a593Smuzhiyun unsigned int dword11, void *buffer, size_t buflen, u32 *result)
1436*4882a593Smuzhiyun {
1437*4882a593Smuzhiyun union nvme_result res = { 0 };
1438*4882a593Smuzhiyun struct nvme_command c;
1439*4882a593Smuzhiyun int ret;
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
1442*4882a593Smuzhiyun c.features.opcode = op;
1443*4882a593Smuzhiyun c.features.fid = cpu_to_le32(fid);
1444*4882a593Smuzhiyun c.features.dword11 = cpu_to_le32(dword11);
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1447*4882a593Smuzhiyun buffer, buflen, 0, NVME_QID_ANY, 0, 0, false);
1448*4882a593Smuzhiyun if (ret >= 0 && result)
1449*4882a593Smuzhiyun *result = le32_to_cpu(res.u32);
1450*4882a593Smuzhiyun return ret;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun
nvme_set_features(struct nvme_ctrl * dev,unsigned int fid,unsigned int dword11,void * buffer,size_t buflen,u32 * result)1453*4882a593Smuzhiyun int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1454*4882a593Smuzhiyun unsigned int dword11, void *buffer, size_t buflen,
1455*4882a593Smuzhiyun u32 *result)
1456*4882a593Smuzhiyun {
1457*4882a593Smuzhiyun return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1458*4882a593Smuzhiyun buflen, result);
1459*4882a593Smuzhiyun }
1460*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_set_features);
1461*4882a593Smuzhiyun
nvme_get_features(struct nvme_ctrl * dev,unsigned int fid,unsigned int dword11,void * buffer,size_t buflen,u32 * result)1462*4882a593Smuzhiyun int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1463*4882a593Smuzhiyun unsigned int dword11, void *buffer, size_t buflen,
1464*4882a593Smuzhiyun u32 *result)
1465*4882a593Smuzhiyun {
1466*4882a593Smuzhiyun return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1467*4882a593Smuzhiyun buflen, result);
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_get_features);
1470*4882a593Smuzhiyun
nvme_set_queue_count(struct nvme_ctrl * ctrl,int * count)1471*4882a593Smuzhiyun int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1472*4882a593Smuzhiyun {
1473*4882a593Smuzhiyun u32 q_count = (*count - 1) | ((*count - 1) << 16);
1474*4882a593Smuzhiyun u32 result;
1475*4882a593Smuzhiyun int status, nr_io_queues;
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
1478*4882a593Smuzhiyun &result);
1479*4882a593Smuzhiyun if (status < 0)
1480*4882a593Smuzhiyun return status;
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun /*
1483*4882a593Smuzhiyun * Degraded controllers might return an error when setting the queue
1484*4882a593Smuzhiyun * count. We still want to be able to bring them online and offer
1485*4882a593Smuzhiyun * access to the admin queue, as that might be only way to fix them up.
1486*4882a593Smuzhiyun */
1487*4882a593Smuzhiyun if (status > 0) {
1488*4882a593Smuzhiyun dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
1489*4882a593Smuzhiyun *count = 0;
1490*4882a593Smuzhiyun } else {
1491*4882a593Smuzhiyun nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1492*4882a593Smuzhiyun *count = min(*count, nr_io_queues);
1493*4882a593Smuzhiyun }
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun return 0;
1496*4882a593Smuzhiyun }
1497*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_set_queue_count);
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun #define NVME_AEN_SUPPORTED \
1500*4882a593Smuzhiyun (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1501*4882a593Smuzhiyun NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
1502*4882a593Smuzhiyun
nvme_enable_aen(struct nvme_ctrl * ctrl)1503*4882a593Smuzhiyun static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1504*4882a593Smuzhiyun {
1505*4882a593Smuzhiyun u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
1506*4882a593Smuzhiyun int status;
1507*4882a593Smuzhiyun
1508*4882a593Smuzhiyun if (!supported_aens)
1509*4882a593Smuzhiyun return;
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1512*4882a593Smuzhiyun NULL, 0, &result);
1513*4882a593Smuzhiyun if (status)
1514*4882a593Smuzhiyun dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
1515*4882a593Smuzhiyun supported_aens);
1516*4882a593Smuzhiyun
1517*4882a593Smuzhiyun queue_work(nvme_wq, &ctrl->async_event_work);
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun /*
1521*4882a593Smuzhiyun * Convert integer values from ioctl structures to user pointers, silently
1522*4882a593Smuzhiyun * ignoring the upper bits in the compat case to match behaviour of 32-bit
1523*4882a593Smuzhiyun * kernels.
1524*4882a593Smuzhiyun */
nvme_to_user_ptr(uintptr_t ptrval)1525*4882a593Smuzhiyun static void __user *nvme_to_user_ptr(uintptr_t ptrval)
1526*4882a593Smuzhiyun {
1527*4882a593Smuzhiyun if (in_compat_syscall())
1528*4882a593Smuzhiyun ptrval = (compat_uptr_t)ptrval;
1529*4882a593Smuzhiyun return (void __user *)ptrval;
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun
nvme_submit_io(struct nvme_ns * ns,struct nvme_user_io __user * uio)1532*4882a593Smuzhiyun static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1533*4882a593Smuzhiyun {
1534*4882a593Smuzhiyun struct nvme_user_io io;
1535*4882a593Smuzhiyun struct nvme_command c;
1536*4882a593Smuzhiyun unsigned length, meta_len;
1537*4882a593Smuzhiyun void __user *metadata;
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun if (copy_from_user(&io, uio, sizeof(io)))
1540*4882a593Smuzhiyun return -EFAULT;
1541*4882a593Smuzhiyun if (io.flags)
1542*4882a593Smuzhiyun return -EINVAL;
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun switch (io.opcode) {
1545*4882a593Smuzhiyun case nvme_cmd_write:
1546*4882a593Smuzhiyun case nvme_cmd_read:
1547*4882a593Smuzhiyun case nvme_cmd_compare:
1548*4882a593Smuzhiyun break;
1549*4882a593Smuzhiyun default:
1550*4882a593Smuzhiyun return -EINVAL;
1551*4882a593Smuzhiyun }
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun length = (io.nblocks + 1) << ns->lba_shift;
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun if ((io.control & NVME_RW_PRINFO_PRACT) &&
1556*4882a593Smuzhiyun ns->ms == sizeof(struct t10_pi_tuple)) {
1557*4882a593Smuzhiyun /*
1558*4882a593Smuzhiyun * Protection information is stripped/inserted by the
1559*4882a593Smuzhiyun * controller.
1560*4882a593Smuzhiyun */
1561*4882a593Smuzhiyun if (nvme_to_user_ptr(io.metadata))
1562*4882a593Smuzhiyun return -EINVAL;
1563*4882a593Smuzhiyun meta_len = 0;
1564*4882a593Smuzhiyun metadata = NULL;
1565*4882a593Smuzhiyun } else {
1566*4882a593Smuzhiyun meta_len = (io.nblocks + 1) * ns->ms;
1567*4882a593Smuzhiyun metadata = nvme_to_user_ptr(io.metadata);
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun if (ns->features & NVME_NS_EXT_LBAS) {
1571*4882a593Smuzhiyun length += meta_len;
1572*4882a593Smuzhiyun meta_len = 0;
1573*4882a593Smuzhiyun } else if (meta_len) {
1574*4882a593Smuzhiyun if ((io.metadata & 3) || !io.metadata)
1575*4882a593Smuzhiyun return -EINVAL;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
1579*4882a593Smuzhiyun c.rw.opcode = io.opcode;
1580*4882a593Smuzhiyun c.rw.flags = io.flags;
1581*4882a593Smuzhiyun c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1582*4882a593Smuzhiyun c.rw.slba = cpu_to_le64(io.slba);
1583*4882a593Smuzhiyun c.rw.length = cpu_to_le16(io.nblocks);
1584*4882a593Smuzhiyun c.rw.control = cpu_to_le16(io.control);
1585*4882a593Smuzhiyun c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1586*4882a593Smuzhiyun c.rw.reftag = cpu_to_le32(io.reftag);
1587*4882a593Smuzhiyun c.rw.apptag = cpu_to_le16(io.apptag);
1588*4882a593Smuzhiyun c.rw.appmask = cpu_to_le16(io.appmask);
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun return nvme_submit_user_cmd(ns->queue, &c,
1591*4882a593Smuzhiyun nvme_to_user_ptr(io.addr), length,
1592*4882a593Smuzhiyun metadata, meta_len, lower_32_bits(io.slba), NULL, 0);
1593*4882a593Smuzhiyun }
1594*4882a593Smuzhiyun
nvme_user_cmd(struct nvme_ctrl * ctrl,struct nvme_ns * ns,struct nvme_passthru_cmd __user * ucmd)1595*4882a593Smuzhiyun static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1596*4882a593Smuzhiyun struct nvme_passthru_cmd __user *ucmd)
1597*4882a593Smuzhiyun {
1598*4882a593Smuzhiyun struct nvme_passthru_cmd cmd;
1599*4882a593Smuzhiyun struct nvme_command c;
1600*4882a593Smuzhiyun unsigned timeout = 0;
1601*4882a593Smuzhiyun u64 result;
1602*4882a593Smuzhiyun int status;
1603*4882a593Smuzhiyun
1604*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
1605*4882a593Smuzhiyun return -EACCES;
1606*4882a593Smuzhiyun if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1607*4882a593Smuzhiyun return -EFAULT;
1608*4882a593Smuzhiyun if (cmd.flags)
1609*4882a593Smuzhiyun return -EINVAL;
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
1612*4882a593Smuzhiyun c.common.opcode = cmd.opcode;
1613*4882a593Smuzhiyun c.common.flags = cmd.flags;
1614*4882a593Smuzhiyun c.common.nsid = cpu_to_le32(cmd.nsid);
1615*4882a593Smuzhiyun c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1616*4882a593Smuzhiyun c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1617*4882a593Smuzhiyun c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1618*4882a593Smuzhiyun c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1619*4882a593Smuzhiyun c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1620*4882a593Smuzhiyun c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1621*4882a593Smuzhiyun c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1622*4882a593Smuzhiyun c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun if (cmd.timeout_ms)
1625*4882a593Smuzhiyun timeout = msecs_to_jiffies(cmd.timeout_ms);
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
1628*4882a593Smuzhiyun nvme_to_user_ptr(cmd.addr), cmd.data_len,
1629*4882a593Smuzhiyun nvme_to_user_ptr(cmd.metadata), cmd.metadata_len,
1630*4882a593Smuzhiyun 0, &result, timeout);
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun if (status >= 0) {
1633*4882a593Smuzhiyun if (put_user(result, &ucmd->result))
1634*4882a593Smuzhiyun return -EFAULT;
1635*4882a593Smuzhiyun }
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun return status;
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun
nvme_user_cmd64(struct nvme_ctrl * ctrl,struct nvme_ns * ns,struct nvme_passthru_cmd64 __user * ucmd)1640*4882a593Smuzhiyun static int nvme_user_cmd64(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1641*4882a593Smuzhiyun struct nvme_passthru_cmd64 __user *ucmd)
1642*4882a593Smuzhiyun {
1643*4882a593Smuzhiyun struct nvme_passthru_cmd64 cmd;
1644*4882a593Smuzhiyun struct nvme_command c;
1645*4882a593Smuzhiyun unsigned timeout = 0;
1646*4882a593Smuzhiyun int status;
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
1649*4882a593Smuzhiyun return -EACCES;
1650*4882a593Smuzhiyun if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1651*4882a593Smuzhiyun return -EFAULT;
1652*4882a593Smuzhiyun if (cmd.flags)
1653*4882a593Smuzhiyun return -EINVAL;
1654*4882a593Smuzhiyun
1655*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
1656*4882a593Smuzhiyun c.common.opcode = cmd.opcode;
1657*4882a593Smuzhiyun c.common.flags = cmd.flags;
1658*4882a593Smuzhiyun c.common.nsid = cpu_to_le32(cmd.nsid);
1659*4882a593Smuzhiyun c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1660*4882a593Smuzhiyun c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1661*4882a593Smuzhiyun c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1662*4882a593Smuzhiyun c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1663*4882a593Smuzhiyun c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1664*4882a593Smuzhiyun c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1665*4882a593Smuzhiyun c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1666*4882a593Smuzhiyun c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun if (cmd.timeout_ms)
1669*4882a593Smuzhiyun timeout = msecs_to_jiffies(cmd.timeout_ms);
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
1672*4882a593Smuzhiyun nvme_to_user_ptr(cmd.addr), cmd.data_len,
1673*4882a593Smuzhiyun nvme_to_user_ptr(cmd.metadata), cmd.metadata_len,
1674*4882a593Smuzhiyun 0, &cmd.result, timeout);
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun if (status >= 0) {
1677*4882a593Smuzhiyun if (put_user(cmd.result, &ucmd->result))
1678*4882a593Smuzhiyun return -EFAULT;
1679*4882a593Smuzhiyun }
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun return status;
1682*4882a593Smuzhiyun }
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun /*
1685*4882a593Smuzhiyun * Issue ioctl requests on the first available path. Note that unlike normal
1686*4882a593Smuzhiyun * block layer requests we will not retry failed request on another controller.
1687*4882a593Smuzhiyun */
nvme_get_ns_from_disk(struct gendisk * disk,struct nvme_ns_head ** head,int * srcu_idx)1688*4882a593Smuzhiyun struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1689*4882a593Smuzhiyun struct nvme_ns_head **head, int *srcu_idx)
1690*4882a593Smuzhiyun {
1691*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
1692*4882a593Smuzhiyun if (disk->fops == &nvme_ns_head_ops) {
1693*4882a593Smuzhiyun struct nvme_ns *ns;
1694*4882a593Smuzhiyun
1695*4882a593Smuzhiyun *head = disk->private_data;
1696*4882a593Smuzhiyun *srcu_idx = srcu_read_lock(&(*head)->srcu);
1697*4882a593Smuzhiyun ns = nvme_find_path(*head);
1698*4882a593Smuzhiyun if (!ns)
1699*4882a593Smuzhiyun srcu_read_unlock(&(*head)->srcu, *srcu_idx);
1700*4882a593Smuzhiyun return ns;
1701*4882a593Smuzhiyun }
1702*4882a593Smuzhiyun #endif
1703*4882a593Smuzhiyun *head = NULL;
1704*4882a593Smuzhiyun *srcu_idx = -1;
1705*4882a593Smuzhiyun return disk->private_data;
1706*4882a593Smuzhiyun }
1707*4882a593Smuzhiyun
nvme_put_ns_from_disk(struct nvme_ns_head * head,int idx)1708*4882a593Smuzhiyun void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1709*4882a593Smuzhiyun {
1710*4882a593Smuzhiyun if (head)
1711*4882a593Smuzhiyun srcu_read_unlock(&head->srcu, idx);
1712*4882a593Smuzhiyun }
1713*4882a593Smuzhiyun
is_ctrl_ioctl(unsigned int cmd)1714*4882a593Smuzhiyun static bool is_ctrl_ioctl(unsigned int cmd)
1715*4882a593Smuzhiyun {
1716*4882a593Smuzhiyun if (cmd == NVME_IOCTL_ADMIN_CMD || cmd == NVME_IOCTL_ADMIN64_CMD)
1717*4882a593Smuzhiyun return true;
1718*4882a593Smuzhiyun if (is_sed_ioctl(cmd))
1719*4882a593Smuzhiyun return true;
1720*4882a593Smuzhiyun return false;
1721*4882a593Smuzhiyun }
1722*4882a593Smuzhiyun
nvme_handle_ctrl_ioctl(struct nvme_ns * ns,unsigned int cmd,void __user * argp,struct nvme_ns_head * head,int srcu_idx)1723*4882a593Smuzhiyun static int nvme_handle_ctrl_ioctl(struct nvme_ns *ns, unsigned int cmd,
1724*4882a593Smuzhiyun void __user *argp,
1725*4882a593Smuzhiyun struct nvme_ns_head *head,
1726*4882a593Smuzhiyun int srcu_idx)
1727*4882a593Smuzhiyun {
1728*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
1729*4882a593Smuzhiyun int ret;
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun nvme_get_ctrl(ns->ctrl);
1732*4882a593Smuzhiyun nvme_put_ns_from_disk(head, srcu_idx);
1733*4882a593Smuzhiyun
1734*4882a593Smuzhiyun switch (cmd) {
1735*4882a593Smuzhiyun case NVME_IOCTL_ADMIN_CMD:
1736*4882a593Smuzhiyun ret = nvme_user_cmd(ctrl, NULL, argp);
1737*4882a593Smuzhiyun break;
1738*4882a593Smuzhiyun case NVME_IOCTL_ADMIN64_CMD:
1739*4882a593Smuzhiyun ret = nvme_user_cmd64(ctrl, NULL, argp);
1740*4882a593Smuzhiyun break;
1741*4882a593Smuzhiyun default:
1742*4882a593Smuzhiyun ret = sed_ioctl(ctrl->opal_dev, cmd, argp);
1743*4882a593Smuzhiyun break;
1744*4882a593Smuzhiyun }
1745*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
1746*4882a593Smuzhiyun return ret;
1747*4882a593Smuzhiyun }
1748*4882a593Smuzhiyun
nvme_ioctl(struct block_device * bdev,fmode_t mode,unsigned int cmd,unsigned long arg)1749*4882a593Smuzhiyun static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1750*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1751*4882a593Smuzhiyun {
1752*4882a593Smuzhiyun struct nvme_ns_head *head = NULL;
1753*4882a593Smuzhiyun void __user *argp = (void __user *)arg;
1754*4882a593Smuzhiyun struct nvme_ns *ns;
1755*4882a593Smuzhiyun int srcu_idx, ret;
1756*4882a593Smuzhiyun
1757*4882a593Smuzhiyun ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1758*4882a593Smuzhiyun if (unlikely(!ns))
1759*4882a593Smuzhiyun return -EWOULDBLOCK;
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun /*
1762*4882a593Smuzhiyun * Handle ioctls that apply to the controller instead of the namespace
1763*4882a593Smuzhiyun * seperately and drop the ns SRCU reference early. This avoids a
1764*4882a593Smuzhiyun * deadlock when deleting namespaces using the passthrough interface.
1765*4882a593Smuzhiyun */
1766*4882a593Smuzhiyun if (is_ctrl_ioctl(cmd))
1767*4882a593Smuzhiyun return nvme_handle_ctrl_ioctl(ns, cmd, argp, head, srcu_idx);
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun switch (cmd) {
1770*4882a593Smuzhiyun case NVME_IOCTL_ID:
1771*4882a593Smuzhiyun force_successful_syscall_return();
1772*4882a593Smuzhiyun ret = ns->head->ns_id;
1773*4882a593Smuzhiyun break;
1774*4882a593Smuzhiyun case NVME_IOCTL_IO_CMD:
1775*4882a593Smuzhiyun ret = nvme_user_cmd(ns->ctrl, ns, argp);
1776*4882a593Smuzhiyun break;
1777*4882a593Smuzhiyun case NVME_IOCTL_SUBMIT_IO:
1778*4882a593Smuzhiyun ret = nvme_submit_io(ns, argp);
1779*4882a593Smuzhiyun break;
1780*4882a593Smuzhiyun case NVME_IOCTL_IO64_CMD:
1781*4882a593Smuzhiyun ret = nvme_user_cmd64(ns->ctrl, ns, argp);
1782*4882a593Smuzhiyun break;
1783*4882a593Smuzhiyun default:
1784*4882a593Smuzhiyun if (ns->ndev)
1785*4882a593Smuzhiyun ret = nvme_nvm_ioctl(ns, cmd, arg);
1786*4882a593Smuzhiyun else
1787*4882a593Smuzhiyun ret = -ENOTTY;
1788*4882a593Smuzhiyun }
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun nvme_put_ns_from_disk(head, srcu_idx);
1791*4882a593Smuzhiyun return ret;
1792*4882a593Smuzhiyun }
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1795*4882a593Smuzhiyun struct nvme_user_io32 {
1796*4882a593Smuzhiyun __u8 opcode;
1797*4882a593Smuzhiyun __u8 flags;
1798*4882a593Smuzhiyun __u16 control;
1799*4882a593Smuzhiyun __u16 nblocks;
1800*4882a593Smuzhiyun __u16 rsvd;
1801*4882a593Smuzhiyun __u64 metadata;
1802*4882a593Smuzhiyun __u64 addr;
1803*4882a593Smuzhiyun __u64 slba;
1804*4882a593Smuzhiyun __u32 dsmgmt;
1805*4882a593Smuzhiyun __u32 reftag;
1806*4882a593Smuzhiyun __u16 apptag;
1807*4882a593Smuzhiyun __u16 appmask;
1808*4882a593Smuzhiyun } __attribute__((__packed__));
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun #define NVME_IOCTL_SUBMIT_IO32 _IOW('N', 0x42, struct nvme_user_io32)
1811*4882a593Smuzhiyun
nvme_compat_ioctl(struct block_device * bdev,fmode_t mode,unsigned int cmd,unsigned long arg)1812*4882a593Smuzhiyun static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1813*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1814*4882a593Smuzhiyun {
1815*4882a593Smuzhiyun /*
1816*4882a593Smuzhiyun * Corresponds to the difference of NVME_IOCTL_SUBMIT_IO
1817*4882a593Smuzhiyun * between 32 bit programs and 64 bit kernel.
1818*4882a593Smuzhiyun * The cause is that the results of sizeof(struct nvme_user_io),
1819*4882a593Smuzhiyun * which is used to define NVME_IOCTL_SUBMIT_IO,
1820*4882a593Smuzhiyun * are not same between 32 bit compiler and 64 bit compiler.
1821*4882a593Smuzhiyun * NVME_IOCTL_SUBMIT_IO32 is for 64 bit kernel handling
1822*4882a593Smuzhiyun * NVME_IOCTL_SUBMIT_IO issued from 32 bit programs.
1823*4882a593Smuzhiyun * Other IOCTL numbers are same between 32 bit and 64 bit.
1824*4882a593Smuzhiyun * So there is nothing to do regarding to other IOCTL numbers.
1825*4882a593Smuzhiyun */
1826*4882a593Smuzhiyun if (cmd == NVME_IOCTL_SUBMIT_IO32)
1827*4882a593Smuzhiyun return nvme_ioctl(bdev, mode, NVME_IOCTL_SUBMIT_IO, arg);
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun return nvme_ioctl(bdev, mode, cmd, arg);
1830*4882a593Smuzhiyun }
1831*4882a593Smuzhiyun #else
1832*4882a593Smuzhiyun #define nvme_compat_ioctl NULL
1833*4882a593Smuzhiyun #endif /* CONFIG_COMPAT */
1834*4882a593Smuzhiyun
nvme_open(struct block_device * bdev,fmode_t mode)1835*4882a593Smuzhiyun static int nvme_open(struct block_device *bdev, fmode_t mode)
1836*4882a593Smuzhiyun {
1837*4882a593Smuzhiyun struct nvme_ns *ns = bdev->bd_disk->private_data;
1838*4882a593Smuzhiyun
1839*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
1840*4882a593Smuzhiyun /* should never be called due to GENHD_FL_HIDDEN */
1841*4882a593Smuzhiyun if (WARN_ON_ONCE(ns->head->disk))
1842*4882a593Smuzhiyun goto fail;
1843*4882a593Smuzhiyun #endif
1844*4882a593Smuzhiyun if (!kref_get_unless_zero(&ns->kref))
1845*4882a593Smuzhiyun goto fail;
1846*4882a593Smuzhiyun if (!try_module_get(ns->ctrl->ops->module))
1847*4882a593Smuzhiyun goto fail_put_ns;
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun return 0;
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun fail_put_ns:
1852*4882a593Smuzhiyun nvme_put_ns(ns);
1853*4882a593Smuzhiyun fail:
1854*4882a593Smuzhiyun return -ENXIO;
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun
nvme_release(struct gendisk * disk,fmode_t mode)1857*4882a593Smuzhiyun static void nvme_release(struct gendisk *disk, fmode_t mode)
1858*4882a593Smuzhiyun {
1859*4882a593Smuzhiyun struct nvme_ns *ns = disk->private_data;
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun module_put(ns->ctrl->ops->module);
1862*4882a593Smuzhiyun nvme_put_ns(ns);
1863*4882a593Smuzhiyun }
1864*4882a593Smuzhiyun
nvme_getgeo(struct block_device * bdev,struct hd_geometry * geo)1865*4882a593Smuzhiyun static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1866*4882a593Smuzhiyun {
1867*4882a593Smuzhiyun /* some standard values */
1868*4882a593Smuzhiyun geo->heads = 1 << 6;
1869*4882a593Smuzhiyun geo->sectors = 1 << 5;
1870*4882a593Smuzhiyun geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1871*4882a593Smuzhiyun return 0;
1872*4882a593Smuzhiyun }
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun #ifdef CONFIG_BLK_DEV_INTEGRITY
nvme_init_integrity(struct gendisk * disk,u16 ms,u8 pi_type,u32 max_integrity_segments)1875*4882a593Smuzhiyun static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type,
1876*4882a593Smuzhiyun u32 max_integrity_segments)
1877*4882a593Smuzhiyun {
1878*4882a593Smuzhiyun struct blk_integrity integrity;
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun memset(&integrity, 0, sizeof(integrity));
1881*4882a593Smuzhiyun switch (pi_type) {
1882*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE3:
1883*4882a593Smuzhiyun integrity.profile = &t10_pi_type3_crc;
1884*4882a593Smuzhiyun integrity.tag_size = sizeof(u16) + sizeof(u32);
1885*4882a593Smuzhiyun integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1886*4882a593Smuzhiyun break;
1887*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE1:
1888*4882a593Smuzhiyun case NVME_NS_DPS_PI_TYPE2:
1889*4882a593Smuzhiyun integrity.profile = &t10_pi_type1_crc;
1890*4882a593Smuzhiyun integrity.tag_size = sizeof(u16);
1891*4882a593Smuzhiyun integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1892*4882a593Smuzhiyun break;
1893*4882a593Smuzhiyun default:
1894*4882a593Smuzhiyun integrity.profile = NULL;
1895*4882a593Smuzhiyun break;
1896*4882a593Smuzhiyun }
1897*4882a593Smuzhiyun integrity.tuple_size = ms;
1898*4882a593Smuzhiyun blk_integrity_register(disk, &integrity);
1899*4882a593Smuzhiyun blk_queue_max_integrity_segments(disk->queue, max_integrity_segments);
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun #else
nvme_init_integrity(struct gendisk * disk,u16 ms,u8 pi_type,u32 max_integrity_segments)1902*4882a593Smuzhiyun static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type,
1903*4882a593Smuzhiyun u32 max_integrity_segments)
1904*4882a593Smuzhiyun {
1905*4882a593Smuzhiyun }
1906*4882a593Smuzhiyun #endif /* CONFIG_BLK_DEV_INTEGRITY */
1907*4882a593Smuzhiyun
nvme_config_discard(struct gendisk * disk,struct nvme_ns * ns)1908*4882a593Smuzhiyun static void nvme_config_discard(struct gendisk *disk, struct nvme_ns *ns)
1909*4882a593Smuzhiyun {
1910*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
1911*4882a593Smuzhiyun struct request_queue *queue = disk->queue;
1912*4882a593Smuzhiyun u32 size = queue_logical_block_size(queue);
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1915*4882a593Smuzhiyun blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1916*4882a593Smuzhiyun return;
1917*4882a593Smuzhiyun }
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun if (ctrl->nr_streams && ns->sws && ns->sgs)
1920*4882a593Smuzhiyun size *= ns->sws * ns->sgs;
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1923*4882a593Smuzhiyun NVME_DSM_MAX_RANGES);
1924*4882a593Smuzhiyun
1925*4882a593Smuzhiyun queue->limits.discard_alignment = 0;
1926*4882a593Smuzhiyun queue->limits.discard_granularity = size;
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun /* If discard is already enabled, don't reset queue limits */
1929*4882a593Smuzhiyun if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1930*4882a593Smuzhiyun return;
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun blk_queue_max_discard_sectors(queue, UINT_MAX);
1933*4882a593Smuzhiyun blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
1936*4882a593Smuzhiyun blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1937*4882a593Smuzhiyun }
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun /*
1940*4882a593Smuzhiyun * Even though NVMe spec explicitly states that MDTS is not applicable to the
1941*4882a593Smuzhiyun * write-zeroes, we are cautious and limit the size to the controllers
1942*4882a593Smuzhiyun * max_hw_sectors value, which is based on the MDTS field and possibly other
1943*4882a593Smuzhiyun * limiting factors.
1944*4882a593Smuzhiyun */
nvme_config_write_zeroes(struct request_queue * q,struct nvme_ctrl * ctrl)1945*4882a593Smuzhiyun static void nvme_config_write_zeroes(struct request_queue *q,
1946*4882a593Smuzhiyun struct nvme_ctrl *ctrl)
1947*4882a593Smuzhiyun {
1948*4882a593Smuzhiyun if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
1949*4882a593Smuzhiyun !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
1950*4882a593Smuzhiyun blk_queue_max_write_zeroes_sectors(q, ctrl->max_hw_sectors);
1951*4882a593Smuzhiyun }
1952*4882a593Smuzhiyun
nvme_ns_ids_valid(struct nvme_ns_ids * ids)1953*4882a593Smuzhiyun static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1954*4882a593Smuzhiyun {
1955*4882a593Smuzhiyun return !uuid_is_null(&ids->uuid) ||
1956*4882a593Smuzhiyun memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1957*4882a593Smuzhiyun memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1958*4882a593Smuzhiyun }
1959*4882a593Smuzhiyun
nvme_ns_ids_equal(struct nvme_ns_ids * a,struct nvme_ns_ids * b)1960*4882a593Smuzhiyun static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1961*4882a593Smuzhiyun {
1962*4882a593Smuzhiyun return uuid_equal(&a->uuid, &b->uuid) &&
1963*4882a593Smuzhiyun memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1964*4882a593Smuzhiyun memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1965*4882a593Smuzhiyun a->csi == b->csi;
1966*4882a593Smuzhiyun }
1967*4882a593Smuzhiyun
nvme_setup_streams_ns(struct nvme_ctrl * ctrl,struct nvme_ns * ns,u32 * phys_bs,u32 * io_opt)1968*4882a593Smuzhiyun static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1969*4882a593Smuzhiyun u32 *phys_bs, u32 *io_opt)
1970*4882a593Smuzhiyun {
1971*4882a593Smuzhiyun struct streams_directive_params s;
1972*4882a593Smuzhiyun int ret;
1973*4882a593Smuzhiyun
1974*4882a593Smuzhiyun if (!ctrl->nr_streams)
1975*4882a593Smuzhiyun return 0;
1976*4882a593Smuzhiyun
1977*4882a593Smuzhiyun ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
1978*4882a593Smuzhiyun if (ret)
1979*4882a593Smuzhiyun return ret;
1980*4882a593Smuzhiyun
1981*4882a593Smuzhiyun ns->sws = le32_to_cpu(s.sws);
1982*4882a593Smuzhiyun ns->sgs = le16_to_cpu(s.sgs);
1983*4882a593Smuzhiyun
1984*4882a593Smuzhiyun if (ns->sws) {
1985*4882a593Smuzhiyun *phys_bs = ns->sws * (1 << ns->lba_shift);
1986*4882a593Smuzhiyun if (ns->sgs)
1987*4882a593Smuzhiyun *io_opt = *phys_bs * ns->sgs;
1988*4882a593Smuzhiyun }
1989*4882a593Smuzhiyun
1990*4882a593Smuzhiyun return 0;
1991*4882a593Smuzhiyun }
1992*4882a593Smuzhiyun
nvme_configure_metadata(struct nvme_ns * ns,struct nvme_id_ns * id)1993*4882a593Smuzhiyun static int nvme_configure_metadata(struct nvme_ns *ns, struct nvme_id_ns *id)
1994*4882a593Smuzhiyun {
1995*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
1996*4882a593Smuzhiyun
1997*4882a593Smuzhiyun /*
1998*4882a593Smuzhiyun * The PI implementation requires the metadata size to be equal to the
1999*4882a593Smuzhiyun * t10 pi tuple size.
2000*4882a593Smuzhiyun */
2001*4882a593Smuzhiyun ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
2002*4882a593Smuzhiyun if (ns->ms == sizeof(struct t10_pi_tuple))
2003*4882a593Smuzhiyun ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
2004*4882a593Smuzhiyun else
2005*4882a593Smuzhiyun ns->pi_type = 0;
2006*4882a593Smuzhiyun
2007*4882a593Smuzhiyun ns->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
2008*4882a593Smuzhiyun if (!ns->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
2009*4882a593Smuzhiyun return 0;
2010*4882a593Smuzhiyun if (ctrl->ops->flags & NVME_F_FABRICS) {
2011*4882a593Smuzhiyun /*
2012*4882a593Smuzhiyun * The NVMe over Fabrics specification only supports metadata as
2013*4882a593Smuzhiyun * part of the extended data LBA. We rely on HCA/HBA support to
2014*4882a593Smuzhiyun * remap the separate metadata buffer from the block layer.
2015*4882a593Smuzhiyun */
2016*4882a593Smuzhiyun if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
2017*4882a593Smuzhiyun return -EINVAL;
2018*4882a593Smuzhiyun if (ctrl->max_integrity_segments)
2019*4882a593Smuzhiyun ns->features |=
2020*4882a593Smuzhiyun (NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
2021*4882a593Smuzhiyun } else {
2022*4882a593Smuzhiyun /*
2023*4882a593Smuzhiyun * For PCIe controllers, we can't easily remap the separate
2024*4882a593Smuzhiyun * metadata buffer from the block layer and thus require a
2025*4882a593Smuzhiyun * separate metadata buffer for block layer metadata/PI support.
2026*4882a593Smuzhiyun * We allow extended LBAs for the passthrough interface, though.
2027*4882a593Smuzhiyun */
2028*4882a593Smuzhiyun if (id->flbas & NVME_NS_FLBAS_META_EXT)
2029*4882a593Smuzhiyun ns->features |= NVME_NS_EXT_LBAS;
2030*4882a593Smuzhiyun else
2031*4882a593Smuzhiyun ns->features |= NVME_NS_METADATA_SUPPORTED;
2032*4882a593Smuzhiyun }
2033*4882a593Smuzhiyun
2034*4882a593Smuzhiyun return 0;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun
nvme_set_queue_limits(struct nvme_ctrl * ctrl,struct request_queue * q)2037*4882a593Smuzhiyun static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
2038*4882a593Smuzhiyun struct request_queue *q)
2039*4882a593Smuzhiyun {
2040*4882a593Smuzhiyun bool vwc = ctrl->vwc & NVME_CTRL_VWC_PRESENT;
2041*4882a593Smuzhiyun
2042*4882a593Smuzhiyun if (ctrl->max_hw_sectors) {
2043*4882a593Smuzhiyun u32 max_segments =
2044*4882a593Smuzhiyun (ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> 9)) + 1;
2045*4882a593Smuzhiyun
2046*4882a593Smuzhiyun max_segments = min_not_zero(max_segments, ctrl->max_segments);
2047*4882a593Smuzhiyun blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
2048*4882a593Smuzhiyun blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1);
2051*4882a593Smuzhiyun blk_queue_dma_alignment(q, 3);
2052*4882a593Smuzhiyun blk_queue_write_cache(q, vwc, vwc);
2053*4882a593Smuzhiyun }
2054*4882a593Smuzhiyun
nvme_update_disk_info(struct gendisk * disk,struct nvme_ns * ns,struct nvme_id_ns * id)2055*4882a593Smuzhiyun static void nvme_update_disk_info(struct gendisk *disk,
2056*4882a593Smuzhiyun struct nvme_ns *ns, struct nvme_id_ns *id)
2057*4882a593Smuzhiyun {
2058*4882a593Smuzhiyun sector_t capacity = nvme_lba_to_sect(ns, le64_to_cpu(id->nsze));
2059*4882a593Smuzhiyun unsigned short bs = 1 << ns->lba_shift;
2060*4882a593Smuzhiyun u32 atomic_bs, phys_bs, io_opt = 0;
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun /*
2063*4882a593Smuzhiyun * The block layer can't support LBA sizes larger than the page size
2064*4882a593Smuzhiyun * yet, so catch this early and don't allow block I/O.
2065*4882a593Smuzhiyun */
2066*4882a593Smuzhiyun if (ns->lba_shift > PAGE_SHIFT) {
2067*4882a593Smuzhiyun capacity = 0;
2068*4882a593Smuzhiyun bs = (1 << 9);
2069*4882a593Smuzhiyun }
2070*4882a593Smuzhiyun
2071*4882a593Smuzhiyun blk_integrity_unregister(disk);
2072*4882a593Smuzhiyun
2073*4882a593Smuzhiyun atomic_bs = phys_bs = bs;
2074*4882a593Smuzhiyun nvme_setup_streams_ns(ns->ctrl, ns, &phys_bs, &io_opt);
2075*4882a593Smuzhiyun if (id->nabo == 0) {
2076*4882a593Smuzhiyun /*
2077*4882a593Smuzhiyun * Bit 1 indicates whether NAWUPF is defined for this namespace
2078*4882a593Smuzhiyun * and whether it should be used instead of AWUPF. If NAWUPF ==
2079*4882a593Smuzhiyun * 0 then AWUPF must be used instead.
2080*4882a593Smuzhiyun */
2081*4882a593Smuzhiyun if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
2082*4882a593Smuzhiyun atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
2083*4882a593Smuzhiyun else
2084*4882a593Smuzhiyun atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun
2087*4882a593Smuzhiyun if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
2088*4882a593Smuzhiyun /* NPWG = Namespace Preferred Write Granularity */
2089*4882a593Smuzhiyun phys_bs = bs * (1 + le16_to_cpu(id->npwg));
2090*4882a593Smuzhiyun /* NOWS = Namespace Optimal Write Size */
2091*4882a593Smuzhiyun io_opt = bs * (1 + le16_to_cpu(id->nows));
2092*4882a593Smuzhiyun }
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun blk_queue_logical_block_size(disk->queue, bs);
2095*4882a593Smuzhiyun /*
2096*4882a593Smuzhiyun * Linux filesystems assume writing a single physical block is
2097*4882a593Smuzhiyun * an atomic operation. Hence limit the physical block size to the
2098*4882a593Smuzhiyun * value of the Atomic Write Unit Power Fail parameter.
2099*4882a593Smuzhiyun */
2100*4882a593Smuzhiyun blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs));
2101*4882a593Smuzhiyun blk_queue_io_min(disk->queue, phys_bs);
2102*4882a593Smuzhiyun blk_queue_io_opt(disk->queue, io_opt);
2103*4882a593Smuzhiyun
2104*4882a593Smuzhiyun /*
2105*4882a593Smuzhiyun * Register a metadata profile for PI, or the plain non-integrity NVMe
2106*4882a593Smuzhiyun * metadata masquerading as Type 0 if supported, otherwise reject block
2107*4882a593Smuzhiyun * I/O to namespaces with metadata except when the namespace supports
2108*4882a593Smuzhiyun * PI, as it can strip/insert in that case.
2109*4882a593Smuzhiyun */
2110*4882a593Smuzhiyun if (ns->ms) {
2111*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) &&
2112*4882a593Smuzhiyun (ns->features & NVME_NS_METADATA_SUPPORTED))
2113*4882a593Smuzhiyun nvme_init_integrity(disk, ns->ms, ns->pi_type,
2114*4882a593Smuzhiyun ns->ctrl->max_integrity_segments);
2115*4882a593Smuzhiyun else if (!nvme_ns_has_pi(ns))
2116*4882a593Smuzhiyun capacity = 0;
2117*4882a593Smuzhiyun }
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun set_capacity_revalidate_and_notify(disk, capacity, false);
2120*4882a593Smuzhiyun
2121*4882a593Smuzhiyun nvme_config_discard(disk, ns);
2122*4882a593Smuzhiyun nvme_config_write_zeroes(disk->queue, ns->ctrl);
2123*4882a593Smuzhiyun
2124*4882a593Smuzhiyun if (id->nsattr & NVME_NS_ATTR_RO)
2125*4882a593Smuzhiyun set_disk_ro(disk, true);
2126*4882a593Smuzhiyun }
2127*4882a593Smuzhiyun
nvme_first_scan(struct gendisk * disk)2128*4882a593Smuzhiyun static inline bool nvme_first_scan(struct gendisk *disk)
2129*4882a593Smuzhiyun {
2130*4882a593Smuzhiyun /* nvme_alloc_ns() scans the disk prior to adding it */
2131*4882a593Smuzhiyun return !(disk->flags & GENHD_FL_UP);
2132*4882a593Smuzhiyun }
2133*4882a593Smuzhiyun
nvme_set_chunk_sectors(struct nvme_ns * ns,struct nvme_id_ns * id)2134*4882a593Smuzhiyun static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id)
2135*4882a593Smuzhiyun {
2136*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
2137*4882a593Smuzhiyun u32 iob;
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2140*4882a593Smuzhiyun is_power_of_2(ctrl->max_hw_sectors))
2141*4882a593Smuzhiyun iob = ctrl->max_hw_sectors;
2142*4882a593Smuzhiyun else
2143*4882a593Smuzhiyun iob = nvme_lba_to_sect(ns, le16_to_cpu(id->noiob));
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun if (!iob)
2146*4882a593Smuzhiyun return;
2147*4882a593Smuzhiyun
2148*4882a593Smuzhiyun if (!is_power_of_2(iob)) {
2149*4882a593Smuzhiyun if (nvme_first_scan(ns->disk))
2150*4882a593Smuzhiyun pr_warn("%s: ignoring unaligned IO boundary:%u\n",
2151*4882a593Smuzhiyun ns->disk->disk_name, iob);
2152*4882a593Smuzhiyun return;
2153*4882a593Smuzhiyun }
2154*4882a593Smuzhiyun
2155*4882a593Smuzhiyun if (blk_queue_is_zoned(ns->disk->queue)) {
2156*4882a593Smuzhiyun if (nvme_first_scan(ns->disk))
2157*4882a593Smuzhiyun pr_warn("%s: ignoring zoned namespace IO boundary\n",
2158*4882a593Smuzhiyun ns->disk->disk_name);
2159*4882a593Smuzhiyun return;
2160*4882a593Smuzhiyun }
2161*4882a593Smuzhiyun
2162*4882a593Smuzhiyun blk_queue_chunk_sectors(ns->queue, iob);
2163*4882a593Smuzhiyun }
2164*4882a593Smuzhiyun
nvme_update_ns_info(struct nvme_ns * ns,struct nvme_id_ns * id)2165*4882a593Smuzhiyun static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_id_ns *id)
2166*4882a593Smuzhiyun {
2167*4882a593Smuzhiyun unsigned lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2168*4882a593Smuzhiyun int ret;
2169*4882a593Smuzhiyun
2170*4882a593Smuzhiyun blk_mq_freeze_queue(ns->disk->queue);
2171*4882a593Smuzhiyun ns->lba_shift = id->lbaf[lbaf].ds;
2172*4882a593Smuzhiyun nvme_set_queue_limits(ns->ctrl, ns->queue);
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun if (ns->head->ids.csi == NVME_CSI_ZNS) {
2175*4882a593Smuzhiyun ret = nvme_update_zone_info(ns, lbaf);
2176*4882a593Smuzhiyun if (ret)
2177*4882a593Smuzhiyun goto out_unfreeze;
2178*4882a593Smuzhiyun }
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun ret = nvme_configure_metadata(ns, id);
2181*4882a593Smuzhiyun if (ret)
2182*4882a593Smuzhiyun goto out_unfreeze;
2183*4882a593Smuzhiyun nvme_set_chunk_sectors(ns, id);
2184*4882a593Smuzhiyun nvme_update_disk_info(ns->disk, ns, id);
2185*4882a593Smuzhiyun blk_mq_unfreeze_queue(ns->disk->queue);
2186*4882a593Smuzhiyun
2187*4882a593Smuzhiyun if (blk_queue_is_zoned(ns->queue)) {
2188*4882a593Smuzhiyun ret = nvme_revalidate_zones(ns);
2189*4882a593Smuzhiyun if (ret && !nvme_first_scan(ns->disk))
2190*4882a593Smuzhiyun return ret;
2191*4882a593Smuzhiyun }
2192*4882a593Smuzhiyun
2193*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
2194*4882a593Smuzhiyun if (ns->head->disk) {
2195*4882a593Smuzhiyun blk_mq_freeze_queue(ns->head->disk->queue);
2196*4882a593Smuzhiyun nvme_update_disk_info(ns->head->disk, ns, id);
2197*4882a593Smuzhiyun blk_stack_limits(&ns->head->disk->queue->limits,
2198*4882a593Smuzhiyun &ns->queue->limits, 0);
2199*4882a593Smuzhiyun blk_queue_update_readahead(ns->head->disk->queue);
2200*4882a593Smuzhiyun nvme_update_bdev_size(ns->head->disk);
2201*4882a593Smuzhiyun blk_mq_unfreeze_queue(ns->head->disk->queue);
2202*4882a593Smuzhiyun }
2203*4882a593Smuzhiyun #endif
2204*4882a593Smuzhiyun return 0;
2205*4882a593Smuzhiyun
2206*4882a593Smuzhiyun out_unfreeze:
2207*4882a593Smuzhiyun blk_mq_unfreeze_queue(ns->disk->queue);
2208*4882a593Smuzhiyun return ret;
2209*4882a593Smuzhiyun }
2210*4882a593Smuzhiyun
nvme_pr_type(enum pr_type type)2211*4882a593Smuzhiyun static char nvme_pr_type(enum pr_type type)
2212*4882a593Smuzhiyun {
2213*4882a593Smuzhiyun switch (type) {
2214*4882a593Smuzhiyun case PR_WRITE_EXCLUSIVE:
2215*4882a593Smuzhiyun return 1;
2216*4882a593Smuzhiyun case PR_EXCLUSIVE_ACCESS:
2217*4882a593Smuzhiyun return 2;
2218*4882a593Smuzhiyun case PR_WRITE_EXCLUSIVE_REG_ONLY:
2219*4882a593Smuzhiyun return 3;
2220*4882a593Smuzhiyun case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2221*4882a593Smuzhiyun return 4;
2222*4882a593Smuzhiyun case PR_WRITE_EXCLUSIVE_ALL_REGS:
2223*4882a593Smuzhiyun return 5;
2224*4882a593Smuzhiyun case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2225*4882a593Smuzhiyun return 6;
2226*4882a593Smuzhiyun default:
2227*4882a593Smuzhiyun return 0;
2228*4882a593Smuzhiyun }
2229*4882a593Smuzhiyun };
2230*4882a593Smuzhiyun
nvme_pr_command(struct block_device * bdev,u32 cdw10,u64 key,u64 sa_key,u8 op)2231*4882a593Smuzhiyun static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2232*4882a593Smuzhiyun u64 key, u64 sa_key, u8 op)
2233*4882a593Smuzhiyun {
2234*4882a593Smuzhiyun struct nvme_ns_head *head = NULL;
2235*4882a593Smuzhiyun struct nvme_ns *ns;
2236*4882a593Smuzhiyun struct nvme_command c;
2237*4882a593Smuzhiyun int srcu_idx, ret;
2238*4882a593Smuzhiyun u8 data[16] = { 0, };
2239*4882a593Smuzhiyun
2240*4882a593Smuzhiyun ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
2241*4882a593Smuzhiyun if (unlikely(!ns))
2242*4882a593Smuzhiyun return -EWOULDBLOCK;
2243*4882a593Smuzhiyun
2244*4882a593Smuzhiyun put_unaligned_le64(key, &data[0]);
2245*4882a593Smuzhiyun put_unaligned_le64(sa_key, &data[8]);
2246*4882a593Smuzhiyun
2247*4882a593Smuzhiyun memset(&c, 0, sizeof(c));
2248*4882a593Smuzhiyun c.common.opcode = op;
2249*4882a593Smuzhiyun c.common.nsid = cpu_to_le32(ns->head->ns_id);
2250*4882a593Smuzhiyun c.common.cdw10 = cpu_to_le32(cdw10);
2251*4882a593Smuzhiyun
2252*4882a593Smuzhiyun ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2253*4882a593Smuzhiyun nvme_put_ns_from_disk(head, srcu_idx);
2254*4882a593Smuzhiyun return ret;
2255*4882a593Smuzhiyun }
2256*4882a593Smuzhiyun
nvme_pr_register(struct block_device * bdev,u64 old,u64 new,unsigned flags)2257*4882a593Smuzhiyun static int nvme_pr_register(struct block_device *bdev, u64 old,
2258*4882a593Smuzhiyun u64 new, unsigned flags)
2259*4882a593Smuzhiyun {
2260*4882a593Smuzhiyun u32 cdw10;
2261*4882a593Smuzhiyun
2262*4882a593Smuzhiyun if (flags & ~PR_FL_IGNORE_KEY)
2263*4882a593Smuzhiyun return -EOPNOTSUPP;
2264*4882a593Smuzhiyun
2265*4882a593Smuzhiyun cdw10 = old ? 2 : 0;
2266*4882a593Smuzhiyun cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2267*4882a593Smuzhiyun cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2268*4882a593Smuzhiyun return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2269*4882a593Smuzhiyun }
2270*4882a593Smuzhiyun
nvme_pr_reserve(struct block_device * bdev,u64 key,enum pr_type type,unsigned flags)2271*4882a593Smuzhiyun static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2272*4882a593Smuzhiyun enum pr_type type, unsigned flags)
2273*4882a593Smuzhiyun {
2274*4882a593Smuzhiyun u32 cdw10;
2275*4882a593Smuzhiyun
2276*4882a593Smuzhiyun if (flags & ~PR_FL_IGNORE_KEY)
2277*4882a593Smuzhiyun return -EOPNOTSUPP;
2278*4882a593Smuzhiyun
2279*4882a593Smuzhiyun cdw10 = nvme_pr_type(type) << 8;
2280*4882a593Smuzhiyun cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2281*4882a593Smuzhiyun return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2282*4882a593Smuzhiyun }
2283*4882a593Smuzhiyun
nvme_pr_preempt(struct block_device * bdev,u64 old,u64 new,enum pr_type type,bool abort)2284*4882a593Smuzhiyun static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2285*4882a593Smuzhiyun enum pr_type type, bool abort)
2286*4882a593Smuzhiyun {
2287*4882a593Smuzhiyun u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
2288*4882a593Smuzhiyun
2289*4882a593Smuzhiyun return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2290*4882a593Smuzhiyun }
2291*4882a593Smuzhiyun
nvme_pr_clear(struct block_device * bdev,u64 key)2292*4882a593Smuzhiyun static int nvme_pr_clear(struct block_device *bdev, u64 key)
2293*4882a593Smuzhiyun {
2294*4882a593Smuzhiyun u32 cdw10 = 1 | (key ? 0 : 1 << 3);
2295*4882a593Smuzhiyun
2296*4882a593Smuzhiyun return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2297*4882a593Smuzhiyun }
2298*4882a593Smuzhiyun
nvme_pr_release(struct block_device * bdev,u64 key,enum pr_type type)2299*4882a593Smuzhiyun static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2300*4882a593Smuzhiyun {
2301*4882a593Smuzhiyun u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 0 : 1 << 3);
2302*4882a593Smuzhiyun
2303*4882a593Smuzhiyun return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2304*4882a593Smuzhiyun }
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun static const struct pr_ops nvme_pr_ops = {
2307*4882a593Smuzhiyun .pr_register = nvme_pr_register,
2308*4882a593Smuzhiyun .pr_reserve = nvme_pr_reserve,
2309*4882a593Smuzhiyun .pr_release = nvme_pr_release,
2310*4882a593Smuzhiyun .pr_preempt = nvme_pr_preempt,
2311*4882a593Smuzhiyun .pr_clear = nvme_pr_clear,
2312*4882a593Smuzhiyun };
2313*4882a593Smuzhiyun
2314*4882a593Smuzhiyun #ifdef CONFIG_BLK_SED_OPAL
nvme_sec_submit(void * data,u16 spsp,u8 secp,void * buffer,size_t len,bool send)2315*4882a593Smuzhiyun int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
2316*4882a593Smuzhiyun bool send)
2317*4882a593Smuzhiyun {
2318*4882a593Smuzhiyun struct nvme_ctrl *ctrl = data;
2319*4882a593Smuzhiyun struct nvme_command cmd;
2320*4882a593Smuzhiyun
2321*4882a593Smuzhiyun memset(&cmd, 0, sizeof(cmd));
2322*4882a593Smuzhiyun if (send)
2323*4882a593Smuzhiyun cmd.common.opcode = nvme_admin_security_send;
2324*4882a593Smuzhiyun else
2325*4882a593Smuzhiyun cmd.common.opcode = nvme_admin_security_recv;
2326*4882a593Smuzhiyun cmd.common.nsid = 0;
2327*4882a593Smuzhiyun cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2328*4882a593Smuzhiyun cmd.common.cdw11 = cpu_to_le32(len);
2329*4882a593Smuzhiyun
2330*4882a593Smuzhiyun return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
2331*4882a593Smuzhiyun ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0, false);
2332*4882a593Smuzhiyun }
2333*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_sec_submit);
2334*4882a593Smuzhiyun #endif /* CONFIG_BLK_SED_OPAL */
2335*4882a593Smuzhiyun
2336*4882a593Smuzhiyun static const struct block_device_operations nvme_fops = {
2337*4882a593Smuzhiyun .owner = THIS_MODULE,
2338*4882a593Smuzhiyun .ioctl = nvme_ioctl,
2339*4882a593Smuzhiyun .compat_ioctl = nvme_compat_ioctl,
2340*4882a593Smuzhiyun .open = nvme_open,
2341*4882a593Smuzhiyun .release = nvme_release,
2342*4882a593Smuzhiyun .getgeo = nvme_getgeo,
2343*4882a593Smuzhiyun .report_zones = nvme_report_zones,
2344*4882a593Smuzhiyun .pr_ops = &nvme_pr_ops,
2345*4882a593Smuzhiyun };
2346*4882a593Smuzhiyun
2347*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
nvme_ns_head_open(struct block_device * bdev,fmode_t mode)2348*4882a593Smuzhiyun static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
2349*4882a593Smuzhiyun {
2350*4882a593Smuzhiyun struct nvme_ns_head *head = bdev->bd_disk->private_data;
2351*4882a593Smuzhiyun
2352*4882a593Smuzhiyun if (!kref_get_unless_zero(&head->ref))
2353*4882a593Smuzhiyun return -ENXIO;
2354*4882a593Smuzhiyun return 0;
2355*4882a593Smuzhiyun }
2356*4882a593Smuzhiyun
nvme_ns_head_release(struct gendisk * disk,fmode_t mode)2357*4882a593Smuzhiyun static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
2358*4882a593Smuzhiyun {
2359*4882a593Smuzhiyun nvme_put_ns_head(disk->private_data);
2360*4882a593Smuzhiyun }
2361*4882a593Smuzhiyun
2362*4882a593Smuzhiyun const struct block_device_operations nvme_ns_head_ops = {
2363*4882a593Smuzhiyun .owner = THIS_MODULE,
2364*4882a593Smuzhiyun .submit_bio = nvme_ns_head_submit_bio,
2365*4882a593Smuzhiyun .open = nvme_ns_head_open,
2366*4882a593Smuzhiyun .release = nvme_ns_head_release,
2367*4882a593Smuzhiyun .ioctl = nvme_ioctl,
2368*4882a593Smuzhiyun .compat_ioctl = nvme_compat_ioctl,
2369*4882a593Smuzhiyun .getgeo = nvme_getgeo,
2370*4882a593Smuzhiyun .report_zones = nvme_report_zones,
2371*4882a593Smuzhiyun .pr_ops = &nvme_pr_ops,
2372*4882a593Smuzhiyun };
2373*4882a593Smuzhiyun #endif /* CONFIG_NVME_MULTIPATH */
2374*4882a593Smuzhiyun
nvme_wait_ready(struct nvme_ctrl * ctrl,u64 cap,bool enabled)2375*4882a593Smuzhiyun static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
2376*4882a593Smuzhiyun {
2377*4882a593Smuzhiyun unsigned long timeout =
2378*4882a593Smuzhiyun ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
2379*4882a593Smuzhiyun u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
2380*4882a593Smuzhiyun int ret;
2381*4882a593Smuzhiyun
2382*4882a593Smuzhiyun while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
2383*4882a593Smuzhiyun if (csts == ~0)
2384*4882a593Smuzhiyun return -ENODEV;
2385*4882a593Smuzhiyun if ((csts & NVME_CSTS_RDY) == bit)
2386*4882a593Smuzhiyun break;
2387*4882a593Smuzhiyun
2388*4882a593Smuzhiyun usleep_range(1000, 2000);
2389*4882a593Smuzhiyun if (fatal_signal_pending(current))
2390*4882a593Smuzhiyun return -EINTR;
2391*4882a593Smuzhiyun if (time_after(jiffies, timeout)) {
2392*4882a593Smuzhiyun dev_err(ctrl->device,
2393*4882a593Smuzhiyun "Device not ready; aborting %s, CSTS=0x%x\n",
2394*4882a593Smuzhiyun enabled ? "initialisation" : "reset", csts);
2395*4882a593Smuzhiyun return -ENODEV;
2396*4882a593Smuzhiyun }
2397*4882a593Smuzhiyun }
2398*4882a593Smuzhiyun
2399*4882a593Smuzhiyun return ret;
2400*4882a593Smuzhiyun }
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun /*
2403*4882a593Smuzhiyun * If the device has been passed off to us in an enabled state, just clear
2404*4882a593Smuzhiyun * the enabled bit. The spec says we should set the 'shutdown notification
2405*4882a593Smuzhiyun * bits', but doing so may cause the device to complete commands to the
2406*4882a593Smuzhiyun * admin queue ... and we don't know what memory that might be pointing at!
2407*4882a593Smuzhiyun */
nvme_disable_ctrl(struct nvme_ctrl * ctrl)2408*4882a593Smuzhiyun int nvme_disable_ctrl(struct nvme_ctrl *ctrl)
2409*4882a593Smuzhiyun {
2410*4882a593Smuzhiyun int ret;
2411*4882a593Smuzhiyun
2412*4882a593Smuzhiyun ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2413*4882a593Smuzhiyun ctrl->ctrl_config &= ~NVME_CC_ENABLE;
2414*4882a593Smuzhiyun
2415*4882a593Smuzhiyun ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2416*4882a593Smuzhiyun if (ret)
2417*4882a593Smuzhiyun return ret;
2418*4882a593Smuzhiyun
2419*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
2420*4882a593Smuzhiyun msleep(NVME_QUIRK_DELAY_AMOUNT);
2421*4882a593Smuzhiyun
2422*4882a593Smuzhiyun return nvme_wait_ready(ctrl, ctrl->cap, false);
2423*4882a593Smuzhiyun }
2424*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
2425*4882a593Smuzhiyun
nvme_enable_ctrl(struct nvme_ctrl * ctrl)2426*4882a593Smuzhiyun int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
2427*4882a593Smuzhiyun {
2428*4882a593Smuzhiyun unsigned dev_page_min;
2429*4882a593Smuzhiyun int ret;
2430*4882a593Smuzhiyun
2431*4882a593Smuzhiyun ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2432*4882a593Smuzhiyun if (ret) {
2433*4882a593Smuzhiyun dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2434*4882a593Smuzhiyun return ret;
2435*4882a593Smuzhiyun }
2436*4882a593Smuzhiyun dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2437*4882a593Smuzhiyun
2438*4882a593Smuzhiyun if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
2439*4882a593Smuzhiyun dev_err(ctrl->device,
2440*4882a593Smuzhiyun "Minimum device page size %u too large for host (%u)\n",
2441*4882a593Smuzhiyun 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
2442*4882a593Smuzhiyun return -ENODEV;
2443*4882a593Smuzhiyun }
2444*4882a593Smuzhiyun
2445*4882a593Smuzhiyun if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2446*4882a593Smuzhiyun ctrl->ctrl_config = NVME_CC_CSS_CSI;
2447*4882a593Smuzhiyun else
2448*4882a593Smuzhiyun ctrl->ctrl_config = NVME_CC_CSS_NVM;
2449*4882a593Smuzhiyun ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
2450*4882a593Smuzhiyun ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
2451*4882a593Smuzhiyun ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
2452*4882a593Smuzhiyun ctrl->ctrl_config |= NVME_CC_ENABLE;
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2455*4882a593Smuzhiyun if (ret)
2456*4882a593Smuzhiyun return ret;
2457*4882a593Smuzhiyun return nvme_wait_ready(ctrl, ctrl->cap, true);
2458*4882a593Smuzhiyun }
2459*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
2460*4882a593Smuzhiyun
nvme_shutdown_ctrl(struct nvme_ctrl * ctrl)2461*4882a593Smuzhiyun int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
2462*4882a593Smuzhiyun {
2463*4882a593Smuzhiyun unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
2464*4882a593Smuzhiyun u32 csts;
2465*4882a593Smuzhiyun int ret;
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2468*4882a593Smuzhiyun ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2469*4882a593Smuzhiyun
2470*4882a593Smuzhiyun ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2471*4882a593Smuzhiyun if (ret)
2472*4882a593Smuzhiyun return ret;
2473*4882a593Smuzhiyun
2474*4882a593Smuzhiyun while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
2475*4882a593Smuzhiyun if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
2476*4882a593Smuzhiyun break;
2477*4882a593Smuzhiyun
2478*4882a593Smuzhiyun msleep(100);
2479*4882a593Smuzhiyun if (fatal_signal_pending(current))
2480*4882a593Smuzhiyun return -EINTR;
2481*4882a593Smuzhiyun if (time_after(jiffies, timeout)) {
2482*4882a593Smuzhiyun dev_err(ctrl->device,
2483*4882a593Smuzhiyun "Device shutdown incomplete; abort shutdown\n");
2484*4882a593Smuzhiyun return -ENODEV;
2485*4882a593Smuzhiyun }
2486*4882a593Smuzhiyun }
2487*4882a593Smuzhiyun
2488*4882a593Smuzhiyun return ret;
2489*4882a593Smuzhiyun }
2490*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
2491*4882a593Smuzhiyun
nvme_configure_timestamp(struct nvme_ctrl * ctrl)2492*4882a593Smuzhiyun static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun __le64 ts;
2495*4882a593Smuzhiyun int ret;
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2498*4882a593Smuzhiyun return 0;
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2501*4882a593Smuzhiyun ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2502*4882a593Smuzhiyun NULL);
2503*4882a593Smuzhiyun if (ret)
2504*4882a593Smuzhiyun dev_warn_once(ctrl->device,
2505*4882a593Smuzhiyun "could not set timestamp (%d)\n", ret);
2506*4882a593Smuzhiyun return ret;
2507*4882a593Smuzhiyun }
2508*4882a593Smuzhiyun
nvme_configure_acre(struct nvme_ctrl * ctrl)2509*4882a593Smuzhiyun static int nvme_configure_acre(struct nvme_ctrl *ctrl)
2510*4882a593Smuzhiyun {
2511*4882a593Smuzhiyun struct nvme_feat_host_behavior *host;
2512*4882a593Smuzhiyun int ret;
2513*4882a593Smuzhiyun
2514*4882a593Smuzhiyun /* Don't bother enabling the feature if retry delay is not reported */
2515*4882a593Smuzhiyun if (!ctrl->crdt[0])
2516*4882a593Smuzhiyun return 0;
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun host = kzalloc(sizeof(*host), GFP_KERNEL);
2519*4882a593Smuzhiyun if (!host)
2520*4882a593Smuzhiyun return 0;
2521*4882a593Smuzhiyun
2522*4882a593Smuzhiyun host->acre = NVME_ENABLE_ACRE;
2523*4882a593Smuzhiyun ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2524*4882a593Smuzhiyun host, sizeof(*host), NULL);
2525*4882a593Smuzhiyun kfree(host);
2526*4882a593Smuzhiyun return ret;
2527*4882a593Smuzhiyun }
2528*4882a593Smuzhiyun
nvme_configure_apst(struct nvme_ctrl * ctrl)2529*4882a593Smuzhiyun static int nvme_configure_apst(struct nvme_ctrl *ctrl)
2530*4882a593Smuzhiyun {
2531*4882a593Smuzhiyun /*
2532*4882a593Smuzhiyun * APST (Autonomous Power State Transition) lets us program a
2533*4882a593Smuzhiyun * table of power state transitions that the controller will
2534*4882a593Smuzhiyun * perform automatically. We configure it with a simple
2535*4882a593Smuzhiyun * heuristic: we are willing to spend at most 2% of the time
2536*4882a593Smuzhiyun * transitioning between power states. Therefore, when running
2537*4882a593Smuzhiyun * in any given state, we will enter the next lower-power
2538*4882a593Smuzhiyun * non-operational state after waiting 50 * (enlat + exlat)
2539*4882a593Smuzhiyun * microseconds, as long as that state's exit latency is under
2540*4882a593Smuzhiyun * the requested maximum latency.
2541*4882a593Smuzhiyun *
2542*4882a593Smuzhiyun * We will not autonomously enter any non-operational state for
2543*4882a593Smuzhiyun * which the total latency exceeds ps_max_latency_us. Users
2544*4882a593Smuzhiyun * can set ps_max_latency_us to zero to turn off APST.
2545*4882a593Smuzhiyun */
2546*4882a593Smuzhiyun
2547*4882a593Smuzhiyun unsigned apste;
2548*4882a593Smuzhiyun struct nvme_feat_auto_pst *table;
2549*4882a593Smuzhiyun u64 max_lat_us = 0;
2550*4882a593Smuzhiyun int max_ps = -1;
2551*4882a593Smuzhiyun int ret;
2552*4882a593Smuzhiyun
2553*4882a593Smuzhiyun /*
2554*4882a593Smuzhiyun * If APST isn't supported or if we haven't been initialized yet,
2555*4882a593Smuzhiyun * then don't do anything.
2556*4882a593Smuzhiyun */
2557*4882a593Smuzhiyun if (!ctrl->apsta)
2558*4882a593Smuzhiyun return 0;
2559*4882a593Smuzhiyun
2560*4882a593Smuzhiyun if (ctrl->npss > 31) {
2561*4882a593Smuzhiyun dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
2562*4882a593Smuzhiyun return 0;
2563*4882a593Smuzhiyun }
2564*4882a593Smuzhiyun
2565*4882a593Smuzhiyun table = kzalloc(sizeof(*table), GFP_KERNEL);
2566*4882a593Smuzhiyun if (!table)
2567*4882a593Smuzhiyun return 0;
2568*4882a593Smuzhiyun
2569*4882a593Smuzhiyun if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
2570*4882a593Smuzhiyun /* Turn off APST. */
2571*4882a593Smuzhiyun apste = 0;
2572*4882a593Smuzhiyun dev_dbg(ctrl->device, "APST disabled\n");
2573*4882a593Smuzhiyun } else {
2574*4882a593Smuzhiyun __le64 target = cpu_to_le64(0);
2575*4882a593Smuzhiyun int state;
2576*4882a593Smuzhiyun
2577*4882a593Smuzhiyun /*
2578*4882a593Smuzhiyun * Walk through all states from lowest- to highest-power.
2579*4882a593Smuzhiyun * According to the spec, lower-numbered states use more
2580*4882a593Smuzhiyun * power. NPSS, despite the name, is the index of the
2581*4882a593Smuzhiyun * lowest-power state, not the number of states.
2582*4882a593Smuzhiyun */
2583*4882a593Smuzhiyun for (state = (int)ctrl->npss; state >= 0; state--) {
2584*4882a593Smuzhiyun u64 total_latency_us, exit_latency_us, transition_ms;
2585*4882a593Smuzhiyun
2586*4882a593Smuzhiyun if (target)
2587*4882a593Smuzhiyun table->entries[state] = target;
2588*4882a593Smuzhiyun
2589*4882a593Smuzhiyun /*
2590*4882a593Smuzhiyun * Don't allow transitions to the deepest state
2591*4882a593Smuzhiyun * if it's quirked off.
2592*4882a593Smuzhiyun */
2593*4882a593Smuzhiyun if (state == ctrl->npss &&
2594*4882a593Smuzhiyun (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2595*4882a593Smuzhiyun continue;
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun /*
2598*4882a593Smuzhiyun * Is this state a useful non-operational state for
2599*4882a593Smuzhiyun * higher-power states to autonomously transition to?
2600*4882a593Smuzhiyun */
2601*4882a593Smuzhiyun if (!(ctrl->psd[state].flags &
2602*4882a593Smuzhiyun NVME_PS_FLAGS_NON_OP_STATE))
2603*4882a593Smuzhiyun continue;
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun exit_latency_us =
2606*4882a593Smuzhiyun (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2607*4882a593Smuzhiyun if (exit_latency_us > ctrl->ps_max_latency_us)
2608*4882a593Smuzhiyun continue;
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun total_latency_us =
2611*4882a593Smuzhiyun exit_latency_us +
2612*4882a593Smuzhiyun le32_to_cpu(ctrl->psd[state].entry_lat);
2613*4882a593Smuzhiyun
2614*4882a593Smuzhiyun /*
2615*4882a593Smuzhiyun * This state is good. Use it as the APST idle
2616*4882a593Smuzhiyun * target for higher power states.
2617*4882a593Smuzhiyun */
2618*4882a593Smuzhiyun transition_ms = total_latency_us + 19;
2619*4882a593Smuzhiyun do_div(transition_ms, 20);
2620*4882a593Smuzhiyun if (transition_ms > (1 << 24) - 1)
2621*4882a593Smuzhiyun transition_ms = (1 << 24) - 1;
2622*4882a593Smuzhiyun
2623*4882a593Smuzhiyun target = cpu_to_le64((state << 3) |
2624*4882a593Smuzhiyun (transition_ms << 8));
2625*4882a593Smuzhiyun
2626*4882a593Smuzhiyun if (max_ps == -1)
2627*4882a593Smuzhiyun max_ps = state;
2628*4882a593Smuzhiyun
2629*4882a593Smuzhiyun if (total_latency_us > max_lat_us)
2630*4882a593Smuzhiyun max_lat_us = total_latency_us;
2631*4882a593Smuzhiyun }
2632*4882a593Smuzhiyun
2633*4882a593Smuzhiyun apste = 1;
2634*4882a593Smuzhiyun
2635*4882a593Smuzhiyun if (max_ps == -1) {
2636*4882a593Smuzhiyun dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2637*4882a593Smuzhiyun } else {
2638*4882a593Smuzhiyun dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2639*4882a593Smuzhiyun max_ps, max_lat_us, (int)sizeof(*table), table);
2640*4882a593Smuzhiyun }
2641*4882a593Smuzhiyun }
2642*4882a593Smuzhiyun
2643*4882a593Smuzhiyun ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2644*4882a593Smuzhiyun table, sizeof(*table), NULL);
2645*4882a593Smuzhiyun if (ret)
2646*4882a593Smuzhiyun dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
2647*4882a593Smuzhiyun
2648*4882a593Smuzhiyun kfree(table);
2649*4882a593Smuzhiyun return ret;
2650*4882a593Smuzhiyun }
2651*4882a593Smuzhiyun
nvme_set_latency_tolerance(struct device * dev,s32 val)2652*4882a593Smuzhiyun static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2653*4882a593Smuzhiyun {
2654*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2655*4882a593Smuzhiyun u64 latency;
2656*4882a593Smuzhiyun
2657*4882a593Smuzhiyun switch (val) {
2658*4882a593Smuzhiyun case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2659*4882a593Smuzhiyun case PM_QOS_LATENCY_ANY:
2660*4882a593Smuzhiyun latency = U64_MAX;
2661*4882a593Smuzhiyun break;
2662*4882a593Smuzhiyun
2663*4882a593Smuzhiyun default:
2664*4882a593Smuzhiyun latency = val;
2665*4882a593Smuzhiyun }
2666*4882a593Smuzhiyun
2667*4882a593Smuzhiyun if (ctrl->ps_max_latency_us != latency) {
2668*4882a593Smuzhiyun ctrl->ps_max_latency_us = latency;
2669*4882a593Smuzhiyun if (ctrl->state == NVME_CTRL_LIVE)
2670*4882a593Smuzhiyun nvme_configure_apst(ctrl);
2671*4882a593Smuzhiyun }
2672*4882a593Smuzhiyun }
2673*4882a593Smuzhiyun
2674*4882a593Smuzhiyun struct nvme_core_quirk_entry {
2675*4882a593Smuzhiyun /*
2676*4882a593Smuzhiyun * NVMe model and firmware strings are padded with spaces. For
2677*4882a593Smuzhiyun * simplicity, strings in the quirk table are padded with NULLs
2678*4882a593Smuzhiyun * instead.
2679*4882a593Smuzhiyun */
2680*4882a593Smuzhiyun u16 vid;
2681*4882a593Smuzhiyun const char *mn;
2682*4882a593Smuzhiyun const char *fr;
2683*4882a593Smuzhiyun unsigned long quirks;
2684*4882a593Smuzhiyun };
2685*4882a593Smuzhiyun
2686*4882a593Smuzhiyun static const struct nvme_core_quirk_entry core_quirks[] = {
2687*4882a593Smuzhiyun {
2688*4882a593Smuzhiyun /*
2689*4882a593Smuzhiyun * This Toshiba device seems to die using any APST states. See:
2690*4882a593Smuzhiyun * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2691*4882a593Smuzhiyun */
2692*4882a593Smuzhiyun .vid = 0x1179,
2693*4882a593Smuzhiyun .mn = "THNSF5256GPUK TOSHIBA",
2694*4882a593Smuzhiyun .quirks = NVME_QUIRK_NO_APST,
2695*4882a593Smuzhiyun },
2696*4882a593Smuzhiyun {
2697*4882a593Smuzhiyun /*
2698*4882a593Smuzhiyun * This LiteON CL1-3D*-Q11 firmware version has a race
2699*4882a593Smuzhiyun * condition associated with actions related to suspend to idle
2700*4882a593Smuzhiyun * LiteON has resolved the problem in future firmware
2701*4882a593Smuzhiyun */
2702*4882a593Smuzhiyun .vid = 0x14a4,
2703*4882a593Smuzhiyun .fr = "22301111",
2704*4882a593Smuzhiyun .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
2705*4882a593Smuzhiyun },
2706*4882a593Smuzhiyun {
2707*4882a593Smuzhiyun /*
2708*4882a593Smuzhiyun * This Kioxia CD6-V Series / HPE PE8030 device times out and
2709*4882a593Smuzhiyun * aborts I/O during any load, but more easily reproducible
2710*4882a593Smuzhiyun * with discards (fstrim).
2711*4882a593Smuzhiyun *
2712*4882a593Smuzhiyun * The device is left in a state where it is also not possible
2713*4882a593Smuzhiyun * to use "nvme set-feature" to disable APST, but booting with
2714*4882a593Smuzhiyun * nvme_core.default_ps_max_latency=0 works.
2715*4882a593Smuzhiyun */
2716*4882a593Smuzhiyun .vid = 0x1e0f,
2717*4882a593Smuzhiyun .mn = "KCD6XVUL6T40",
2718*4882a593Smuzhiyun .quirks = NVME_QUIRK_NO_APST,
2719*4882a593Smuzhiyun },
2720*4882a593Smuzhiyun {
2721*4882a593Smuzhiyun /*
2722*4882a593Smuzhiyun * The external Samsung X5 SSD fails initialization without a
2723*4882a593Smuzhiyun * delay before checking if it is ready and has a whole set of
2724*4882a593Smuzhiyun * other problems. To make this even more interesting, it
2725*4882a593Smuzhiyun * shares the PCI ID with internal Samsung 970 Evo Plus that
2726*4882a593Smuzhiyun * does not need or want these quirks.
2727*4882a593Smuzhiyun */
2728*4882a593Smuzhiyun .vid = 0x144d,
2729*4882a593Smuzhiyun .mn = "Samsung Portable SSD X5",
2730*4882a593Smuzhiyun .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
2731*4882a593Smuzhiyun NVME_QUIRK_NO_DEEPEST_PS |
2732*4882a593Smuzhiyun NVME_QUIRK_IGNORE_DEV_SUBNQN,
2733*4882a593Smuzhiyun }
2734*4882a593Smuzhiyun };
2735*4882a593Smuzhiyun
2736*4882a593Smuzhiyun /* match is null-terminated but idstr is space-padded. */
string_matches(const char * idstr,const char * match,size_t len)2737*4882a593Smuzhiyun static bool string_matches(const char *idstr, const char *match, size_t len)
2738*4882a593Smuzhiyun {
2739*4882a593Smuzhiyun size_t matchlen;
2740*4882a593Smuzhiyun
2741*4882a593Smuzhiyun if (!match)
2742*4882a593Smuzhiyun return true;
2743*4882a593Smuzhiyun
2744*4882a593Smuzhiyun matchlen = strlen(match);
2745*4882a593Smuzhiyun WARN_ON_ONCE(matchlen > len);
2746*4882a593Smuzhiyun
2747*4882a593Smuzhiyun if (memcmp(idstr, match, matchlen))
2748*4882a593Smuzhiyun return false;
2749*4882a593Smuzhiyun
2750*4882a593Smuzhiyun for (; matchlen < len; matchlen++)
2751*4882a593Smuzhiyun if (idstr[matchlen] != ' ')
2752*4882a593Smuzhiyun return false;
2753*4882a593Smuzhiyun
2754*4882a593Smuzhiyun return true;
2755*4882a593Smuzhiyun }
2756*4882a593Smuzhiyun
quirk_matches(const struct nvme_id_ctrl * id,const struct nvme_core_quirk_entry * q)2757*4882a593Smuzhiyun static bool quirk_matches(const struct nvme_id_ctrl *id,
2758*4882a593Smuzhiyun const struct nvme_core_quirk_entry *q)
2759*4882a593Smuzhiyun {
2760*4882a593Smuzhiyun return q->vid == le16_to_cpu(id->vid) &&
2761*4882a593Smuzhiyun string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2762*4882a593Smuzhiyun string_matches(id->fr, q->fr, sizeof(id->fr));
2763*4882a593Smuzhiyun }
2764*4882a593Smuzhiyun
nvme_init_subnqn(struct nvme_subsystem * subsys,struct nvme_ctrl * ctrl,struct nvme_id_ctrl * id)2765*4882a593Smuzhiyun static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2766*4882a593Smuzhiyun struct nvme_id_ctrl *id)
2767*4882a593Smuzhiyun {
2768*4882a593Smuzhiyun size_t nqnlen;
2769*4882a593Smuzhiyun int off;
2770*4882a593Smuzhiyun
2771*4882a593Smuzhiyun if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2772*4882a593Smuzhiyun nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2773*4882a593Smuzhiyun if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2774*4882a593Smuzhiyun strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2775*4882a593Smuzhiyun return;
2776*4882a593Smuzhiyun }
2777*4882a593Smuzhiyun
2778*4882a593Smuzhiyun if (ctrl->vs >= NVME_VS(1, 2, 1))
2779*4882a593Smuzhiyun dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2780*4882a593Smuzhiyun }
2781*4882a593Smuzhiyun
2782*4882a593Smuzhiyun /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
2783*4882a593Smuzhiyun off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
2784*4882a593Smuzhiyun "nqn.2014.08.org.nvmexpress:%04x%04x",
2785*4882a593Smuzhiyun le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
2786*4882a593Smuzhiyun memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
2787*4882a593Smuzhiyun off += sizeof(id->sn);
2788*4882a593Smuzhiyun memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
2789*4882a593Smuzhiyun off += sizeof(id->mn);
2790*4882a593Smuzhiyun memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2791*4882a593Smuzhiyun }
2792*4882a593Smuzhiyun
nvme_release_subsystem(struct device * dev)2793*4882a593Smuzhiyun static void nvme_release_subsystem(struct device *dev)
2794*4882a593Smuzhiyun {
2795*4882a593Smuzhiyun struct nvme_subsystem *subsys =
2796*4882a593Smuzhiyun container_of(dev, struct nvme_subsystem, dev);
2797*4882a593Smuzhiyun
2798*4882a593Smuzhiyun if (subsys->instance >= 0)
2799*4882a593Smuzhiyun ida_simple_remove(&nvme_instance_ida, subsys->instance);
2800*4882a593Smuzhiyun kfree(subsys);
2801*4882a593Smuzhiyun }
2802*4882a593Smuzhiyun
nvme_destroy_subsystem(struct kref * ref)2803*4882a593Smuzhiyun static void nvme_destroy_subsystem(struct kref *ref)
2804*4882a593Smuzhiyun {
2805*4882a593Smuzhiyun struct nvme_subsystem *subsys =
2806*4882a593Smuzhiyun container_of(ref, struct nvme_subsystem, ref);
2807*4882a593Smuzhiyun
2808*4882a593Smuzhiyun mutex_lock(&nvme_subsystems_lock);
2809*4882a593Smuzhiyun list_del(&subsys->entry);
2810*4882a593Smuzhiyun mutex_unlock(&nvme_subsystems_lock);
2811*4882a593Smuzhiyun
2812*4882a593Smuzhiyun ida_destroy(&subsys->ns_ida);
2813*4882a593Smuzhiyun device_del(&subsys->dev);
2814*4882a593Smuzhiyun put_device(&subsys->dev);
2815*4882a593Smuzhiyun }
2816*4882a593Smuzhiyun
nvme_put_subsystem(struct nvme_subsystem * subsys)2817*4882a593Smuzhiyun static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2818*4882a593Smuzhiyun {
2819*4882a593Smuzhiyun kref_put(&subsys->ref, nvme_destroy_subsystem);
2820*4882a593Smuzhiyun }
2821*4882a593Smuzhiyun
__nvme_find_get_subsystem(const char * subsysnqn)2822*4882a593Smuzhiyun static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2823*4882a593Smuzhiyun {
2824*4882a593Smuzhiyun struct nvme_subsystem *subsys;
2825*4882a593Smuzhiyun
2826*4882a593Smuzhiyun lockdep_assert_held(&nvme_subsystems_lock);
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun /*
2829*4882a593Smuzhiyun * Fail matches for discovery subsystems. This results
2830*4882a593Smuzhiyun * in each discovery controller bound to a unique subsystem.
2831*4882a593Smuzhiyun * This avoids issues with validating controller values
2832*4882a593Smuzhiyun * that can only be true when there is a single unique subsystem.
2833*4882a593Smuzhiyun * There may be multiple and completely independent entities
2834*4882a593Smuzhiyun * that provide discovery controllers.
2835*4882a593Smuzhiyun */
2836*4882a593Smuzhiyun if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2837*4882a593Smuzhiyun return NULL;
2838*4882a593Smuzhiyun
2839*4882a593Smuzhiyun list_for_each_entry(subsys, &nvme_subsystems, entry) {
2840*4882a593Smuzhiyun if (strcmp(subsys->subnqn, subsysnqn))
2841*4882a593Smuzhiyun continue;
2842*4882a593Smuzhiyun if (!kref_get_unless_zero(&subsys->ref))
2843*4882a593Smuzhiyun continue;
2844*4882a593Smuzhiyun return subsys;
2845*4882a593Smuzhiyun }
2846*4882a593Smuzhiyun
2847*4882a593Smuzhiyun return NULL;
2848*4882a593Smuzhiyun }
2849*4882a593Smuzhiyun
2850*4882a593Smuzhiyun #define SUBSYS_ATTR_RO(_name, _mode, _show) \
2851*4882a593Smuzhiyun struct device_attribute subsys_attr_##_name = \
2852*4882a593Smuzhiyun __ATTR(_name, _mode, _show, NULL)
2853*4882a593Smuzhiyun
nvme_subsys_show_nqn(struct device * dev,struct device_attribute * attr,char * buf)2854*4882a593Smuzhiyun static ssize_t nvme_subsys_show_nqn(struct device *dev,
2855*4882a593Smuzhiyun struct device_attribute *attr,
2856*4882a593Smuzhiyun char *buf)
2857*4882a593Smuzhiyun {
2858*4882a593Smuzhiyun struct nvme_subsystem *subsys =
2859*4882a593Smuzhiyun container_of(dev, struct nvme_subsystem, dev);
2860*4882a593Smuzhiyun
2861*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2862*4882a593Smuzhiyun }
2863*4882a593Smuzhiyun static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2864*4882a593Smuzhiyun
2865*4882a593Smuzhiyun #define nvme_subsys_show_str_function(field) \
2866*4882a593Smuzhiyun static ssize_t subsys_##field##_show(struct device *dev, \
2867*4882a593Smuzhiyun struct device_attribute *attr, char *buf) \
2868*4882a593Smuzhiyun { \
2869*4882a593Smuzhiyun struct nvme_subsystem *subsys = \
2870*4882a593Smuzhiyun container_of(dev, struct nvme_subsystem, dev); \
2871*4882a593Smuzhiyun return sysfs_emit(buf, "%.*s\n", \
2872*4882a593Smuzhiyun (int)sizeof(subsys->field), subsys->field); \
2873*4882a593Smuzhiyun } \
2874*4882a593Smuzhiyun static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2875*4882a593Smuzhiyun
2876*4882a593Smuzhiyun nvme_subsys_show_str_function(model);
2877*4882a593Smuzhiyun nvme_subsys_show_str_function(serial);
2878*4882a593Smuzhiyun nvme_subsys_show_str_function(firmware_rev);
2879*4882a593Smuzhiyun
2880*4882a593Smuzhiyun static struct attribute *nvme_subsys_attrs[] = {
2881*4882a593Smuzhiyun &subsys_attr_model.attr,
2882*4882a593Smuzhiyun &subsys_attr_serial.attr,
2883*4882a593Smuzhiyun &subsys_attr_firmware_rev.attr,
2884*4882a593Smuzhiyun &subsys_attr_subsysnqn.attr,
2885*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
2886*4882a593Smuzhiyun &subsys_attr_iopolicy.attr,
2887*4882a593Smuzhiyun #endif
2888*4882a593Smuzhiyun NULL,
2889*4882a593Smuzhiyun };
2890*4882a593Smuzhiyun
2891*4882a593Smuzhiyun static struct attribute_group nvme_subsys_attrs_group = {
2892*4882a593Smuzhiyun .attrs = nvme_subsys_attrs,
2893*4882a593Smuzhiyun };
2894*4882a593Smuzhiyun
2895*4882a593Smuzhiyun static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2896*4882a593Smuzhiyun &nvme_subsys_attrs_group,
2897*4882a593Smuzhiyun NULL,
2898*4882a593Smuzhiyun };
2899*4882a593Smuzhiyun
nvme_discovery_ctrl(struct nvme_ctrl * ctrl)2900*4882a593Smuzhiyun static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2901*4882a593Smuzhiyun {
2902*4882a593Smuzhiyun return ctrl->opts && ctrl->opts->discovery_nqn;
2903*4882a593Smuzhiyun }
2904*4882a593Smuzhiyun
nvme_validate_cntlid(struct nvme_subsystem * subsys,struct nvme_ctrl * ctrl,struct nvme_id_ctrl * id)2905*4882a593Smuzhiyun static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2906*4882a593Smuzhiyun struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2907*4882a593Smuzhiyun {
2908*4882a593Smuzhiyun struct nvme_ctrl *tmp;
2909*4882a593Smuzhiyun
2910*4882a593Smuzhiyun lockdep_assert_held(&nvme_subsystems_lock);
2911*4882a593Smuzhiyun
2912*4882a593Smuzhiyun list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
2913*4882a593Smuzhiyun if (nvme_state_terminal(tmp))
2914*4882a593Smuzhiyun continue;
2915*4882a593Smuzhiyun
2916*4882a593Smuzhiyun if (tmp->cntlid == ctrl->cntlid) {
2917*4882a593Smuzhiyun dev_err(ctrl->device,
2918*4882a593Smuzhiyun "Duplicate cntlid %u with %s, rejecting\n",
2919*4882a593Smuzhiyun ctrl->cntlid, dev_name(tmp->device));
2920*4882a593Smuzhiyun return false;
2921*4882a593Smuzhiyun }
2922*4882a593Smuzhiyun
2923*4882a593Smuzhiyun if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
2924*4882a593Smuzhiyun nvme_discovery_ctrl(ctrl))
2925*4882a593Smuzhiyun continue;
2926*4882a593Smuzhiyun
2927*4882a593Smuzhiyun dev_err(ctrl->device,
2928*4882a593Smuzhiyun "Subsystem does not support multiple controllers\n");
2929*4882a593Smuzhiyun return false;
2930*4882a593Smuzhiyun }
2931*4882a593Smuzhiyun
2932*4882a593Smuzhiyun return true;
2933*4882a593Smuzhiyun }
2934*4882a593Smuzhiyun
nvme_init_subsystem(struct nvme_ctrl * ctrl,struct nvme_id_ctrl * id)2935*4882a593Smuzhiyun static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2936*4882a593Smuzhiyun {
2937*4882a593Smuzhiyun struct nvme_subsystem *subsys, *found;
2938*4882a593Smuzhiyun int ret;
2939*4882a593Smuzhiyun
2940*4882a593Smuzhiyun subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2941*4882a593Smuzhiyun if (!subsys)
2942*4882a593Smuzhiyun return -ENOMEM;
2943*4882a593Smuzhiyun
2944*4882a593Smuzhiyun subsys->instance = -1;
2945*4882a593Smuzhiyun mutex_init(&subsys->lock);
2946*4882a593Smuzhiyun kref_init(&subsys->ref);
2947*4882a593Smuzhiyun INIT_LIST_HEAD(&subsys->ctrls);
2948*4882a593Smuzhiyun INIT_LIST_HEAD(&subsys->nsheads);
2949*4882a593Smuzhiyun nvme_init_subnqn(subsys, ctrl, id);
2950*4882a593Smuzhiyun memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2951*4882a593Smuzhiyun memcpy(subsys->model, id->mn, sizeof(subsys->model));
2952*4882a593Smuzhiyun subsys->vendor_id = le16_to_cpu(id->vid);
2953*4882a593Smuzhiyun subsys->cmic = id->cmic;
2954*4882a593Smuzhiyun subsys->awupf = le16_to_cpu(id->awupf);
2955*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
2956*4882a593Smuzhiyun subsys->iopolicy = NVME_IOPOLICY_NUMA;
2957*4882a593Smuzhiyun #endif
2958*4882a593Smuzhiyun
2959*4882a593Smuzhiyun subsys->dev.class = nvme_subsys_class;
2960*4882a593Smuzhiyun subsys->dev.release = nvme_release_subsystem;
2961*4882a593Smuzhiyun subsys->dev.groups = nvme_subsys_attrs_groups;
2962*4882a593Smuzhiyun dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
2963*4882a593Smuzhiyun device_initialize(&subsys->dev);
2964*4882a593Smuzhiyun
2965*4882a593Smuzhiyun mutex_lock(&nvme_subsystems_lock);
2966*4882a593Smuzhiyun found = __nvme_find_get_subsystem(subsys->subnqn);
2967*4882a593Smuzhiyun if (found) {
2968*4882a593Smuzhiyun put_device(&subsys->dev);
2969*4882a593Smuzhiyun subsys = found;
2970*4882a593Smuzhiyun
2971*4882a593Smuzhiyun if (!nvme_validate_cntlid(subsys, ctrl, id)) {
2972*4882a593Smuzhiyun ret = -EINVAL;
2973*4882a593Smuzhiyun goto out_put_subsystem;
2974*4882a593Smuzhiyun }
2975*4882a593Smuzhiyun } else {
2976*4882a593Smuzhiyun ret = device_add(&subsys->dev);
2977*4882a593Smuzhiyun if (ret) {
2978*4882a593Smuzhiyun dev_err(ctrl->device,
2979*4882a593Smuzhiyun "failed to register subsystem device.\n");
2980*4882a593Smuzhiyun put_device(&subsys->dev);
2981*4882a593Smuzhiyun goto out_unlock;
2982*4882a593Smuzhiyun }
2983*4882a593Smuzhiyun ida_init(&subsys->ns_ida);
2984*4882a593Smuzhiyun list_add_tail(&subsys->entry, &nvme_subsystems);
2985*4882a593Smuzhiyun }
2986*4882a593Smuzhiyun
2987*4882a593Smuzhiyun ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2988*4882a593Smuzhiyun dev_name(ctrl->device));
2989*4882a593Smuzhiyun if (ret) {
2990*4882a593Smuzhiyun dev_err(ctrl->device,
2991*4882a593Smuzhiyun "failed to create sysfs link from subsystem.\n");
2992*4882a593Smuzhiyun goto out_put_subsystem;
2993*4882a593Smuzhiyun }
2994*4882a593Smuzhiyun
2995*4882a593Smuzhiyun if (!found)
2996*4882a593Smuzhiyun subsys->instance = ctrl->instance;
2997*4882a593Smuzhiyun ctrl->subsys = subsys;
2998*4882a593Smuzhiyun list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2999*4882a593Smuzhiyun mutex_unlock(&nvme_subsystems_lock);
3000*4882a593Smuzhiyun return 0;
3001*4882a593Smuzhiyun
3002*4882a593Smuzhiyun out_put_subsystem:
3003*4882a593Smuzhiyun nvme_put_subsystem(subsys);
3004*4882a593Smuzhiyun out_unlock:
3005*4882a593Smuzhiyun mutex_unlock(&nvme_subsystems_lock);
3006*4882a593Smuzhiyun return ret;
3007*4882a593Smuzhiyun }
3008*4882a593Smuzhiyun
nvme_get_log(struct nvme_ctrl * ctrl,u32 nsid,u8 log_page,u8 lsp,u8 csi,void * log,size_t size,u64 offset)3009*4882a593Smuzhiyun int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
3010*4882a593Smuzhiyun void *log, size_t size, u64 offset)
3011*4882a593Smuzhiyun {
3012*4882a593Smuzhiyun struct nvme_command c = { };
3013*4882a593Smuzhiyun u32 dwlen = nvme_bytes_to_numd(size);
3014*4882a593Smuzhiyun
3015*4882a593Smuzhiyun c.get_log_page.opcode = nvme_admin_get_log_page;
3016*4882a593Smuzhiyun c.get_log_page.nsid = cpu_to_le32(nsid);
3017*4882a593Smuzhiyun c.get_log_page.lid = log_page;
3018*4882a593Smuzhiyun c.get_log_page.lsp = lsp;
3019*4882a593Smuzhiyun c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
3020*4882a593Smuzhiyun c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
3021*4882a593Smuzhiyun c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
3022*4882a593Smuzhiyun c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
3023*4882a593Smuzhiyun c.get_log_page.csi = csi;
3024*4882a593Smuzhiyun
3025*4882a593Smuzhiyun return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
3026*4882a593Smuzhiyun }
3027*4882a593Smuzhiyun
nvme_get_effects_log(struct nvme_ctrl * ctrl,u8 csi,struct nvme_effects_log ** log)3028*4882a593Smuzhiyun static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
3029*4882a593Smuzhiyun struct nvme_effects_log **log)
3030*4882a593Smuzhiyun {
3031*4882a593Smuzhiyun struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
3032*4882a593Smuzhiyun int ret;
3033*4882a593Smuzhiyun
3034*4882a593Smuzhiyun if (cel)
3035*4882a593Smuzhiyun goto out;
3036*4882a593Smuzhiyun
3037*4882a593Smuzhiyun cel = kzalloc(sizeof(*cel), GFP_KERNEL);
3038*4882a593Smuzhiyun if (!cel)
3039*4882a593Smuzhiyun return -ENOMEM;
3040*4882a593Smuzhiyun
3041*4882a593Smuzhiyun ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
3042*4882a593Smuzhiyun cel, sizeof(*cel), 0);
3043*4882a593Smuzhiyun if (ret) {
3044*4882a593Smuzhiyun kfree(cel);
3045*4882a593Smuzhiyun return ret;
3046*4882a593Smuzhiyun }
3047*4882a593Smuzhiyun
3048*4882a593Smuzhiyun xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
3049*4882a593Smuzhiyun out:
3050*4882a593Smuzhiyun *log = cel;
3051*4882a593Smuzhiyun return 0;
3052*4882a593Smuzhiyun }
3053*4882a593Smuzhiyun
3054*4882a593Smuzhiyun /*
3055*4882a593Smuzhiyun * Initialize the cached copies of the Identify data and various controller
3056*4882a593Smuzhiyun * register in our nvme_ctrl structure. This should be called as soon as
3057*4882a593Smuzhiyun * the admin queue is fully up and running.
3058*4882a593Smuzhiyun */
nvme_init_identify(struct nvme_ctrl * ctrl)3059*4882a593Smuzhiyun int nvme_init_identify(struct nvme_ctrl *ctrl)
3060*4882a593Smuzhiyun {
3061*4882a593Smuzhiyun struct nvme_id_ctrl *id;
3062*4882a593Smuzhiyun int ret, page_shift;
3063*4882a593Smuzhiyun u32 max_hw_sectors;
3064*4882a593Smuzhiyun bool prev_apst_enabled;
3065*4882a593Smuzhiyun
3066*4882a593Smuzhiyun ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
3067*4882a593Smuzhiyun if (ret) {
3068*4882a593Smuzhiyun dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
3069*4882a593Smuzhiyun return ret;
3070*4882a593Smuzhiyun }
3071*4882a593Smuzhiyun page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12;
3072*4882a593Smuzhiyun ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
3073*4882a593Smuzhiyun
3074*4882a593Smuzhiyun if (ctrl->vs >= NVME_VS(1, 1, 0))
3075*4882a593Smuzhiyun ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
3076*4882a593Smuzhiyun
3077*4882a593Smuzhiyun ret = nvme_identify_ctrl(ctrl, &id);
3078*4882a593Smuzhiyun if (ret) {
3079*4882a593Smuzhiyun dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
3080*4882a593Smuzhiyun return -EIO;
3081*4882a593Smuzhiyun }
3082*4882a593Smuzhiyun
3083*4882a593Smuzhiyun if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
3084*4882a593Smuzhiyun ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
3085*4882a593Smuzhiyun if (ret < 0)
3086*4882a593Smuzhiyun goto out_free;
3087*4882a593Smuzhiyun }
3088*4882a593Smuzhiyun
3089*4882a593Smuzhiyun if (!(ctrl->ops->flags & NVME_F_FABRICS))
3090*4882a593Smuzhiyun ctrl->cntlid = le16_to_cpu(id->cntlid);
3091*4882a593Smuzhiyun
3092*4882a593Smuzhiyun if (!ctrl->identified) {
3093*4882a593Smuzhiyun int i;
3094*4882a593Smuzhiyun
3095*4882a593Smuzhiyun /*
3096*4882a593Smuzhiyun * Check for quirks. Quirk can depend on firmware version,
3097*4882a593Smuzhiyun * so, in principle, the set of quirks present can change
3098*4882a593Smuzhiyun * across a reset. As a possible future enhancement, we
3099*4882a593Smuzhiyun * could re-scan for quirks every time we reinitialize
3100*4882a593Smuzhiyun * the device, but we'd have to make sure that the driver
3101*4882a593Smuzhiyun * behaves intelligently if the quirks change.
3102*4882a593Smuzhiyun */
3103*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
3104*4882a593Smuzhiyun if (quirk_matches(id, &core_quirks[i]))
3105*4882a593Smuzhiyun ctrl->quirks |= core_quirks[i].quirks;
3106*4882a593Smuzhiyun }
3107*4882a593Smuzhiyun
3108*4882a593Smuzhiyun ret = nvme_init_subsystem(ctrl, id);
3109*4882a593Smuzhiyun if (ret)
3110*4882a593Smuzhiyun goto out_free;
3111*4882a593Smuzhiyun }
3112*4882a593Smuzhiyun memcpy(ctrl->subsys->firmware_rev, id->fr,
3113*4882a593Smuzhiyun sizeof(ctrl->subsys->firmware_rev));
3114*4882a593Smuzhiyun
3115*4882a593Smuzhiyun if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
3116*4882a593Smuzhiyun dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
3117*4882a593Smuzhiyun ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
3118*4882a593Smuzhiyun }
3119*4882a593Smuzhiyun
3120*4882a593Smuzhiyun ctrl->crdt[0] = le16_to_cpu(id->crdt1);
3121*4882a593Smuzhiyun ctrl->crdt[1] = le16_to_cpu(id->crdt2);
3122*4882a593Smuzhiyun ctrl->crdt[2] = le16_to_cpu(id->crdt3);
3123*4882a593Smuzhiyun
3124*4882a593Smuzhiyun ctrl->oacs = le16_to_cpu(id->oacs);
3125*4882a593Smuzhiyun ctrl->oncs = le16_to_cpu(id->oncs);
3126*4882a593Smuzhiyun ctrl->mtfa = le16_to_cpu(id->mtfa);
3127*4882a593Smuzhiyun ctrl->oaes = le32_to_cpu(id->oaes);
3128*4882a593Smuzhiyun ctrl->wctemp = le16_to_cpu(id->wctemp);
3129*4882a593Smuzhiyun ctrl->cctemp = le16_to_cpu(id->cctemp);
3130*4882a593Smuzhiyun
3131*4882a593Smuzhiyun atomic_set(&ctrl->abort_limit, id->acl + 1);
3132*4882a593Smuzhiyun ctrl->vwc = id->vwc;
3133*4882a593Smuzhiyun if (id->mdts)
3134*4882a593Smuzhiyun max_hw_sectors = 1 << (id->mdts + page_shift - 9);
3135*4882a593Smuzhiyun else
3136*4882a593Smuzhiyun max_hw_sectors = UINT_MAX;
3137*4882a593Smuzhiyun ctrl->max_hw_sectors =
3138*4882a593Smuzhiyun min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
3139*4882a593Smuzhiyun
3140*4882a593Smuzhiyun nvme_set_queue_limits(ctrl, ctrl->admin_q);
3141*4882a593Smuzhiyun ctrl->sgls = le32_to_cpu(id->sgls);
3142*4882a593Smuzhiyun ctrl->kas = le16_to_cpu(id->kas);
3143*4882a593Smuzhiyun ctrl->max_namespaces = le32_to_cpu(id->mnan);
3144*4882a593Smuzhiyun ctrl->ctratt = le32_to_cpu(id->ctratt);
3145*4882a593Smuzhiyun
3146*4882a593Smuzhiyun if (id->rtd3e) {
3147*4882a593Smuzhiyun /* us -> s */
3148*4882a593Smuzhiyun u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
3149*4882a593Smuzhiyun
3150*4882a593Smuzhiyun ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
3151*4882a593Smuzhiyun shutdown_timeout, 60);
3152*4882a593Smuzhiyun
3153*4882a593Smuzhiyun if (ctrl->shutdown_timeout != shutdown_timeout)
3154*4882a593Smuzhiyun dev_info(ctrl->device,
3155*4882a593Smuzhiyun "Shutdown timeout set to %u seconds\n",
3156*4882a593Smuzhiyun ctrl->shutdown_timeout);
3157*4882a593Smuzhiyun } else
3158*4882a593Smuzhiyun ctrl->shutdown_timeout = shutdown_timeout;
3159*4882a593Smuzhiyun
3160*4882a593Smuzhiyun ctrl->npss = id->npss;
3161*4882a593Smuzhiyun ctrl->apsta = id->apsta;
3162*4882a593Smuzhiyun prev_apst_enabled = ctrl->apst_enabled;
3163*4882a593Smuzhiyun if (ctrl->quirks & NVME_QUIRK_NO_APST) {
3164*4882a593Smuzhiyun if (force_apst && id->apsta) {
3165*4882a593Smuzhiyun dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
3166*4882a593Smuzhiyun ctrl->apst_enabled = true;
3167*4882a593Smuzhiyun } else {
3168*4882a593Smuzhiyun ctrl->apst_enabled = false;
3169*4882a593Smuzhiyun }
3170*4882a593Smuzhiyun } else {
3171*4882a593Smuzhiyun ctrl->apst_enabled = id->apsta;
3172*4882a593Smuzhiyun }
3173*4882a593Smuzhiyun memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
3174*4882a593Smuzhiyun
3175*4882a593Smuzhiyun if (ctrl->ops->flags & NVME_F_FABRICS) {
3176*4882a593Smuzhiyun ctrl->icdoff = le16_to_cpu(id->icdoff);
3177*4882a593Smuzhiyun ctrl->ioccsz = le32_to_cpu(id->ioccsz);
3178*4882a593Smuzhiyun ctrl->iorcsz = le32_to_cpu(id->iorcsz);
3179*4882a593Smuzhiyun ctrl->maxcmd = le16_to_cpu(id->maxcmd);
3180*4882a593Smuzhiyun
3181*4882a593Smuzhiyun /*
3182*4882a593Smuzhiyun * In fabrics we need to verify the cntlid matches the
3183*4882a593Smuzhiyun * admin connect
3184*4882a593Smuzhiyun */
3185*4882a593Smuzhiyun if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
3186*4882a593Smuzhiyun dev_err(ctrl->device,
3187*4882a593Smuzhiyun "Mismatching cntlid: Connect %u vs Identify "
3188*4882a593Smuzhiyun "%u, rejecting\n",
3189*4882a593Smuzhiyun ctrl->cntlid, le16_to_cpu(id->cntlid));
3190*4882a593Smuzhiyun ret = -EINVAL;
3191*4882a593Smuzhiyun goto out_free;
3192*4882a593Smuzhiyun }
3193*4882a593Smuzhiyun
3194*4882a593Smuzhiyun if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
3195*4882a593Smuzhiyun dev_err(ctrl->device,
3196*4882a593Smuzhiyun "keep-alive support is mandatory for fabrics\n");
3197*4882a593Smuzhiyun ret = -EINVAL;
3198*4882a593Smuzhiyun goto out_free;
3199*4882a593Smuzhiyun }
3200*4882a593Smuzhiyun } else {
3201*4882a593Smuzhiyun ctrl->hmpre = le32_to_cpu(id->hmpre);
3202*4882a593Smuzhiyun ctrl->hmmin = le32_to_cpu(id->hmmin);
3203*4882a593Smuzhiyun ctrl->hmminds = le32_to_cpu(id->hmminds);
3204*4882a593Smuzhiyun ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
3205*4882a593Smuzhiyun }
3206*4882a593Smuzhiyun
3207*4882a593Smuzhiyun ret = nvme_mpath_init_identify(ctrl, id);
3208*4882a593Smuzhiyun kfree(id);
3209*4882a593Smuzhiyun
3210*4882a593Smuzhiyun if (ret < 0)
3211*4882a593Smuzhiyun return ret;
3212*4882a593Smuzhiyun
3213*4882a593Smuzhiyun if (ctrl->apst_enabled && !prev_apst_enabled)
3214*4882a593Smuzhiyun dev_pm_qos_expose_latency_tolerance(ctrl->device);
3215*4882a593Smuzhiyun else if (!ctrl->apst_enabled && prev_apst_enabled)
3216*4882a593Smuzhiyun dev_pm_qos_hide_latency_tolerance(ctrl->device);
3217*4882a593Smuzhiyun
3218*4882a593Smuzhiyun ret = nvme_configure_apst(ctrl);
3219*4882a593Smuzhiyun if (ret < 0)
3220*4882a593Smuzhiyun return ret;
3221*4882a593Smuzhiyun
3222*4882a593Smuzhiyun ret = nvme_configure_timestamp(ctrl);
3223*4882a593Smuzhiyun if (ret < 0)
3224*4882a593Smuzhiyun return ret;
3225*4882a593Smuzhiyun
3226*4882a593Smuzhiyun ret = nvme_configure_directives(ctrl);
3227*4882a593Smuzhiyun if (ret < 0)
3228*4882a593Smuzhiyun return ret;
3229*4882a593Smuzhiyun
3230*4882a593Smuzhiyun ret = nvme_configure_acre(ctrl);
3231*4882a593Smuzhiyun if (ret < 0)
3232*4882a593Smuzhiyun return ret;
3233*4882a593Smuzhiyun
3234*4882a593Smuzhiyun if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
3235*4882a593Smuzhiyun /*
3236*4882a593Smuzhiyun * Do not return errors unless we are in a controller reset,
3237*4882a593Smuzhiyun * the controller works perfectly fine without hwmon.
3238*4882a593Smuzhiyun */
3239*4882a593Smuzhiyun ret = nvme_hwmon_init(ctrl);
3240*4882a593Smuzhiyun if (ret == -EINTR)
3241*4882a593Smuzhiyun return ret;
3242*4882a593Smuzhiyun }
3243*4882a593Smuzhiyun
3244*4882a593Smuzhiyun ctrl->identified = true;
3245*4882a593Smuzhiyun
3246*4882a593Smuzhiyun return 0;
3247*4882a593Smuzhiyun
3248*4882a593Smuzhiyun out_free:
3249*4882a593Smuzhiyun kfree(id);
3250*4882a593Smuzhiyun return ret;
3251*4882a593Smuzhiyun }
3252*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_init_identify);
3253*4882a593Smuzhiyun
nvme_dev_open(struct inode * inode,struct file * file)3254*4882a593Smuzhiyun static int nvme_dev_open(struct inode *inode, struct file *file)
3255*4882a593Smuzhiyun {
3256*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
3257*4882a593Smuzhiyun container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3258*4882a593Smuzhiyun
3259*4882a593Smuzhiyun switch (ctrl->state) {
3260*4882a593Smuzhiyun case NVME_CTRL_LIVE:
3261*4882a593Smuzhiyun break;
3262*4882a593Smuzhiyun default:
3263*4882a593Smuzhiyun return -EWOULDBLOCK;
3264*4882a593Smuzhiyun }
3265*4882a593Smuzhiyun
3266*4882a593Smuzhiyun nvme_get_ctrl(ctrl);
3267*4882a593Smuzhiyun if (!try_module_get(ctrl->ops->module)) {
3268*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
3269*4882a593Smuzhiyun return -EINVAL;
3270*4882a593Smuzhiyun }
3271*4882a593Smuzhiyun
3272*4882a593Smuzhiyun file->private_data = ctrl;
3273*4882a593Smuzhiyun return 0;
3274*4882a593Smuzhiyun }
3275*4882a593Smuzhiyun
nvme_dev_release(struct inode * inode,struct file * file)3276*4882a593Smuzhiyun static int nvme_dev_release(struct inode *inode, struct file *file)
3277*4882a593Smuzhiyun {
3278*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
3279*4882a593Smuzhiyun container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3280*4882a593Smuzhiyun
3281*4882a593Smuzhiyun module_put(ctrl->ops->module);
3282*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
3283*4882a593Smuzhiyun return 0;
3284*4882a593Smuzhiyun }
3285*4882a593Smuzhiyun
nvme_dev_user_cmd(struct nvme_ctrl * ctrl,void __user * argp)3286*4882a593Smuzhiyun static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
3287*4882a593Smuzhiyun {
3288*4882a593Smuzhiyun struct nvme_ns *ns;
3289*4882a593Smuzhiyun int ret;
3290*4882a593Smuzhiyun
3291*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
3292*4882a593Smuzhiyun if (list_empty(&ctrl->namespaces)) {
3293*4882a593Smuzhiyun ret = -ENOTTY;
3294*4882a593Smuzhiyun goto out_unlock;
3295*4882a593Smuzhiyun }
3296*4882a593Smuzhiyun
3297*4882a593Smuzhiyun ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
3298*4882a593Smuzhiyun if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
3299*4882a593Smuzhiyun dev_warn(ctrl->device,
3300*4882a593Smuzhiyun "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
3301*4882a593Smuzhiyun ret = -EINVAL;
3302*4882a593Smuzhiyun goto out_unlock;
3303*4882a593Smuzhiyun }
3304*4882a593Smuzhiyun
3305*4882a593Smuzhiyun dev_warn(ctrl->device,
3306*4882a593Smuzhiyun "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
3307*4882a593Smuzhiyun kref_get(&ns->kref);
3308*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
3309*4882a593Smuzhiyun
3310*4882a593Smuzhiyun ret = nvme_user_cmd(ctrl, ns, argp);
3311*4882a593Smuzhiyun nvme_put_ns(ns);
3312*4882a593Smuzhiyun return ret;
3313*4882a593Smuzhiyun
3314*4882a593Smuzhiyun out_unlock:
3315*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
3316*4882a593Smuzhiyun return ret;
3317*4882a593Smuzhiyun }
3318*4882a593Smuzhiyun
nvme_dev_ioctl(struct file * file,unsigned int cmd,unsigned long arg)3319*4882a593Smuzhiyun static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
3320*4882a593Smuzhiyun unsigned long arg)
3321*4882a593Smuzhiyun {
3322*4882a593Smuzhiyun struct nvme_ctrl *ctrl = file->private_data;
3323*4882a593Smuzhiyun void __user *argp = (void __user *)arg;
3324*4882a593Smuzhiyun
3325*4882a593Smuzhiyun switch (cmd) {
3326*4882a593Smuzhiyun case NVME_IOCTL_ADMIN_CMD:
3327*4882a593Smuzhiyun return nvme_user_cmd(ctrl, NULL, argp);
3328*4882a593Smuzhiyun case NVME_IOCTL_ADMIN64_CMD:
3329*4882a593Smuzhiyun return nvme_user_cmd64(ctrl, NULL, argp);
3330*4882a593Smuzhiyun case NVME_IOCTL_IO_CMD:
3331*4882a593Smuzhiyun return nvme_dev_user_cmd(ctrl, argp);
3332*4882a593Smuzhiyun case NVME_IOCTL_RESET:
3333*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
3334*4882a593Smuzhiyun return -EACCES;
3335*4882a593Smuzhiyun dev_warn(ctrl->device, "resetting controller\n");
3336*4882a593Smuzhiyun return nvme_reset_ctrl_sync(ctrl);
3337*4882a593Smuzhiyun case NVME_IOCTL_SUBSYS_RESET:
3338*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
3339*4882a593Smuzhiyun return -EACCES;
3340*4882a593Smuzhiyun return nvme_reset_subsystem(ctrl);
3341*4882a593Smuzhiyun case NVME_IOCTL_RESCAN:
3342*4882a593Smuzhiyun if (!capable(CAP_SYS_ADMIN))
3343*4882a593Smuzhiyun return -EACCES;
3344*4882a593Smuzhiyun nvme_queue_scan(ctrl);
3345*4882a593Smuzhiyun return 0;
3346*4882a593Smuzhiyun default:
3347*4882a593Smuzhiyun return -ENOTTY;
3348*4882a593Smuzhiyun }
3349*4882a593Smuzhiyun }
3350*4882a593Smuzhiyun
3351*4882a593Smuzhiyun static const struct file_operations nvme_dev_fops = {
3352*4882a593Smuzhiyun .owner = THIS_MODULE,
3353*4882a593Smuzhiyun .open = nvme_dev_open,
3354*4882a593Smuzhiyun .release = nvme_dev_release,
3355*4882a593Smuzhiyun .unlocked_ioctl = nvme_dev_ioctl,
3356*4882a593Smuzhiyun .compat_ioctl = compat_ptr_ioctl,
3357*4882a593Smuzhiyun };
3358*4882a593Smuzhiyun
nvme_sysfs_reset(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3359*4882a593Smuzhiyun static ssize_t nvme_sysfs_reset(struct device *dev,
3360*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
3361*4882a593Smuzhiyun size_t count)
3362*4882a593Smuzhiyun {
3363*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3364*4882a593Smuzhiyun int ret;
3365*4882a593Smuzhiyun
3366*4882a593Smuzhiyun ret = nvme_reset_ctrl_sync(ctrl);
3367*4882a593Smuzhiyun if (ret < 0)
3368*4882a593Smuzhiyun return ret;
3369*4882a593Smuzhiyun return count;
3370*4882a593Smuzhiyun }
3371*4882a593Smuzhiyun static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3372*4882a593Smuzhiyun
nvme_sysfs_rescan(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3373*4882a593Smuzhiyun static ssize_t nvme_sysfs_rescan(struct device *dev,
3374*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
3375*4882a593Smuzhiyun size_t count)
3376*4882a593Smuzhiyun {
3377*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3378*4882a593Smuzhiyun
3379*4882a593Smuzhiyun nvme_queue_scan(ctrl);
3380*4882a593Smuzhiyun return count;
3381*4882a593Smuzhiyun }
3382*4882a593Smuzhiyun static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
3383*4882a593Smuzhiyun
dev_to_ns_head(struct device * dev)3384*4882a593Smuzhiyun static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
3385*4882a593Smuzhiyun {
3386*4882a593Smuzhiyun struct gendisk *disk = dev_to_disk(dev);
3387*4882a593Smuzhiyun
3388*4882a593Smuzhiyun if (disk->fops == &nvme_fops)
3389*4882a593Smuzhiyun return nvme_get_ns_from_dev(dev)->head;
3390*4882a593Smuzhiyun else
3391*4882a593Smuzhiyun return disk->private_data;
3392*4882a593Smuzhiyun }
3393*4882a593Smuzhiyun
wwid_show(struct device * dev,struct device_attribute * attr,char * buf)3394*4882a593Smuzhiyun static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
3395*4882a593Smuzhiyun char *buf)
3396*4882a593Smuzhiyun {
3397*4882a593Smuzhiyun struct nvme_ns_head *head = dev_to_ns_head(dev);
3398*4882a593Smuzhiyun struct nvme_ns_ids *ids = &head->ids;
3399*4882a593Smuzhiyun struct nvme_subsystem *subsys = head->subsys;
3400*4882a593Smuzhiyun int serial_len = sizeof(subsys->serial);
3401*4882a593Smuzhiyun int model_len = sizeof(subsys->model);
3402*4882a593Smuzhiyun
3403*4882a593Smuzhiyun if (!uuid_is_null(&ids->uuid))
3404*4882a593Smuzhiyun return sysfs_emit(buf, "uuid.%pU\n", &ids->uuid);
3405*4882a593Smuzhiyun
3406*4882a593Smuzhiyun if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
3407*4882a593Smuzhiyun return sysfs_emit(buf, "eui.%16phN\n", ids->nguid);
3408*4882a593Smuzhiyun
3409*4882a593Smuzhiyun if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
3410*4882a593Smuzhiyun return sysfs_emit(buf, "eui.%8phN\n", ids->eui64);
3411*4882a593Smuzhiyun
3412*4882a593Smuzhiyun while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
3413*4882a593Smuzhiyun subsys->serial[serial_len - 1] == '\0'))
3414*4882a593Smuzhiyun serial_len--;
3415*4882a593Smuzhiyun while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
3416*4882a593Smuzhiyun subsys->model[model_len - 1] == '\0'))
3417*4882a593Smuzhiyun model_len--;
3418*4882a593Smuzhiyun
3419*4882a593Smuzhiyun return sysfs_emit(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
3420*4882a593Smuzhiyun serial_len, subsys->serial, model_len, subsys->model,
3421*4882a593Smuzhiyun head->ns_id);
3422*4882a593Smuzhiyun }
3423*4882a593Smuzhiyun static DEVICE_ATTR_RO(wwid);
3424*4882a593Smuzhiyun
nguid_show(struct device * dev,struct device_attribute * attr,char * buf)3425*4882a593Smuzhiyun static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
3426*4882a593Smuzhiyun char *buf)
3427*4882a593Smuzhiyun {
3428*4882a593Smuzhiyun return sysfs_emit(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
3429*4882a593Smuzhiyun }
3430*4882a593Smuzhiyun static DEVICE_ATTR_RO(nguid);
3431*4882a593Smuzhiyun
uuid_show(struct device * dev,struct device_attribute * attr,char * buf)3432*4882a593Smuzhiyun static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
3433*4882a593Smuzhiyun char *buf)
3434*4882a593Smuzhiyun {
3435*4882a593Smuzhiyun struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
3436*4882a593Smuzhiyun
3437*4882a593Smuzhiyun /* For backward compatibility expose the NGUID to userspace if
3438*4882a593Smuzhiyun * we have no UUID set
3439*4882a593Smuzhiyun */
3440*4882a593Smuzhiyun if (uuid_is_null(&ids->uuid)) {
3441*4882a593Smuzhiyun dev_warn_ratelimited(dev,
3442*4882a593Smuzhiyun "No UUID available providing old NGUID\n");
3443*4882a593Smuzhiyun return sysfs_emit(buf, "%pU\n", ids->nguid);
3444*4882a593Smuzhiyun }
3445*4882a593Smuzhiyun return sysfs_emit(buf, "%pU\n", &ids->uuid);
3446*4882a593Smuzhiyun }
3447*4882a593Smuzhiyun static DEVICE_ATTR_RO(uuid);
3448*4882a593Smuzhiyun
eui_show(struct device * dev,struct device_attribute * attr,char * buf)3449*4882a593Smuzhiyun static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
3450*4882a593Smuzhiyun char *buf)
3451*4882a593Smuzhiyun {
3452*4882a593Smuzhiyun return sysfs_emit(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
3453*4882a593Smuzhiyun }
3454*4882a593Smuzhiyun static DEVICE_ATTR_RO(eui);
3455*4882a593Smuzhiyun
nsid_show(struct device * dev,struct device_attribute * attr,char * buf)3456*4882a593Smuzhiyun static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
3457*4882a593Smuzhiyun char *buf)
3458*4882a593Smuzhiyun {
3459*4882a593Smuzhiyun return sysfs_emit(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
3460*4882a593Smuzhiyun }
3461*4882a593Smuzhiyun static DEVICE_ATTR_RO(nsid);
3462*4882a593Smuzhiyun
3463*4882a593Smuzhiyun static struct attribute *nvme_ns_id_attrs[] = {
3464*4882a593Smuzhiyun &dev_attr_wwid.attr,
3465*4882a593Smuzhiyun &dev_attr_uuid.attr,
3466*4882a593Smuzhiyun &dev_attr_nguid.attr,
3467*4882a593Smuzhiyun &dev_attr_eui.attr,
3468*4882a593Smuzhiyun &dev_attr_nsid.attr,
3469*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
3470*4882a593Smuzhiyun &dev_attr_ana_grpid.attr,
3471*4882a593Smuzhiyun &dev_attr_ana_state.attr,
3472*4882a593Smuzhiyun #endif
3473*4882a593Smuzhiyun NULL,
3474*4882a593Smuzhiyun };
3475*4882a593Smuzhiyun
nvme_ns_id_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)3476*4882a593Smuzhiyun static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
3477*4882a593Smuzhiyun struct attribute *a, int n)
3478*4882a593Smuzhiyun {
3479*4882a593Smuzhiyun struct device *dev = container_of(kobj, struct device, kobj);
3480*4882a593Smuzhiyun struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
3481*4882a593Smuzhiyun
3482*4882a593Smuzhiyun if (a == &dev_attr_uuid.attr) {
3483*4882a593Smuzhiyun if (uuid_is_null(&ids->uuid) &&
3484*4882a593Smuzhiyun !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
3485*4882a593Smuzhiyun return 0;
3486*4882a593Smuzhiyun }
3487*4882a593Smuzhiyun if (a == &dev_attr_nguid.attr) {
3488*4882a593Smuzhiyun if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
3489*4882a593Smuzhiyun return 0;
3490*4882a593Smuzhiyun }
3491*4882a593Smuzhiyun if (a == &dev_attr_eui.attr) {
3492*4882a593Smuzhiyun if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
3493*4882a593Smuzhiyun return 0;
3494*4882a593Smuzhiyun }
3495*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
3496*4882a593Smuzhiyun if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
3497*4882a593Smuzhiyun if (dev_to_disk(dev)->fops != &nvme_fops) /* per-path attr */
3498*4882a593Smuzhiyun return 0;
3499*4882a593Smuzhiyun if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
3500*4882a593Smuzhiyun return 0;
3501*4882a593Smuzhiyun }
3502*4882a593Smuzhiyun #endif
3503*4882a593Smuzhiyun return a->mode;
3504*4882a593Smuzhiyun }
3505*4882a593Smuzhiyun
3506*4882a593Smuzhiyun static const struct attribute_group nvme_ns_id_attr_group = {
3507*4882a593Smuzhiyun .attrs = nvme_ns_id_attrs,
3508*4882a593Smuzhiyun .is_visible = nvme_ns_id_attrs_are_visible,
3509*4882a593Smuzhiyun };
3510*4882a593Smuzhiyun
3511*4882a593Smuzhiyun const struct attribute_group *nvme_ns_id_attr_groups[] = {
3512*4882a593Smuzhiyun &nvme_ns_id_attr_group,
3513*4882a593Smuzhiyun #ifdef CONFIG_NVM
3514*4882a593Smuzhiyun &nvme_nvm_attr_group,
3515*4882a593Smuzhiyun #endif
3516*4882a593Smuzhiyun NULL,
3517*4882a593Smuzhiyun };
3518*4882a593Smuzhiyun
3519*4882a593Smuzhiyun #define nvme_show_str_function(field) \
3520*4882a593Smuzhiyun static ssize_t field##_show(struct device *dev, \
3521*4882a593Smuzhiyun struct device_attribute *attr, char *buf) \
3522*4882a593Smuzhiyun { \
3523*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
3524*4882a593Smuzhiyun return sysfs_emit(buf, "%.*s\n", \
3525*4882a593Smuzhiyun (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
3526*4882a593Smuzhiyun } \
3527*4882a593Smuzhiyun static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3528*4882a593Smuzhiyun
3529*4882a593Smuzhiyun nvme_show_str_function(model);
3530*4882a593Smuzhiyun nvme_show_str_function(serial);
3531*4882a593Smuzhiyun nvme_show_str_function(firmware_rev);
3532*4882a593Smuzhiyun
3533*4882a593Smuzhiyun #define nvme_show_int_function(field) \
3534*4882a593Smuzhiyun static ssize_t field##_show(struct device *dev, \
3535*4882a593Smuzhiyun struct device_attribute *attr, char *buf) \
3536*4882a593Smuzhiyun { \
3537*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
3538*4882a593Smuzhiyun return sysfs_emit(buf, "%d\n", ctrl->field); \
3539*4882a593Smuzhiyun } \
3540*4882a593Smuzhiyun static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3541*4882a593Smuzhiyun
3542*4882a593Smuzhiyun nvme_show_int_function(cntlid);
3543*4882a593Smuzhiyun nvme_show_int_function(numa_node);
3544*4882a593Smuzhiyun nvme_show_int_function(queue_count);
3545*4882a593Smuzhiyun nvme_show_int_function(sqsize);
3546*4882a593Smuzhiyun
nvme_sysfs_delete(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3547*4882a593Smuzhiyun static ssize_t nvme_sysfs_delete(struct device *dev,
3548*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
3549*4882a593Smuzhiyun size_t count)
3550*4882a593Smuzhiyun {
3551*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3552*4882a593Smuzhiyun
3553*4882a593Smuzhiyun if (device_remove_file_self(dev, attr))
3554*4882a593Smuzhiyun nvme_delete_ctrl_sync(ctrl);
3555*4882a593Smuzhiyun return count;
3556*4882a593Smuzhiyun }
3557*4882a593Smuzhiyun static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
3558*4882a593Smuzhiyun
nvme_sysfs_show_transport(struct device * dev,struct device_attribute * attr,char * buf)3559*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_transport(struct device *dev,
3560*4882a593Smuzhiyun struct device_attribute *attr,
3561*4882a593Smuzhiyun char *buf)
3562*4882a593Smuzhiyun {
3563*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3564*4882a593Smuzhiyun
3565*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
3566*4882a593Smuzhiyun }
3567*4882a593Smuzhiyun static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
3568*4882a593Smuzhiyun
nvme_sysfs_show_state(struct device * dev,struct device_attribute * attr,char * buf)3569*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_state(struct device *dev,
3570*4882a593Smuzhiyun struct device_attribute *attr,
3571*4882a593Smuzhiyun char *buf)
3572*4882a593Smuzhiyun {
3573*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3574*4882a593Smuzhiyun static const char *const state_name[] = {
3575*4882a593Smuzhiyun [NVME_CTRL_NEW] = "new",
3576*4882a593Smuzhiyun [NVME_CTRL_LIVE] = "live",
3577*4882a593Smuzhiyun [NVME_CTRL_RESETTING] = "resetting",
3578*4882a593Smuzhiyun [NVME_CTRL_CONNECTING] = "connecting",
3579*4882a593Smuzhiyun [NVME_CTRL_DELETING] = "deleting",
3580*4882a593Smuzhiyun [NVME_CTRL_DELETING_NOIO]= "deleting (no IO)",
3581*4882a593Smuzhiyun [NVME_CTRL_DEAD] = "dead",
3582*4882a593Smuzhiyun };
3583*4882a593Smuzhiyun
3584*4882a593Smuzhiyun if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
3585*4882a593Smuzhiyun state_name[ctrl->state])
3586*4882a593Smuzhiyun return sysfs_emit(buf, "%s\n", state_name[ctrl->state]);
3587*4882a593Smuzhiyun
3588*4882a593Smuzhiyun return sysfs_emit(buf, "unknown state\n");
3589*4882a593Smuzhiyun }
3590*4882a593Smuzhiyun
3591*4882a593Smuzhiyun static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
3592*4882a593Smuzhiyun
nvme_sysfs_show_subsysnqn(struct device * dev,struct device_attribute * attr,char * buf)3593*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
3594*4882a593Smuzhiyun struct device_attribute *attr,
3595*4882a593Smuzhiyun char *buf)
3596*4882a593Smuzhiyun {
3597*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3598*4882a593Smuzhiyun
3599*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
3600*4882a593Smuzhiyun }
3601*4882a593Smuzhiyun static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
3602*4882a593Smuzhiyun
nvme_sysfs_show_hostnqn(struct device * dev,struct device_attribute * attr,char * buf)3603*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_hostnqn(struct device *dev,
3604*4882a593Smuzhiyun struct device_attribute *attr,
3605*4882a593Smuzhiyun char *buf)
3606*4882a593Smuzhiyun {
3607*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3608*4882a593Smuzhiyun
3609*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->opts->host->nqn);
3610*4882a593Smuzhiyun }
3611*4882a593Smuzhiyun static DEVICE_ATTR(hostnqn, S_IRUGO, nvme_sysfs_show_hostnqn, NULL);
3612*4882a593Smuzhiyun
nvme_sysfs_show_hostid(struct device * dev,struct device_attribute * attr,char * buf)3613*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_hostid(struct device *dev,
3614*4882a593Smuzhiyun struct device_attribute *attr,
3615*4882a593Smuzhiyun char *buf)
3616*4882a593Smuzhiyun {
3617*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3618*4882a593Smuzhiyun
3619*4882a593Smuzhiyun return snprintf(buf, PAGE_SIZE, "%pU\n", &ctrl->opts->host->id);
3620*4882a593Smuzhiyun }
3621*4882a593Smuzhiyun static DEVICE_ATTR(hostid, S_IRUGO, nvme_sysfs_show_hostid, NULL);
3622*4882a593Smuzhiyun
nvme_sysfs_show_address(struct device * dev,struct device_attribute * attr,char * buf)3623*4882a593Smuzhiyun static ssize_t nvme_sysfs_show_address(struct device *dev,
3624*4882a593Smuzhiyun struct device_attribute *attr,
3625*4882a593Smuzhiyun char *buf)
3626*4882a593Smuzhiyun {
3627*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3628*4882a593Smuzhiyun
3629*4882a593Smuzhiyun return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
3630*4882a593Smuzhiyun }
3631*4882a593Smuzhiyun static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
3632*4882a593Smuzhiyun
nvme_ctrl_loss_tmo_show(struct device * dev,struct device_attribute * attr,char * buf)3633*4882a593Smuzhiyun static ssize_t nvme_ctrl_loss_tmo_show(struct device *dev,
3634*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
3635*4882a593Smuzhiyun {
3636*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3637*4882a593Smuzhiyun struct nvmf_ctrl_options *opts = ctrl->opts;
3638*4882a593Smuzhiyun
3639*4882a593Smuzhiyun if (ctrl->opts->max_reconnects == -1)
3640*4882a593Smuzhiyun return sysfs_emit(buf, "off\n");
3641*4882a593Smuzhiyun return sysfs_emit(buf, "%d\n",
3642*4882a593Smuzhiyun opts->max_reconnects * opts->reconnect_delay);
3643*4882a593Smuzhiyun }
3644*4882a593Smuzhiyun
nvme_ctrl_loss_tmo_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3645*4882a593Smuzhiyun static ssize_t nvme_ctrl_loss_tmo_store(struct device *dev,
3646*4882a593Smuzhiyun struct device_attribute *attr, const char *buf, size_t count)
3647*4882a593Smuzhiyun {
3648*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3649*4882a593Smuzhiyun struct nvmf_ctrl_options *opts = ctrl->opts;
3650*4882a593Smuzhiyun int ctrl_loss_tmo, err;
3651*4882a593Smuzhiyun
3652*4882a593Smuzhiyun err = kstrtoint(buf, 10, &ctrl_loss_tmo);
3653*4882a593Smuzhiyun if (err)
3654*4882a593Smuzhiyun return -EINVAL;
3655*4882a593Smuzhiyun
3656*4882a593Smuzhiyun else if (ctrl_loss_tmo < 0)
3657*4882a593Smuzhiyun opts->max_reconnects = -1;
3658*4882a593Smuzhiyun else
3659*4882a593Smuzhiyun opts->max_reconnects = DIV_ROUND_UP(ctrl_loss_tmo,
3660*4882a593Smuzhiyun opts->reconnect_delay);
3661*4882a593Smuzhiyun return count;
3662*4882a593Smuzhiyun }
3663*4882a593Smuzhiyun static DEVICE_ATTR(ctrl_loss_tmo, S_IRUGO | S_IWUSR,
3664*4882a593Smuzhiyun nvme_ctrl_loss_tmo_show, nvme_ctrl_loss_tmo_store);
3665*4882a593Smuzhiyun
nvme_ctrl_reconnect_delay_show(struct device * dev,struct device_attribute * attr,char * buf)3666*4882a593Smuzhiyun static ssize_t nvme_ctrl_reconnect_delay_show(struct device *dev,
3667*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
3668*4882a593Smuzhiyun {
3669*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3670*4882a593Smuzhiyun
3671*4882a593Smuzhiyun if (ctrl->opts->reconnect_delay == -1)
3672*4882a593Smuzhiyun return sysfs_emit(buf, "off\n");
3673*4882a593Smuzhiyun return sysfs_emit(buf, "%d\n", ctrl->opts->reconnect_delay);
3674*4882a593Smuzhiyun }
3675*4882a593Smuzhiyun
nvme_ctrl_reconnect_delay_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3676*4882a593Smuzhiyun static ssize_t nvme_ctrl_reconnect_delay_store(struct device *dev,
3677*4882a593Smuzhiyun struct device_attribute *attr, const char *buf, size_t count)
3678*4882a593Smuzhiyun {
3679*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3680*4882a593Smuzhiyun unsigned int v;
3681*4882a593Smuzhiyun int err;
3682*4882a593Smuzhiyun
3683*4882a593Smuzhiyun err = kstrtou32(buf, 10, &v);
3684*4882a593Smuzhiyun if (err)
3685*4882a593Smuzhiyun return err;
3686*4882a593Smuzhiyun
3687*4882a593Smuzhiyun ctrl->opts->reconnect_delay = v;
3688*4882a593Smuzhiyun return count;
3689*4882a593Smuzhiyun }
3690*4882a593Smuzhiyun static DEVICE_ATTR(reconnect_delay, S_IRUGO | S_IWUSR,
3691*4882a593Smuzhiyun nvme_ctrl_reconnect_delay_show, nvme_ctrl_reconnect_delay_store);
3692*4882a593Smuzhiyun
3693*4882a593Smuzhiyun static struct attribute *nvme_dev_attrs[] = {
3694*4882a593Smuzhiyun &dev_attr_reset_controller.attr,
3695*4882a593Smuzhiyun &dev_attr_rescan_controller.attr,
3696*4882a593Smuzhiyun &dev_attr_model.attr,
3697*4882a593Smuzhiyun &dev_attr_serial.attr,
3698*4882a593Smuzhiyun &dev_attr_firmware_rev.attr,
3699*4882a593Smuzhiyun &dev_attr_cntlid.attr,
3700*4882a593Smuzhiyun &dev_attr_delete_controller.attr,
3701*4882a593Smuzhiyun &dev_attr_transport.attr,
3702*4882a593Smuzhiyun &dev_attr_subsysnqn.attr,
3703*4882a593Smuzhiyun &dev_attr_address.attr,
3704*4882a593Smuzhiyun &dev_attr_state.attr,
3705*4882a593Smuzhiyun &dev_attr_numa_node.attr,
3706*4882a593Smuzhiyun &dev_attr_queue_count.attr,
3707*4882a593Smuzhiyun &dev_attr_sqsize.attr,
3708*4882a593Smuzhiyun &dev_attr_hostnqn.attr,
3709*4882a593Smuzhiyun &dev_attr_hostid.attr,
3710*4882a593Smuzhiyun &dev_attr_ctrl_loss_tmo.attr,
3711*4882a593Smuzhiyun &dev_attr_reconnect_delay.attr,
3712*4882a593Smuzhiyun NULL
3713*4882a593Smuzhiyun };
3714*4882a593Smuzhiyun
nvme_dev_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)3715*4882a593Smuzhiyun static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
3716*4882a593Smuzhiyun struct attribute *a, int n)
3717*4882a593Smuzhiyun {
3718*4882a593Smuzhiyun struct device *dev = container_of(kobj, struct device, kobj);
3719*4882a593Smuzhiyun struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3720*4882a593Smuzhiyun
3721*4882a593Smuzhiyun if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
3722*4882a593Smuzhiyun return 0;
3723*4882a593Smuzhiyun if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
3724*4882a593Smuzhiyun return 0;
3725*4882a593Smuzhiyun if (a == &dev_attr_hostnqn.attr && !ctrl->opts)
3726*4882a593Smuzhiyun return 0;
3727*4882a593Smuzhiyun if (a == &dev_attr_hostid.attr && !ctrl->opts)
3728*4882a593Smuzhiyun return 0;
3729*4882a593Smuzhiyun if (a == &dev_attr_ctrl_loss_tmo.attr && !ctrl->opts)
3730*4882a593Smuzhiyun return 0;
3731*4882a593Smuzhiyun if (a == &dev_attr_reconnect_delay.attr && !ctrl->opts)
3732*4882a593Smuzhiyun return 0;
3733*4882a593Smuzhiyun
3734*4882a593Smuzhiyun return a->mode;
3735*4882a593Smuzhiyun }
3736*4882a593Smuzhiyun
3737*4882a593Smuzhiyun static struct attribute_group nvme_dev_attrs_group = {
3738*4882a593Smuzhiyun .attrs = nvme_dev_attrs,
3739*4882a593Smuzhiyun .is_visible = nvme_dev_attrs_are_visible,
3740*4882a593Smuzhiyun };
3741*4882a593Smuzhiyun
3742*4882a593Smuzhiyun static const struct attribute_group *nvme_dev_attr_groups[] = {
3743*4882a593Smuzhiyun &nvme_dev_attrs_group,
3744*4882a593Smuzhiyun NULL,
3745*4882a593Smuzhiyun };
3746*4882a593Smuzhiyun
nvme_find_ns_head(struct nvme_subsystem * subsys,unsigned nsid)3747*4882a593Smuzhiyun static struct nvme_ns_head *nvme_find_ns_head(struct nvme_subsystem *subsys,
3748*4882a593Smuzhiyun unsigned nsid)
3749*4882a593Smuzhiyun {
3750*4882a593Smuzhiyun struct nvme_ns_head *h;
3751*4882a593Smuzhiyun
3752*4882a593Smuzhiyun lockdep_assert_held(&subsys->lock);
3753*4882a593Smuzhiyun
3754*4882a593Smuzhiyun list_for_each_entry(h, &subsys->nsheads, entry) {
3755*4882a593Smuzhiyun if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
3756*4882a593Smuzhiyun return h;
3757*4882a593Smuzhiyun }
3758*4882a593Smuzhiyun
3759*4882a593Smuzhiyun return NULL;
3760*4882a593Smuzhiyun }
3761*4882a593Smuzhiyun
nvme_subsys_check_duplicate_ids(struct nvme_subsystem * subsys,struct nvme_ns_ids * ids)3762*4882a593Smuzhiyun static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys,
3763*4882a593Smuzhiyun struct nvme_ns_ids *ids)
3764*4882a593Smuzhiyun {
3765*4882a593Smuzhiyun struct nvme_ns_head *h;
3766*4882a593Smuzhiyun
3767*4882a593Smuzhiyun lockdep_assert_held(&subsys->lock);
3768*4882a593Smuzhiyun
3769*4882a593Smuzhiyun list_for_each_entry(h, &subsys->nsheads, entry) {
3770*4882a593Smuzhiyun if (nvme_ns_ids_valid(ids) && nvme_ns_ids_equal(ids, &h->ids))
3771*4882a593Smuzhiyun return -EINVAL;
3772*4882a593Smuzhiyun }
3773*4882a593Smuzhiyun
3774*4882a593Smuzhiyun return 0;
3775*4882a593Smuzhiyun }
3776*4882a593Smuzhiyun
nvme_alloc_ns_head(struct nvme_ctrl * ctrl,unsigned nsid,struct nvme_ns_ids * ids)3777*4882a593Smuzhiyun static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
3778*4882a593Smuzhiyun unsigned nsid, struct nvme_ns_ids *ids)
3779*4882a593Smuzhiyun {
3780*4882a593Smuzhiyun struct nvme_ns_head *head;
3781*4882a593Smuzhiyun size_t size = sizeof(*head);
3782*4882a593Smuzhiyun int ret = -ENOMEM;
3783*4882a593Smuzhiyun
3784*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
3785*4882a593Smuzhiyun size += num_possible_nodes() * sizeof(struct nvme_ns *);
3786*4882a593Smuzhiyun #endif
3787*4882a593Smuzhiyun
3788*4882a593Smuzhiyun head = kzalloc(size, GFP_KERNEL);
3789*4882a593Smuzhiyun if (!head)
3790*4882a593Smuzhiyun goto out;
3791*4882a593Smuzhiyun ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3792*4882a593Smuzhiyun if (ret < 0)
3793*4882a593Smuzhiyun goto out_free_head;
3794*4882a593Smuzhiyun head->instance = ret;
3795*4882a593Smuzhiyun INIT_LIST_HEAD(&head->list);
3796*4882a593Smuzhiyun ret = init_srcu_struct(&head->srcu);
3797*4882a593Smuzhiyun if (ret)
3798*4882a593Smuzhiyun goto out_ida_remove;
3799*4882a593Smuzhiyun head->subsys = ctrl->subsys;
3800*4882a593Smuzhiyun head->ns_id = nsid;
3801*4882a593Smuzhiyun head->ids = *ids;
3802*4882a593Smuzhiyun kref_init(&head->ref);
3803*4882a593Smuzhiyun
3804*4882a593Smuzhiyun ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &head->ids);
3805*4882a593Smuzhiyun if (ret) {
3806*4882a593Smuzhiyun dev_err(ctrl->device,
3807*4882a593Smuzhiyun "duplicate IDs for nsid %d\n", nsid);
3808*4882a593Smuzhiyun goto out_cleanup_srcu;
3809*4882a593Smuzhiyun }
3810*4882a593Smuzhiyun
3811*4882a593Smuzhiyun if (head->ids.csi) {
3812*4882a593Smuzhiyun ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3813*4882a593Smuzhiyun if (ret)
3814*4882a593Smuzhiyun goto out_cleanup_srcu;
3815*4882a593Smuzhiyun } else
3816*4882a593Smuzhiyun head->effects = ctrl->effects;
3817*4882a593Smuzhiyun
3818*4882a593Smuzhiyun ret = nvme_mpath_alloc_disk(ctrl, head);
3819*4882a593Smuzhiyun if (ret)
3820*4882a593Smuzhiyun goto out_cleanup_srcu;
3821*4882a593Smuzhiyun
3822*4882a593Smuzhiyun list_add_tail(&head->entry, &ctrl->subsys->nsheads);
3823*4882a593Smuzhiyun
3824*4882a593Smuzhiyun kref_get(&ctrl->subsys->ref);
3825*4882a593Smuzhiyun
3826*4882a593Smuzhiyun return head;
3827*4882a593Smuzhiyun out_cleanup_srcu:
3828*4882a593Smuzhiyun cleanup_srcu_struct(&head->srcu);
3829*4882a593Smuzhiyun out_ida_remove:
3830*4882a593Smuzhiyun ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3831*4882a593Smuzhiyun out_free_head:
3832*4882a593Smuzhiyun kfree(head);
3833*4882a593Smuzhiyun out:
3834*4882a593Smuzhiyun if (ret > 0)
3835*4882a593Smuzhiyun ret = blk_status_to_errno(nvme_error_status(ret));
3836*4882a593Smuzhiyun return ERR_PTR(ret);
3837*4882a593Smuzhiyun }
3838*4882a593Smuzhiyun
nvme_init_ns_head(struct nvme_ns * ns,unsigned nsid,struct nvme_ns_ids * ids,bool is_shared)3839*4882a593Smuzhiyun static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
3840*4882a593Smuzhiyun struct nvme_ns_ids *ids, bool is_shared)
3841*4882a593Smuzhiyun {
3842*4882a593Smuzhiyun struct nvme_ctrl *ctrl = ns->ctrl;
3843*4882a593Smuzhiyun struct nvme_ns_head *head = NULL;
3844*4882a593Smuzhiyun int ret = 0;
3845*4882a593Smuzhiyun
3846*4882a593Smuzhiyun mutex_lock(&ctrl->subsys->lock);
3847*4882a593Smuzhiyun head = nvme_find_ns_head(ctrl->subsys, nsid);
3848*4882a593Smuzhiyun if (!head) {
3849*4882a593Smuzhiyun head = nvme_alloc_ns_head(ctrl, nsid, ids);
3850*4882a593Smuzhiyun if (IS_ERR(head)) {
3851*4882a593Smuzhiyun ret = PTR_ERR(head);
3852*4882a593Smuzhiyun goto out_unlock;
3853*4882a593Smuzhiyun }
3854*4882a593Smuzhiyun head->shared = is_shared;
3855*4882a593Smuzhiyun } else {
3856*4882a593Smuzhiyun ret = -EINVAL;
3857*4882a593Smuzhiyun if (!is_shared || !head->shared) {
3858*4882a593Smuzhiyun dev_err(ctrl->device,
3859*4882a593Smuzhiyun "Duplicate unshared namespace %d\n", nsid);
3860*4882a593Smuzhiyun goto out_put_ns_head;
3861*4882a593Smuzhiyun }
3862*4882a593Smuzhiyun if (!nvme_ns_ids_equal(&head->ids, ids)) {
3863*4882a593Smuzhiyun dev_err(ctrl->device,
3864*4882a593Smuzhiyun "IDs don't match for shared namespace %d\n",
3865*4882a593Smuzhiyun nsid);
3866*4882a593Smuzhiyun goto out_put_ns_head;
3867*4882a593Smuzhiyun }
3868*4882a593Smuzhiyun }
3869*4882a593Smuzhiyun
3870*4882a593Smuzhiyun list_add_tail(&ns->siblings, &head->list);
3871*4882a593Smuzhiyun ns->head = head;
3872*4882a593Smuzhiyun mutex_unlock(&ctrl->subsys->lock);
3873*4882a593Smuzhiyun return 0;
3874*4882a593Smuzhiyun
3875*4882a593Smuzhiyun out_put_ns_head:
3876*4882a593Smuzhiyun nvme_put_ns_head(head);
3877*4882a593Smuzhiyun out_unlock:
3878*4882a593Smuzhiyun mutex_unlock(&ctrl->subsys->lock);
3879*4882a593Smuzhiyun return ret;
3880*4882a593Smuzhiyun }
3881*4882a593Smuzhiyun
nvme_find_get_ns(struct nvme_ctrl * ctrl,unsigned nsid)3882*4882a593Smuzhiyun struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3883*4882a593Smuzhiyun {
3884*4882a593Smuzhiyun struct nvme_ns *ns, *ret = NULL;
3885*4882a593Smuzhiyun
3886*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
3887*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list) {
3888*4882a593Smuzhiyun if (ns->head->ns_id == nsid) {
3889*4882a593Smuzhiyun if (!kref_get_unless_zero(&ns->kref))
3890*4882a593Smuzhiyun continue;
3891*4882a593Smuzhiyun ret = ns;
3892*4882a593Smuzhiyun break;
3893*4882a593Smuzhiyun }
3894*4882a593Smuzhiyun if (ns->head->ns_id > nsid)
3895*4882a593Smuzhiyun break;
3896*4882a593Smuzhiyun }
3897*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
3898*4882a593Smuzhiyun return ret;
3899*4882a593Smuzhiyun }
3900*4882a593Smuzhiyun EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
3901*4882a593Smuzhiyun
3902*4882a593Smuzhiyun /*
3903*4882a593Smuzhiyun * Add the namespace to the controller list while keeping the list ordered.
3904*4882a593Smuzhiyun */
nvme_ns_add_to_ctrl_list(struct nvme_ns * ns)3905*4882a593Smuzhiyun static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
3906*4882a593Smuzhiyun {
3907*4882a593Smuzhiyun struct nvme_ns *tmp;
3908*4882a593Smuzhiyun
3909*4882a593Smuzhiyun list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
3910*4882a593Smuzhiyun if (tmp->head->ns_id < ns->head->ns_id) {
3911*4882a593Smuzhiyun list_add(&ns->list, &tmp->list);
3912*4882a593Smuzhiyun return;
3913*4882a593Smuzhiyun }
3914*4882a593Smuzhiyun }
3915*4882a593Smuzhiyun list_add(&ns->list, &ns->ctrl->namespaces);
3916*4882a593Smuzhiyun }
3917*4882a593Smuzhiyun
nvme_alloc_ns(struct nvme_ctrl * ctrl,unsigned nsid,struct nvme_ns_ids * ids)3918*4882a593Smuzhiyun static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid,
3919*4882a593Smuzhiyun struct nvme_ns_ids *ids)
3920*4882a593Smuzhiyun {
3921*4882a593Smuzhiyun struct nvme_ns *ns;
3922*4882a593Smuzhiyun struct gendisk *disk;
3923*4882a593Smuzhiyun struct nvme_id_ns *id;
3924*4882a593Smuzhiyun char disk_name[DISK_NAME_LEN];
3925*4882a593Smuzhiyun int node = ctrl->numa_node, flags = GENHD_FL_EXT_DEVT, ret;
3926*4882a593Smuzhiyun
3927*4882a593Smuzhiyun if (nvme_identify_ns(ctrl, nsid, ids, &id))
3928*4882a593Smuzhiyun return;
3929*4882a593Smuzhiyun
3930*4882a593Smuzhiyun ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3931*4882a593Smuzhiyun if (!ns)
3932*4882a593Smuzhiyun goto out_free_id;
3933*4882a593Smuzhiyun
3934*4882a593Smuzhiyun ns->queue = blk_mq_init_queue(ctrl->tagset);
3935*4882a593Smuzhiyun if (IS_ERR(ns->queue))
3936*4882a593Smuzhiyun goto out_free_ns;
3937*4882a593Smuzhiyun
3938*4882a593Smuzhiyun if (ctrl->opts && ctrl->opts->data_digest)
3939*4882a593Smuzhiyun blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
3940*4882a593Smuzhiyun
3941*4882a593Smuzhiyun blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
3942*4882a593Smuzhiyun if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3943*4882a593Smuzhiyun blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3944*4882a593Smuzhiyun
3945*4882a593Smuzhiyun ns->queue->queuedata = ns;
3946*4882a593Smuzhiyun ns->ctrl = ctrl;
3947*4882a593Smuzhiyun kref_init(&ns->kref);
3948*4882a593Smuzhiyun
3949*4882a593Smuzhiyun ret = nvme_init_ns_head(ns, nsid, ids, id->nmic & NVME_NS_NMIC_SHARED);
3950*4882a593Smuzhiyun if (ret)
3951*4882a593Smuzhiyun goto out_free_queue;
3952*4882a593Smuzhiyun nvme_set_disk_name(disk_name, ns, ctrl, &flags);
3953*4882a593Smuzhiyun
3954*4882a593Smuzhiyun disk = alloc_disk_node(0, node);
3955*4882a593Smuzhiyun if (!disk)
3956*4882a593Smuzhiyun goto out_unlink_ns;
3957*4882a593Smuzhiyun
3958*4882a593Smuzhiyun disk->fops = &nvme_fops;
3959*4882a593Smuzhiyun disk->private_data = ns;
3960*4882a593Smuzhiyun disk->queue = ns->queue;
3961*4882a593Smuzhiyun disk->flags = flags;
3962*4882a593Smuzhiyun memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3963*4882a593Smuzhiyun ns->disk = disk;
3964*4882a593Smuzhiyun
3965*4882a593Smuzhiyun if (nvme_update_ns_info(ns, id))
3966*4882a593Smuzhiyun goto out_put_disk;
3967*4882a593Smuzhiyun
3968*4882a593Smuzhiyun if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
3969*4882a593Smuzhiyun ret = nvme_nvm_register(ns, disk_name, node);
3970*4882a593Smuzhiyun if (ret) {
3971*4882a593Smuzhiyun dev_warn(ctrl->device, "LightNVM init failure\n");
3972*4882a593Smuzhiyun goto out_put_disk;
3973*4882a593Smuzhiyun }
3974*4882a593Smuzhiyun }
3975*4882a593Smuzhiyun
3976*4882a593Smuzhiyun down_write(&ctrl->namespaces_rwsem);
3977*4882a593Smuzhiyun nvme_ns_add_to_ctrl_list(ns);
3978*4882a593Smuzhiyun up_write(&ctrl->namespaces_rwsem);
3979*4882a593Smuzhiyun nvme_get_ctrl(ctrl);
3980*4882a593Smuzhiyun
3981*4882a593Smuzhiyun device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
3982*4882a593Smuzhiyun
3983*4882a593Smuzhiyun nvme_mpath_add_disk(ns, id);
3984*4882a593Smuzhiyun nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
3985*4882a593Smuzhiyun kfree(id);
3986*4882a593Smuzhiyun
3987*4882a593Smuzhiyun return;
3988*4882a593Smuzhiyun out_put_disk:
3989*4882a593Smuzhiyun /* prevent double queue cleanup */
3990*4882a593Smuzhiyun ns->disk->queue = NULL;
3991*4882a593Smuzhiyun put_disk(ns->disk);
3992*4882a593Smuzhiyun out_unlink_ns:
3993*4882a593Smuzhiyun mutex_lock(&ctrl->subsys->lock);
3994*4882a593Smuzhiyun list_del_rcu(&ns->siblings);
3995*4882a593Smuzhiyun if (list_empty(&ns->head->list))
3996*4882a593Smuzhiyun list_del_init(&ns->head->entry);
3997*4882a593Smuzhiyun mutex_unlock(&ctrl->subsys->lock);
3998*4882a593Smuzhiyun nvme_put_ns_head(ns->head);
3999*4882a593Smuzhiyun out_free_queue:
4000*4882a593Smuzhiyun blk_cleanup_queue(ns->queue);
4001*4882a593Smuzhiyun out_free_ns:
4002*4882a593Smuzhiyun kfree(ns);
4003*4882a593Smuzhiyun out_free_id:
4004*4882a593Smuzhiyun kfree(id);
4005*4882a593Smuzhiyun }
4006*4882a593Smuzhiyun
nvme_ns_remove(struct nvme_ns * ns)4007*4882a593Smuzhiyun static void nvme_ns_remove(struct nvme_ns *ns)
4008*4882a593Smuzhiyun {
4009*4882a593Smuzhiyun if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
4010*4882a593Smuzhiyun return;
4011*4882a593Smuzhiyun
4012*4882a593Smuzhiyun set_capacity(ns->disk, 0);
4013*4882a593Smuzhiyun nvme_fault_inject_fini(&ns->fault_inject);
4014*4882a593Smuzhiyun
4015*4882a593Smuzhiyun mutex_lock(&ns->ctrl->subsys->lock);
4016*4882a593Smuzhiyun list_del_rcu(&ns->siblings);
4017*4882a593Smuzhiyun if (list_empty(&ns->head->list))
4018*4882a593Smuzhiyun list_del_init(&ns->head->entry);
4019*4882a593Smuzhiyun mutex_unlock(&ns->ctrl->subsys->lock);
4020*4882a593Smuzhiyun
4021*4882a593Smuzhiyun synchronize_rcu(); /* guarantee not available in head->list */
4022*4882a593Smuzhiyun nvme_mpath_clear_current_path(ns);
4023*4882a593Smuzhiyun synchronize_srcu(&ns->head->srcu); /* wait for concurrent submissions */
4024*4882a593Smuzhiyun
4025*4882a593Smuzhiyun if (ns->disk->flags & GENHD_FL_UP) {
4026*4882a593Smuzhiyun del_gendisk(ns->disk);
4027*4882a593Smuzhiyun blk_cleanup_queue(ns->queue);
4028*4882a593Smuzhiyun if (blk_get_integrity(ns->disk))
4029*4882a593Smuzhiyun blk_integrity_unregister(ns->disk);
4030*4882a593Smuzhiyun }
4031*4882a593Smuzhiyun
4032*4882a593Smuzhiyun down_write(&ns->ctrl->namespaces_rwsem);
4033*4882a593Smuzhiyun list_del_init(&ns->list);
4034*4882a593Smuzhiyun up_write(&ns->ctrl->namespaces_rwsem);
4035*4882a593Smuzhiyun
4036*4882a593Smuzhiyun nvme_mpath_check_last_path(ns);
4037*4882a593Smuzhiyun nvme_put_ns(ns);
4038*4882a593Smuzhiyun }
4039*4882a593Smuzhiyun
nvme_ns_remove_by_nsid(struct nvme_ctrl * ctrl,u32 nsid)4040*4882a593Smuzhiyun static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
4041*4882a593Smuzhiyun {
4042*4882a593Smuzhiyun struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
4043*4882a593Smuzhiyun
4044*4882a593Smuzhiyun if (ns) {
4045*4882a593Smuzhiyun nvme_ns_remove(ns);
4046*4882a593Smuzhiyun nvme_put_ns(ns);
4047*4882a593Smuzhiyun }
4048*4882a593Smuzhiyun }
4049*4882a593Smuzhiyun
nvme_validate_ns(struct nvme_ns * ns,struct nvme_ns_ids * ids)4050*4882a593Smuzhiyun static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_ids *ids)
4051*4882a593Smuzhiyun {
4052*4882a593Smuzhiyun struct nvme_id_ns *id;
4053*4882a593Smuzhiyun int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
4054*4882a593Smuzhiyun
4055*4882a593Smuzhiyun if (test_bit(NVME_NS_DEAD, &ns->flags))
4056*4882a593Smuzhiyun goto out;
4057*4882a593Smuzhiyun
4058*4882a593Smuzhiyun ret = nvme_identify_ns(ns->ctrl, ns->head->ns_id, ids, &id);
4059*4882a593Smuzhiyun if (ret)
4060*4882a593Smuzhiyun goto out;
4061*4882a593Smuzhiyun
4062*4882a593Smuzhiyun ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
4063*4882a593Smuzhiyun if (!nvme_ns_ids_equal(&ns->head->ids, ids)) {
4064*4882a593Smuzhiyun dev_err(ns->ctrl->device,
4065*4882a593Smuzhiyun "identifiers changed for nsid %d\n", ns->head->ns_id);
4066*4882a593Smuzhiyun goto out_free_id;
4067*4882a593Smuzhiyun }
4068*4882a593Smuzhiyun
4069*4882a593Smuzhiyun ret = nvme_update_ns_info(ns, id);
4070*4882a593Smuzhiyun
4071*4882a593Smuzhiyun out_free_id:
4072*4882a593Smuzhiyun kfree(id);
4073*4882a593Smuzhiyun out:
4074*4882a593Smuzhiyun /*
4075*4882a593Smuzhiyun * Only remove the namespace if we got a fatal error back from the
4076*4882a593Smuzhiyun * device, otherwise ignore the error and just move on.
4077*4882a593Smuzhiyun *
4078*4882a593Smuzhiyun * TODO: we should probably schedule a delayed retry here.
4079*4882a593Smuzhiyun */
4080*4882a593Smuzhiyun if (ret > 0 && (ret & NVME_SC_DNR))
4081*4882a593Smuzhiyun nvme_ns_remove(ns);
4082*4882a593Smuzhiyun else
4083*4882a593Smuzhiyun revalidate_disk_size(ns->disk, true);
4084*4882a593Smuzhiyun }
4085*4882a593Smuzhiyun
nvme_validate_or_alloc_ns(struct nvme_ctrl * ctrl,unsigned nsid)4086*4882a593Smuzhiyun static void nvme_validate_or_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
4087*4882a593Smuzhiyun {
4088*4882a593Smuzhiyun struct nvme_ns_ids ids = { };
4089*4882a593Smuzhiyun struct nvme_ns *ns;
4090*4882a593Smuzhiyun
4091*4882a593Smuzhiyun if (nvme_identify_ns_descs(ctrl, nsid, &ids))
4092*4882a593Smuzhiyun return;
4093*4882a593Smuzhiyun
4094*4882a593Smuzhiyun ns = nvme_find_get_ns(ctrl, nsid);
4095*4882a593Smuzhiyun if (ns) {
4096*4882a593Smuzhiyun nvme_validate_ns(ns, &ids);
4097*4882a593Smuzhiyun nvme_put_ns(ns);
4098*4882a593Smuzhiyun return;
4099*4882a593Smuzhiyun }
4100*4882a593Smuzhiyun
4101*4882a593Smuzhiyun switch (ids.csi) {
4102*4882a593Smuzhiyun case NVME_CSI_NVM:
4103*4882a593Smuzhiyun nvme_alloc_ns(ctrl, nsid, &ids);
4104*4882a593Smuzhiyun break;
4105*4882a593Smuzhiyun case NVME_CSI_ZNS:
4106*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
4107*4882a593Smuzhiyun dev_warn(ctrl->device,
4108*4882a593Smuzhiyun "nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
4109*4882a593Smuzhiyun nsid);
4110*4882a593Smuzhiyun break;
4111*4882a593Smuzhiyun }
4112*4882a593Smuzhiyun if (!nvme_multi_css(ctrl)) {
4113*4882a593Smuzhiyun dev_warn(ctrl->device,
4114*4882a593Smuzhiyun "command set not reported for nsid: %d\n",
4115*4882a593Smuzhiyun nsid);
4116*4882a593Smuzhiyun break;
4117*4882a593Smuzhiyun }
4118*4882a593Smuzhiyun nvme_alloc_ns(ctrl, nsid, &ids);
4119*4882a593Smuzhiyun break;
4120*4882a593Smuzhiyun default:
4121*4882a593Smuzhiyun dev_warn(ctrl->device, "unknown csi %u for nsid %u\n",
4122*4882a593Smuzhiyun ids.csi, nsid);
4123*4882a593Smuzhiyun break;
4124*4882a593Smuzhiyun }
4125*4882a593Smuzhiyun }
4126*4882a593Smuzhiyun
nvme_remove_invalid_namespaces(struct nvme_ctrl * ctrl,unsigned nsid)4127*4882a593Smuzhiyun static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
4128*4882a593Smuzhiyun unsigned nsid)
4129*4882a593Smuzhiyun {
4130*4882a593Smuzhiyun struct nvme_ns *ns, *next;
4131*4882a593Smuzhiyun LIST_HEAD(rm_list);
4132*4882a593Smuzhiyun
4133*4882a593Smuzhiyun down_write(&ctrl->namespaces_rwsem);
4134*4882a593Smuzhiyun list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
4135*4882a593Smuzhiyun if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
4136*4882a593Smuzhiyun list_move_tail(&ns->list, &rm_list);
4137*4882a593Smuzhiyun }
4138*4882a593Smuzhiyun up_write(&ctrl->namespaces_rwsem);
4139*4882a593Smuzhiyun
4140*4882a593Smuzhiyun list_for_each_entry_safe(ns, next, &rm_list, list)
4141*4882a593Smuzhiyun nvme_ns_remove(ns);
4142*4882a593Smuzhiyun
4143*4882a593Smuzhiyun }
4144*4882a593Smuzhiyun
nvme_scan_ns_list(struct nvme_ctrl * ctrl)4145*4882a593Smuzhiyun static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
4146*4882a593Smuzhiyun {
4147*4882a593Smuzhiyun const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
4148*4882a593Smuzhiyun __le32 *ns_list;
4149*4882a593Smuzhiyun u32 prev = 0;
4150*4882a593Smuzhiyun int ret = 0, i;
4151*4882a593Smuzhiyun
4152*4882a593Smuzhiyun if (nvme_ctrl_limited_cns(ctrl))
4153*4882a593Smuzhiyun return -EOPNOTSUPP;
4154*4882a593Smuzhiyun
4155*4882a593Smuzhiyun ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
4156*4882a593Smuzhiyun if (!ns_list)
4157*4882a593Smuzhiyun return -ENOMEM;
4158*4882a593Smuzhiyun
4159*4882a593Smuzhiyun for (;;) {
4160*4882a593Smuzhiyun struct nvme_command cmd = {
4161*4882a593Smuzhiyun .identify.opcode = nvme_admin_identify,
4162*4882a593Smuzhiyun .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
4163*4882a593Smuzhiyun .identify.nsid = cpu_to_le32(prev),
4164*4882a593Smuzhiyun };
4165*4882a593Smuzhiyun
4166*4882a593Smuzhiyun ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
4167*4882a593Smuzhiyun NVME_IDENTIFY_DATA_SIZE);
4168*4882a593Smuzhiyun if (ret)
4169*4882a593Smuzhiyun goto free;
4170*4882a593Smuzhiyun
4171*4882a593Smuzhiyun for (i = 0; i < nr_entries; i++) {
4172*4882a593Smuzhiyun u32 nsid = le32_to_cpu(ns_list[i]);
4173*4882a593Smuzhiyun
4174*4882a593Smuzhiyun if (!nsid) /* end of the list? */
4175*4882a593Smuzhiyun goto out;
4176*4882a593Smuzhiyun nvme_validate_or_alloc_ns(ctrl, nsid);
4177*4882a593Smuzhiyun while (++prev < nsid)
4178*4882a593Smuzhiyun nvme_ns_remove_by_nsid(ctrl, prev);
4179*4882a593Smuzhiyun }
4180*4882a593Smuzhiyun }
4181*4882a593Smuzhiyun out:
4182*4882a593Smuzhiyun nvme_remove_invalid_namespaces(ctrl, prev);
4183*4882a593Smuzhiyun free:
4184*4882a593Smuzhiyun kfree(ns_list);
4185*4882a593Smuzhiyun return ret;
4186*4882a593Smuzhiyun }
4187*4882a593Smuzhiyun
nvme_scan_ns_sequential(struct nvme_ctrl * ctrl)4188*4882a593Smuzhiyun static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
4189*4882a593Smuzhiyun {
4190*4882a593Smuzhiyun struct nvme_id_ctrl *id;
4191*4882a593Smuzhiyun u32 nn, i;
4192*4882a593Smuzhiyun
4193*4882a593Smuzhiyun if (nvme_identify_ctrl(ctrl, &id))
4194*4882a593Smuzhiyun return;
4195*4882a593Smuzhiyun nn = le32_to_cpu(id->nn);
4196*4882a593Smuzhiyun kfree(id);
4197*4882a593Smuzhiyun
4198*4882a593Smuzhiyun for (i = 1; i <= nn; i++)
4199*4882a593Smuzhiyun nvme_validate_or_alloc_ns(ctrl, i);
4200*4882a593Smuzhiyun
4201*4882a593Smuzhiyun nvme_remove_invalid_namespaces(ctrl, nn);
4202*4882a593Smuzhiyun }
4203*4882a593Smuzhiyun
nvme_clear_changed_ns_log(struct nvme_ctrl * ctrl)4204*4882a593Smuzhiyun static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
4205*4882a593Smuzhiyun {
4206*4882a593Smuzhiyun size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
4207*4882a593Smuzhiyun __le32 *log;
4208*4882a593Smuzhiyun int error;
4209*4882a593Smuzhiyun
4210*4882a593Smuzhiyun log = kzalloc(log_size, GFP_KERNEL);
4211*4882a593Smuzhiyun if (!log)
4212*4882a593Smuzhiyun return;
4213*4882a593Smuzhiyun
4214*4882a593Smuzhiyun /*
4215*4882a593Smuzhiyun * We need to read the log to clear the AEN, but we don't want to rely
4216*4882a593Smuzhiyun * on it for the changed namespace information as userspace could have
4217*4882a593Smuzhiyun * raced with us in reading the log page, which could cause us to miss
4218*4882a593Smuzhiyun * updates.
4219*4882a593Smuzhiyun */
4220*4882a593Smuzhiyun error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4221*4882a593Smuzhiyun NVME_CSI_NVM, log, log_size, 0);
4222*4882a593Smuzhiyun if (error)
4223*4882a593Smuzhiyun dev_warn(ctrl->device,
4224*4882a593Smuzhiyun "reading changed ns log failed: %d\n", error);
4225*4882a593Smuzhiyun
4226*4882a593Smuzhiyun kfree(log);
4227*4882a593Smuzhiyun }
4228*4882a593Smuzhiyun
nvme_scan_work(struct work_struct * work)4229*4882a593Smuzhiyun static void nvme_scan_work(struct work_struct *work)
4230*4882a593Smuzhiyun {
4231*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
4232*4882a593Smuzhiyun container_of(work, struct nvme_ctrl, scan_work);
4233*4882a593Smuzhiyun
4234*4882a593Smuzhiyun /* No tagset on a live ctrl means IO queues could not created */
4235*4882a593Smuzhiyun if (ctrl->state != NVME_CTRL_LIVE || !ctrl->tagset)
4236*4882a593Smuzhiyun return;
4237*4882a593Smuzhiyun
4238*4882a593Smuzhiyun if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
4239*4882a593Smuzhiyun dev_info(ctrl->device, "rescanning namespaces.\n");
4240*4882a593Smuzhiyun nvme_clear_changed_ns_log(ctrl);
4241*4882a593Smuzhiyun }
4242*4882a593Smuzhiyun
4243*4882a593Smuzhiyun mutex_lock(&ctrl->scan_lock);
4244*4882a593Smuzhiyun if (nvme_scan_ns_list(ctrl) != 0)
4245*4882a593Smuzhiyun nvme_scan_ns_sequential(ctrl);
4246*4882a593Smuzhiyun mutex_unlock(&ctrl->scan_lock);
4247*4882a593Smuzhiyun }
4248*4882a593Smuzhiyun
4249*4882a593Smuzhiyun /*
4250*4882a593Smuzhiyun * This function iterates the namespace list unlocked to allow recovery from
4251*4882a593Smuzhiyun * controller failure. It is up to the caller to ensure the namespace list is
4252*4882a593Smuzhiyun * not modified by scan work while this function is executing.
4253*4882a593Smuzhiyun */
nvme_remove_namespaces(struct nvme_ctrl * ctrl)4254*4882a593Smuzhiyun void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4255*4882a593Smuzhiyun {
4256*4882a593Smuzhiyun struct nvme_ns *ns, *next;
4257*4882a593Smuzhiyun LIST_HEAD(ns_list);
4258*4882a593Smuzhiyun
4259*4882a593Smuzhiyun /*
4260*4882a593Smuzhiyun * make sure to requeue I/O to all namespaces as these
4261*4882a593Smuzhiyun * might result from the scan itself and must complete
4262*4882a593Smuzhiyun * for the scan_work to make progress
4263*4882a593Smuzhiyun */
4264*4882a593Smuzhiyun nvme_mpath_clear_ctrl_paths(ctrl);
4265*4882a593Smuzhiyun
4266*4882a593Smuzhiyun /* prevent racing with ns scanning */
4267*4882a593Smuzhiyun flush_work(&ctrl->scan_work);
4268*4882a593Smuzhiyun
4269*4882a593Smuzhiyun /*
4270*4882a593Smuzhiyun * The dead states indicates the controller was not gracefully
4271*4882a593Smuzhiyun * disconnected. In that case, we won't be able to flush any data while
4272*4882a593Smuzhiyun * removing the namespaces' disks; fail all the queues now to avoid
4273*4882a593Smuzhiyun * potentially having to clean up the failed sync later.
4274*4882a593Smuzhiyun */
4275*4882a593Smuzhiyun if (ctrl->state == NVME_CTRL_DEAD)
4276*4882a593Smuzhiyun nvme_kill_queues(ctrl);
4277*4882a593Smuzhiyun
4278*4882a593Smuzhiyun /* this is a no-op when called from the controller reset handler */
4279*4882a593Smuzhiyun nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4280*4882a593Smuzhiyun
4281*4882a593Smuzhiyun down_write(&ctrl->namespaces_rwsem);
4282*4882a593Smuzhiyun list_splice_init(&ctrl->namespaces, &ns_list);
4283*4882a593Smuzhiyun up_write(&ctrl->namespaces_rwsem);
4284*4882a593Smuzhiyun
4285*4882a593Smuzhiyun list_for_each_entry_safe(ns, next, &ns_list, list)
4286*4882a593Smuzhiyun nvme_ns_remove(ns);
4287*4882a593Smuzhiyun }
4288*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
4289*4882a593Smuzhiyun
nvme_class_uevent(struct device * dev,struct kobj_uevent_env * env)4290*4882a593Smuzhiyun static int nvme_class_uevent(struct device *dev, struct kobj_uevent_env *env)
4291*4882a593Smuzhiyun {
4292*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
4293*4882a593Smuzhiyun container_of(dev, struct nvme_ctrl, ctrl_device);
4294*4882a593Smuzhiyun struct nvmf_ctrl_options *opts = ctrl->opts;
4295*4882a593Smuzhiyun int ret;
4296*4882a593Smuzhiyun
4297*4882a593Smuzhiyun ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4298*4882a593Smuzhiyun if (ret)
4299*4882a593Smuzhiyun return ret;
4300*4882a593Smuzhiyun
4301*4882a593Smuzhiyun if (opts) {
4302*4882a593Smuzhiyun ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4303*4882a593Smuzhiyun if (ret)
4304*4882a593Smuzhiyun return ret;
4305*4882a593Smuzhiyun
4306*4882a593Smuzhiyun ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4307*4882a593Smuzhiyun opts->trsvcid ?: "none");
4308*4882a593Smuzhiyun if (ret)
4309*4882a593Smuzhiyun return ret;
4310*4882a593Smuzhiyun
4311*4882a593Smuzhiyun ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4312*4882a593Smuzhiyun opts->host_traddr ?: "none");
4313*4882a593Smuzhiyun }
4314*4882a593Smuzhiyun return ret;
4315*4882a593Smuzhiyun }
4316*4882a593Smuzhiyun
nvme_aen_uevent(struct nvme_ctrl * ctrl)4317*4882a593Smuzhiyun static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4318*4882a593Smuzhiyun {
4319*4882a593Smuzhiyun char *envp[2] = { NULL, NULL };
4320*4882a593Smuzhiyun u32 aen_result = ctrl->aen_result;
4321*4882a593Smuzhiyun
4322*4882a593Smuzhiyun ctrl->aen_result = 0;
4323*4882a593Smuzhiyun if (!aen_result)
4324*4882a593Smuzhiyun return;
4325*4882a593Smuzhiyun
4326*4882a593Smuzhiyun envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4327*4882a593Smuzhiyun if (!envp[0])
4328*4882a593Smuzhiyun return;
4329*4882a593Smuzhiyun kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4330*4882a593Smuzhiyun kfree(envp[0]);
4331*4882a593Smuzhiyun }
4332*4882a593Smuzhiyun
nvme_async_event_work(struct work_struct * work)4333*4882a593Smuzhiyun static void nvme_async_event_work(struct work_struct *work)
4334*4882a593Smuzhiyun {
4335*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
4336*4882a593Smuzhiyun container_of(work, struct nvme_ctrl, async_event_work);
4337*4882a593Smuzhiyun
4338*4882a593Smuzhiyun nvme_aen_uevent(ctrl);
4339*4882a593Smuzhiyun
4340*4882a593Smuzhiyun /*
4341*4882a593Smuzhiyun * The transport drivers must guarantee AER submission here is safe by
4342*4882a593Smuzhiyun * flushing ctrl async_event_work after changing the controller state
4343*4882a593Smuzhiyun * from LIVE and before freeing the admin queue.
4344*4882a593Smuzhiyun */
4345*4882a593Smuzhiyun if (ctrl->state == NVME_CTRL_LIVE)
4346*4882a593Smuzhiyun ctrl->ops->submit_async_event(ctrl);
4347*4882a593Smuzhiyun }
4348*4882a593Smuzhiyun
nvme_ctrl_pp_status(struct nvme_ctrl * ctrl)4349*4882a593Smuzhiyun static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4350*4882a593Smuzhiyun {
4351*4882a593Smuzhiyun
4352*4882a593Smuzhiyun u32 csts;
4353*4882a593Smuzhiyun
4354*4882a593Smuzhiyun if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4355*4882a593Smuzhiyun return false;
4356*4882a593Smuzhiyun
4357*4882a593Smuzhiyun if (csts == ~0)
4358*4882a593Smuzhiyun return false;
4359*4882a593Smuzhiyun
4360*4882a593Smuzhiyun return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4361*4882a593Smuzhiyun }
4362*4882a593Smuzhiyun
nvme_get_fw_slot_info(struct nvme_ctrl * ctrl)4363*4882a593Smuzhiyun static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4364*4882a593Smuzhiyun {
4365*4882a593Smuzhiyun struct nvme_fw_slot_info_log *log;
4366*4882a593Smuzhiyun
4367*4882a593Smuzhiyun log = kmalloc(sizeof(*log), GFP_KERNEL);
4368*4882a593Smuzhiyun if (!log)
4369*4882a593Smuzhiyun return;
4370*4882a593Smuzhiyun
4371*4882a593Smuzhiyun if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
4372*4882a593Smuzhiyun log, sizeof(*log), 0))
4373*4882a593Smuzhiyun dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
4374*4882a593Smuzhiyun kfree(log);
4375*4882a593Smuzhiyun }
4376*4882a593Smuzhiyun
nvme_fw_act_work(struct work_struct * work)4377*4882a593Smuzhiyun static void nvme_fw_act_work(struct work_struct *work)
4378*4882a593Smuzhiyun {
4379*4882a593Smuzhiyun struct nvme_ctrl *ctrl = container_of(work,
4380*4882a593Smuzhiyun struct nvme_ctrl, fw_act_work);
4381*4882a593Smuzhiyun unsigned long fw_act_timeout;
4382*4882a593Smuzhiyun
4383*4882a593Smuzhiyun if (ctrl->mtfa)
4384*4882a593Smuzhiyun fw_act_timeout = jiffies +
4385*4882a593Smuzhiyun msecs_to_jiffies(ctrl->mtfa * 100);
4386*4882a593Smuzhiyun else
4387*4882a593Smuzhiyun fw_act_timeout = jiffies +
4388*4882a593Smuzhiyun msecs_to_jiffies(admin_timeout * 1000);
4389*4882a593Smuzhiyun
4390*4882a593Smuzhiyun nvme_stop_queues(ctrl);
4391*4882a593Smuzhiyun while (nvme_ctrl_pp_status(ctrl)) {
4392*4882a593Smuzhiyun if (time_after(jiffies, fw_act_timeout)) {
4393*4882a593Smuzhiyun dev_warn(ctrl->device,
4394*4882a593Smuzhiyun "Fw activation timeout, reset controller\n");
4395*4882a593Smuzhiyun nvme_try_sched_reset(ctrl);
4396*4882a593Smuzhiyun return;
4397*4882a593Smuzhiyun }
4398*4882a593Smuzhiyun msleep(100);
4399*4882a593Smuzhiyun }
4400*4882a593Smuzhiyun
4401*4882a593Smuzhiyun if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
4402*4882a593Smuzhiyun return;
4403*4882a593Smuzhiyun
4404*4882a593Smuzhiyun nvme_start_queues(ctrl);
4405*4882a593Smuzhiyun /* read FW slot information to clear the AER */
4406*4882a593Smuzhiyun nvme_get_fw_slot_info(ctrl);
4407*4882a593Smuzhiyun }
4408*4882a593Smuzhiyun
nvme_handle_aen_notice(struct nvme_ctrl * ctrl,u32 result)4409*4882a593Smuzhiyun static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
4410*4882a593Smuzhiyun {
4411*4882a593Smuzhiyun u32 aer_notice_type = (result & 0xff00) >> 8;
4412*4882a593Smuzhiyun
4413*4882a593Smuzhiyun trace_nvme_async_event(ctrl, aer_notice_type);
4414*4882a593Smuzhiyun
4415*4882a593Smuzhiyun switch (aer_notice_type) {
4416*4882a593Smuzhiyun case NVME_AER_NOTICE_NS_CHANGED:
4417*4882a593Smuzhiyun set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
4418*4882a593Smuzhiyun nvme_queue_scan(ctrl);
4419*4882a593Smuzhiyun break;
4420*4882a593Smuzhiyun case NVME_AER_NOTICE_FW_ACT_STARTING:
4421*4882a593Smuzhiyun /*
4422*4882a593Smuzhiyun * We are (ab)using the RESETTING state to prevent subsequent
4423*4882a593Smuzhiyun * recovery actions from interfering with the controller's
4424*4882a593Smuzhiyun * firmware activation.
4425*4882a593Smuzhiyun */
4426*4882a593Smuzhiyun if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
4427*4882a593Smuzhiyun queue_work(nvme_wq, &ctrl->fw_act_work);
4428*4882a593Smuzhiyun break;
4429*4882a593Smuzhiyun #ifdef CONFIG_NVME_MULTIPATH
4430*4882a593Smuzhiyun case NVME_AER_NOTICE_ANA:
4431*4882a593Smuzhiyun if (!ctrl->ana_log_buf)
4432*4882a593Smuzhiyun break;
4433*4882a593Smuzhiyun queue_work(nvme_wq, &ctrl->ana_work);
4434*4882a593Smuzhiyun break;
4435*4882a593Smuzhiyun #endif
4436*4882a593Smuzhiyun case NVME_AER_NOTICE_DISC_CHANGED:
4437*4882a593Smuzhiyun ctrl->aen_result = result;
4438*4882a593Smuzhiyun break;
4439*4882a593Smuzhiyun default:
4440*4882a593Smuzhiyun dev_warn(ctrl->device, "async event result %08x\n", result);
4441*4882a593Smuzhiyun }
4442*4882a593Smuzhiyun }
4443*4882a593Smuzhiyun
nvme_complete_async_event(struct nvme_ctrl * ctrl,__le16 status,volatile union nvme_result * res)4444*4882a593Smuzhiyun void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
4445*4882a593Smuzhiyun volatile union nvme_result *res)
4446*4882a593Smuzhiyun {
4447*4882a593Smuzhiyun u32 result = le32_to_cpu(res->u32);
4448*4882a593Smuzhiyun u32 aer_type = result & 0x07;
4449*4882a593Smuzhiyun
4450*4882a593Smuzhiyun if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
4451*4882a593Smuzhiyun return;
4452*4882a593Smuzhiyun
4453*4882a593Smuzhiyun switch (aer_type) {
4454*4882a593Smuzhiyun case NVME_AER_NOTICE:
4455*4882a593Smuzhiyun nvme_handle_aen_notice(ctrl, result);
4456*4882a593Smuzhiyun break;
4457*4882a593Smuzhiyun case NVME_AER_ERROR:
4458*4882a593Smuzhiyun case NVME_AER_SMART:
4459*4882a593Smuzhiyun case NVME_AER_CSS:
4460*4882a593Smuzhiyun case NVME_AER_VS:
4461*4882a593Smuzhiyun trace_nvme_async_event(ctrl, aer_type);
4462*4882a593Smuzhiyun ctrl->aen_result = result;
4463*4882a593Smuzhiyun break;
4464*4882a593Smuzhiyun default:
4465*4882a593Smuzhiyun break;
4466*4882a593Smuzhiyun }
4467*4882a593Smuzhiyun queue_work(nvme_wq, &ctrl->async_event_work);
4468*4882a593Smuzhiyun }
4469*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_complete_async_event);
4470*4882a593Smuzhiyun
nvme_stop_ctrl(struct nvme_ctrl * ctrl)4471*4882a593Smuzhiyun void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
4472*4882a593Smuzhiyun {
4473*4882a593Smuzhiyun nvme_mpath_stop(ctrl);
4474*4882a593Smuzhiyun nvme_stop_keep_alive(ctrl);
4475*4882a593Smuzhiyun flush_work(&ctrl->async_event_work);
4476*4882a593Smuzhiyun cancel_work_sync(&ctrl->fw_act_work);
4477*4882a593Smuzhiyun if (ctrl->ops->stop_ctrl)
4478*4882a593Smuzhiyun ctrl->ops->stop_ctrl(ctrl);
4479*4882a593Smuzhiyun }
4480*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4481*4882a593Smuzhiyun
nvme_start_ctrl(struct nvme_ctrl * ctrl)4482*4882a593Smuzhiyun void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4483*4882a593Smuzhiyun {
4484*4882a593Smuzhiyun nvme_start_keep_alive(ctrl);
4485*4882a593Smuzhiyun
4486*4882a593Smuzhiyun nvme_enable_aen(ctrl);
4487*4882a593Smuzhiyun
4488*4882a593Smuzhiyun if (ctrl->queue_count > 1) {
4489*4882a593Smuzhiyun nvme_queue_scan(ctrl);
4490*4882a593Smuzhiyun nvme_start_queues(ctrl);
4491*4882a593Smuzhiyun nvme_mpath_update(ctrl);
4492*4882a593Smuzhiyun }
4493*4882a593Smuzhiyun }
4494*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_start_ctrl);
4495*4882a593Smuzhiyun
nvme_uninit_ctrl(struct nvme_ctrl * ctrl)4496*4882a593Smuzhiyun void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4497*4882a593Smuzhiyun {
4498*4882a593Smuzhiyun nvme_hwmon_exit(ctrl);
4499*4882a593Smuzhiyun nvme_fault_inject_fini(&ctrl->fault_inject);
4500*4882a593Smuzhiyun dev_pm_qos_hide_latency_tolerance(ctrl->device);
4501*4882a593Smuzhiyun cdev_device_del(&ctrl->cdev, ctrl->device);
4502*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
4503*4882a593Smuzhiyun }
4504*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
4505*4882a593Smuzhiyun
nvme_free_cels(struct nvme_ctrl * ctrl)4506*4882a593Smuzhiyun static void nvme_free_cels(struct nvme_ctrl *ctrl)
4507*4882a593Smuzhiyun {
4508*4882a593Smuzhiyun struct nvme_effects_log *cel;
4509*4882a593Smuzhiyun unsigned long i;
4510*4882a593Smuzhiyun
4511*4882a593Smuzhiyun xa_for_each (&ctrl->cels, i, cel) {
4512*4882a593Smuzhiyun xa_erase(&ctrl->cels, i);
4513*4882a593Smuzhiyun kfree(cel);
4514*4882a593Smuzhiyun }
4515*4882a593Smuzhiyun
4516*4882a593Smuzhiyun xa_destroy(&ctrl->cels);
4517*4882a593Smuzhiyun }
4518*4882a593Smuzhiyun
nvme_free_ctrl(struct device * dev)4519*4882a593Smuzhiyun static void nvme_free_ctrl(struct device *dev)
4520*4882a593Smuzhiyun {
4521*4882a593Smuzhiyun struct nvme_ctrl *ctrl =
4522*4882a593Smuzhiyun container_of(dev, struct nvme_ctrl, ctrl_device);
4523*4882a593Smuzhiyun struct nvme_subsystem *subsys = ctrl->subsys;
4524*4882a593Smuzhiyun
4525*4882a593Smuzhiyun if (!subsys || ctrl->instance != subsys->instance)
4526*4882a593Smuzhiyun ida_simple_remove(&nvme_instance_ida, ctrl->instance);
4527*4882a593Smuzhiyun
4528*4882a593Smuzhiyun nvme_free_cels(ctrl);
4529*4882a593Smuzhiyun nvme_mpath_uninit(ctrl);
4530*4882a593Smuzhiyun __free_page(ctrl->discard_page);
4531*4882a593Smuzhiyun
4532*4882a593Smuzhiyun if (subsys) {
4533*4882a593Smuzhiyun mutex_lock(&nvme_subsystems_lock);
4534*4882a593Smuzhiyun list_del(&ctrl->subsys_entry);
4535*4882a593Smuzhiyun sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
4536*4882a593Smuzhiyun mutex_unlock(&nvme_subsystems_lock);
4537*4882a593Smuzhiyun }
4538*4882a593Smuzhiyun
4539*4882a593Smuzhiyun ctrl->ops->free_ctrl(ctrl);
4540*4882a593Smuzhiyun
4541*4882a593Smuzhiyun if (subsys)
4542*4882a593Smuzhiyun nvme_put_subsystem(subsys);
4543*4882a593Smuzhiyun }
4544*4882a593Smuzhiyun
4545*4882a593Smuzhiyun /*
4546*4882a593Smuzhiyun * Initialize a NVMe controller structures. This needs to be called during
4547*4882a593Smuzhiyun * earliest initialization so that we have the initialized structured around
4548*4882a593Smuzhiyun * during probing.
4549*4882a593Smuzhiyun */
nvme_init_ctrl(struct nvme_ctrl * ctrl,struct device * dev,const struct nvme_ctrl_ops * ops,unsigned long quirks)4550*4882a593Smuzhiyun int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4551*4882a593Smuzhiyun const struct nvme_ctrl_ops *ops, unsigned long quirks)
4552*4882a593Smuzhiyun {
4553*4882a593Smuzhiyun int ret;
4554*4882a593Smuzhiyun
4555*4882a593Smuzhiyun ctrl->state = NVME_CTRL_NEW;
4556*4882a593Smuzhiyun spin_lock_init(&ctrl->lock);
4557*4882a593Smuzhiyun mutex_init(&ctrl->scan_lock);
4558*4882a593Smuzhiyun INIT_LIST_HEAD(&ctrl->namespaces);
4559*4882a593Smuzhiyun xa_init(&ctrl->cels);
4560*4882a593Smuzhiyun init_rwsem(&ctrl->namespaces_rwsem);
4561*4882a593Smuzhiyun ctrl->dev = dev;
4562*4882a593Smuzhiyun ctrl->ops = ops;
4563*4882a593Smuzhiyun ctrl->quirks = quirks;
4564*4882a593Smuzhiyun ctrl->numa_node = NUMA_NO_NODE;
4565*4882a593Smuzhiyun INIT_WORK(&ctrl->scan_work, nvme_scan_work);
4566*4882a593Smuzhiyun INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
4567*4882a593Smuzhiyun INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
4568*4882a593Smuzhiyun INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
4569*4882a593Smuzhiyun init_waitqueue_head(&ctrl->state_wq);
4570*4882a593Smuzhiyun
4571*4882a593Smuzhiyun INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
4572*4882a593Smuzhiyun memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4573*4882a593Smuzhiyun ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
4574*4882a593Smuzhiyun
4575*4882a593Smuzhiyun BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4576*4882a593Smuzhiyun PAGE_SIZE);
4577*4882a593Smuzhiyun ctrl->discard_page = alloc_page(GFP_KERNEL);
4578*4882a593Smuzhiyun if (!ctrl->discard_page) {
4579*4882a593Smuzhiyun ret = -ENOMEM;
4580*4882a593Smuzhiyun goto out;
4581*4882a593Smuzhiyun }
4582*4882a593Smuzhiyun
4583*4882a593Smuzhiyun ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
4584*4882a593Smuzhiyun if (ret < 0)
4585*4882a593Smuzhiyun goto out;
4586*4882a593Smuzhiyun ctrl->instance = ret;
4587*4882a593Smuzhiyun
4588*4882a593Smuzhiyun device_initialize(&ctrl->ctrl_device);
4589*4882a593Smuzhiyun ctrl->device = &ctrl->ctrl_device;
4590*4882a593Smuzhiyun ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
4591*4882a593Smuzhiyun ctrl->device->class = nvme_class;
4592*4882a593Smuzhiyun ctrl->device->parent = ctrl->dev;
4593*4882a593Smuzhiyun ctrl->device->groups = nvme_dev_attr_groups;
4594*4882a593Smuzhiyun ctrl->device->release = nvme_free_ctrl;
4595*4882a593Smuzhiyun dev_set_drvdata(ctrl->device, ctrl);
4596*4882a593Smuzhiyun ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4597*4882a593Smuzhiyun if (ret)
4598*4882a593Smuzhiyun goto out_release_instance;
4599*4882a593Smuzhiyun
4600*4882a593Smuzhiyun nvme_get_ctrl(ctrl);
4601*4882a593Smuzhiyun cdev_init(&ctrl->cdev, &nvme_dev_fops);
4602*4882a593Smuzhiyun ctrl->cdev.owner = ops->module;
4603*4882a593Smuzhiyun ret = cdev_device_add(&ctrl->cdev, ctrl->device);
4604*4882a593Smuzhiyun if (ret)
4605*4882a593Smuzhiyun goto out_free_name;
4606*4882a593Smuzhiyun
4607*4882a593Smuzhiyun /*
4608*4882a593Smuzhiyun * Initialize latency tolerance controls. The sysfs files won't
4609*4882a593Smuzhiyun * be visible to userspace unless the device actually supports APST.
4610*4882a593Smuzhiyun */
4611*4882a593Smuzhiyun ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4612*4882a593Smuzhiyun dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4613*4882a593Smuzhiyun min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4614*4882a593Smuzhiyun
4615*4882a593Smuzhiyun nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
4616*4882a593Smuzhiyun nvme_mpath_init_ctrl(ctrl);
4617*4882a593Smuzhiyun
4618*4882a593Smuzhiyun return 0;
4619*4882a593Smuzhiyun out_free_name:
4620*4882a593Smuzhiyun nvme_put_ctrl(ctrl);
4621*4882a593Smuzhiyun kfree_const(ctrl->device->kobj.name);
4622*4882a593Smuzhiyun out_release_instance:
4623*4882a593Smuzhiyun ida_simple_remove(&nvme_instance_ida, ctrl->instance);
4624*4882a593Smuzhiyun out:
4625*4882a593Smuzhiyun if (ctrl->discard_page)
4626*4882a593Smuzhiyun __free_page(ctrl->discard_page);
4627*4882a593Smuzhiyun return ret;
4628*4882a593Smuzhiyun }
4629*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_init_ctrl);
4630*4882a593Smuzhiyun
4631*4882a593Smuzhiyun /**
4632*4882a593Smuzhiyun * nvme_kill_queues(): Ends all namespace queues
4633*4882a593Smuzhiyun * @ctrl: the dead controller that needs to end
4634*4882a593Smuzhiyun *
4635*4882a593Smuzhiyun * Call this function when the driver determines it is unable to get the
4636*4882a593Smuzhiyun * controller in a state capable of servicing IO.
4637*4882a593Smuzhiyun */
nvme_kill_queues(struct nvme_ctrl * ctrl)4638*4882a593Smuzhiyun void nvme_kill_queues(struct nvme_ctrl *ctrl)
4639*4882a593Smuzhiyun {
4640*4882a593Smuzhiyun struct nvme_ns *ns;
4641*4882a593Smuzhiyun
4642*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4643*4882a593Smuzhiyun
4644*4882a593Smuzhiyun /* Forcibly unquiesce queues to avoid blocking dispatch */
4645*4882a593Smuzhiyun if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
4646*4882a593Smuzhiyun blk_mq_unquiesce_queue(ctrl->admin_q);
4647*4882a593Smuzhiyun
4648*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4649*4882a593Smuzhiyun nvme_set_queue_dying(ns);
4650*4882a593Smuzhiyun
4651*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4652*4882a593Smuzhiyun }
4653*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_kill_queues);
4654*4882a593Smuzhiyun
nvme_unfreeze(struct nvme_ctrl * ctrl)4655*4882a593Smuzhiyun void nvme_unfreeze(struct nvme_ctrl *ctrl)
4656*4882a593Smuzhiyun {
4657*4882a593Smuzhiyun struct nvme_ns *ns;
4658*4882a593Smuzhiyun
4659*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4660*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4661*4882a593Smuzhiyun blk_mq_unfreeze_queue(ns->queue);
4662*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4663*4882a593Smuzhiyun }
4664*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_unfreeze);
4665*4882a593Smuzhiyun
nvme_wait_freeze_timeout(struct nvme_ctrl * ctrl,long timeout)4666*4882a593Smuzhiyun int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
4667*4882a593Smuzhiyun {
4668*4882a593Smuzhiyun struct nvme_ns *ns;
4669*4882a593Smuzhiyun
4670*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4671*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list) {
4672*4882a593Smuzhiyun timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4673*4882a593Smuzhiyun if (timeout <= 0)
4674*4882a593Smuzhiyun break;
4675*4882a593Smuzhiyun }
4676*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4677*4882a593Smuzhiyun return timeout;
4678*4882a593Smuzhiyun }
4679*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4680*4882a593Smuzhiyun
nvme_wait_freeze(struct nvme_ctrl * ctrl)4681*4882a593Smuzhiyun void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4682*4882a593Smuzhiyun {
4683*4882a593Smuzhiyun struct nvme_ns *ns;
4684*4882a593Smuzhiyun
4685*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4686*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4687*4882a593Smuzhiyun blk_mq_freeze_queue_wait(ns->queue);
4688*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4689*4882a593Smuzhiyun }
4690*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4691*4882a593Smuzhiyun
nvme_start_freeze(struct nvme_ctrl * ctrl)4692*4882a593Smuzhiyun void nvme_start_freeze(struct nvme_ctrl *ctrl)
4693*4882a593Smuzhiyun {
4694*4882a593Smuzhiyun struct nvme_ns *ns;
4695*4882a593Smuzhiyun
4696*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4697*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4698*4882a593Smuzhiyun blk_freeze_queue_start(ns->queue);
4699*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4700*4882a593Smuzhiyun }
4701*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_start_freeze);
4702*4882a593Smuzhiyun
nvme_stop_queues(struct nvme_ctrl * ctrl)4703*4882a593Smuzhiyun void nvme_stop_queues(struct nvme_ctrl *ctrl)
4704*4882a593Smuzhiyun {
4705*4882a593Smuzhiyun struct nvme_ns *ns;
4706*4882a593Smuzhiyun
4707*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4708*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4709*4882a593Smuzhiyun blk_mq_quiesce_queue(ns->queue);
4710*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4711*4882a593Smuzhiyun }
4712*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_stop_queues);
4713*4882a593Smuzhiyun
nvme_start_queues(struct nvme_ctrl * ctrl)4714*4882a593Smuzhiyun void nvme_start_queues(struct nvme_ctrl *ctrl)
4715*4882a593Smuzhiyun {
4716*4882a593Smuzhiyun struct nvme_ns *ns;
4717*4882a593Smuzhiyun
4718*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4719*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4720*4882a593Smuzhiyun blk_mq_unquiesce_queue(ns->queue);
4721*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4722*4882a593Smuzhiyun }
4723*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_start_queues);
4724*4882a593Smuzhiyun
nvme_sync_io_queues(struct nvme_ctrl * ctrl)4725*4882a593Smuzhiyun void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
4726*4882a593Smuzhiyun {
4727*4882a593Smuzhiyun struct nvme_ns *ns;
4728*4882a593Smuzhiyun
4729*4882a593Smuzhiyun down_read(&ctrl->namespaces_rwsem);
4730*4882a593Smuzhiyun list_for_each_entry(ns, &ctrl->namespaces, list)
4731*4882a593Smuzhiyun blk_sync_queue(ns->queue);
4732*4882a593Smuzhiyun up_read(&ctrl->namespaces_rwsem);
4733*4882a593Smuzhiyun }
4734*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
4735*4882a593Smuzhiyun
nvme_sync_queues(struct nvme_ctrl * ctrl)4736*4882a593Smuzhiyun void nvme_sync_queues(struct nvme_ctrl *ctrl)
4737*4882a593Smuzhiyun {
4738*4882a593Smuzhiyun nvme_sync_io_queues(ctrl);
4739*4882a593Smuzhiyun if (ctrl->admin_q)
4740*4882a593Smuzhiyun blk_sync_queue(ctrl->admin_q);
4741*4882a593Smuzhiyun }
4742*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(nvme_sync_queues);
4743*4882a593Smuzhiyun
nvme_ctrl_from_file(struct file * file)4744*4882a593Smuzhiyun struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
4745*4882a593Smuzhiyun {
4746*4882a593Smuzhiyun if (file->f_op != &nvme_dev_fops)
4747*4882a593Smuzhiyun return NULL;
4748*4882a593Smuzhiyun return file->private_data;
4749*4882a593Smuzhiyun }
4750*4882a593Smuzhiyun EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
4751*4882a593Smuzhiyun
4752*4882a593Smuzhiyun /*
4753*4882a593Smuzhiyun * Check we didn't inadvertently grow the command structure sizes:
4754*4882a593Smuzhiyun */
_nvme_check_size(void)4755*4882a593Smuzhiyun static inline void _nvme_check_size(void)
4756*4882a593Smuzhiyun {
4757*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4758*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4759*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4760*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4761*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4762*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4763*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4764*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4765*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4766*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4767*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4768*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4769*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
4770*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4771*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
4772*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4773*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4774*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4775*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4776*4882a593Smuzhiyun }
4777*4882a593Smuzhiyun
4778*4882a593Smuzhiyun
nvme_core_init(void)4779*4882a593Smuzhiyun static int __init nvme_core_init(void)
4780*4882a593Smuzhiyun {
4781*4882a593Smuzhiyun int result = -ENOMEM;
4782*4882a593Smuzhiyun
4783*4882a593Smuzhiyun _nvme_check_size();
4784*4882a593Smuzhiyun
4785*4882a593Smuzhiyun nvme_wq = alloc_workqueue("nvme-wq",
4786*4882a593Smuzhiyun WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4787*4882a593Smuzhiyun if (!nvme_wq)
4788*4882a593Smuzhiyun goto out;
4789*4882a593Smuzhiyun
4790*4882a593Smuzhiyun nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4791*4882a593Smuzhiyun WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4792*4882a593Smuzhiyun if (!nvme_reset_wq)
4793*4882a593Smuzhiyun goto destroy_wq;
4794*4882a593Smuzhiyun
4795*4882a593Smuzhiyun nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4796*4882a593Smuzhiyun WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4797*4882a593Smuzhiyun if (!nvme_delete_wq)
4798*4882a593Smuzhiyun goto destroy_reset_wq;
4799*4882a593Smuzhiyun
4800*4882a593Smuzhiyun result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
4801*4882a593Smuzhiyun if (result < 0)
4802*4882a593Smuzhiyun goto destroy_delete_wq;
4803*4882a593Smuzhiyun
4804*4882a593Smuzhiyun nvme_class = class_create(THIS_MODULE, "nvme");
4805*4882a593Smuzhiyun if (IS_ERR(nvme_class)) {
4806*4882a593Smuzhiyun result = PTR_ERR(nvme_class);
4807*4882a593Smuzhiyun goto unregister_chrdev;
4808*4882a593Smuzhiyun }
4809*4882a593Smuzhiyun nvme_class->dev_uevent = nvme_class_uevent;
4810*4882a593Smuzhiyun
4811*4882a593Smuzhiyun nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
4812*4882a593Smuzhiyun if (IS_ERR(nvme_subsys_class)) {
4813*4882a593Smuzhiyun result = PTR_ERR(nvme_subsys_class);
4814*4882a593Smuzhiyun goto destroy_class;
4815*4882a593Smuzhiyun }
4816*4882a593Smuzhiyun return 0;
4817*4882a593Smuzhiyun
4818*4882a593Smuzhiyun destroy_class:
4819*4882a593Smuzhiyun class_destroy(nvme_class);
4820*4882a593Smuzhiyun unregister_chrdev:
4821*4882a593Smuzhiyun unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
4822*4882a593Smuzhiyun destroy_delete_wq:
4823*4882a593Smuzhiyun destroy_workqueue(nvme_delete_wq);
4824*4882a593Smuzhiyun destroy_reset_wq:
4825*4882a593Smuzhiyun destroy_workqueue(nvme_reset_wq);
4826*4882a593Smuzhiyun destroy_wq:
4827*4882a593Smuzhiyun destroy_workqueue(nvme_wq);
4828*4882a593Smuzhiyun out:
4829*4882a593Smuzhiyun return result;
4830*4882a593Smuzhiyun }
4831*4882a593Smuzhiyun
nvme_core_exit(void)4832*4882a593Smuzhiyun static void __exit nvme_core_exit(void)
4833*4882a593Smuzhiyun {
4834*4882a593Smuzhiyun class_destroy(nvme_subsys_class);
4835*4882a593Smuzhiyun class_destroy(nvme_class);
4836*4882a593Smuzhiyun unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
4837*4882a593Smuzhiyun destroy_workqueue(nvme_delete_wq);
4838*4882a593Smuzhiyun destroy_workqueue(nvme_reset_wq);
4839*4882a593Smuzhiyun destroy_workqueue(nvme_wq);
4840*4882a593Smuzhiyun ida_destroy(&nvme_instance_ida);
4841*4882a593Smuzhiyun }
4842*4882a593Smuzhiyun
4843*4882a593Smuzhiyun MODULE_LICENSE("GPL");
4844*4882a593Smuzhiyun MODULE_VERSION("1.0");
4845*4882a593Smuzhiyun module_init(nvme_core_init);
4846*4882a593Smuzhiyun module_exit(nvme_core_exit);
4847