1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3*4882a593Smuzhiyun #ifndef _NTB_INTEL_GEN4_H_ 4*4882a593Smuzhiyun #define _NTB_INTEL_GEN4_H_ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include "ntb_hw_intel.h" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Supported PCI device revision range for ICX */ 9*4882a593Smuzhiyun #define PCI_DEVICE_REVISION_ICX_MIN 0x2 10*4882a593Smuzhiyun #define PCI_DEVICE_REVISION_ICX_MAX 0xF 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Intel Gen4 NTB hardware */ 13*4882a593Smuzhiyun /* PCIe config space */ 14*4882a593Smuzhiyun #define GEN4_IMBAR23SZ_OFFSET 0x00c4 15*4882a593Smuzhiyun #define GEN4_IMBAR45SZ_OFFSET 0x00c5 16*4882a593Smuzhiyun #define GEN4_EMBAR23SZ_OFFSET 0x00c6 17*4882a593Smuzhiyun #define GEN4_EMBAR45SZ_OFFSET 0x00c7 18*4882a593Smuzhiyun #define GEN4_DEVCTRL_OFFSET 0x0048 19*4882a593Smuzhiyun #define GEN4_DEVSTS_OFFSET 0x004a 20*4882a593Smuzhiyun #define GEN4_UNCERRSTS_OFFSET 0x0104 21*4882a593Smuzhiyun #define GEN4_CORERRSTS_OFFSET 0x0110 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* BAR0 MMIO */ 24*4882a593Smuzhiyun #define GEN4_NTBCNTL_OFFSET 0x0000 25*4882a593Smuzhiyun #define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */ 26*4882a593Smuzhiyun #define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */ 27*4882a593Smuzhiyun #define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */ 28*4882a593Smuzhiyun #define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */ 29*4882a593Smuzhiyun #define GEN4_IM_INT_STATUS_OFFSET 0x0040 30*4882a593Smuzhiyun #define GEN4_IM_INT_DISABLE_OFFSET 0x0048 31*4882a593Smuzhiyun #define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */ 32*4882a593Smuzhiyun #define GEN4_IM23XBASEIDX_OFFSET 0x0074 33*4882a593Smuzhiyun #define GEN4_IM45XBASEIDX_OFFSET 0x0076 34*4882a593Smuzhiyun #define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */ 35*4882a593Smuzhiyun #define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */ 36*4882a593Smuzhiyun #define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */ 37*4882a593Smuzhiyun #define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */ 38*4882a593Smuzhiyun #define GEN4_EM_SPAD_OFFSET 0x8080 39*4882a593Smuzhiyun /* note, link status is now in MMIO and not config space for NTB */ 40*4882a593Smuzhiyun #define GEN4_LINK_CTRL_OFFSET 0xb050 41*4882a593Smuzhiyun #define GEN4_LINK_STATUS_OFFSET 0xb052 42*4882a593Smuzhiyun #define GEN4_PPD0_OFFSET 0xb0d4 43*4882a593Smuzhiyun #define GEN4_PPD1_OFFSET 0xb4c0 44*4882a593Smuzhiyun #define GEN4_LTSSMSTATEJMP 0xf040 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define GEN4_PPD_CLEAR_TRN 0x0001 47*4882a593Smuzhiyun #define GEN4_PPD_LINKTRN 0x0008 48*4882a593Smuzhiyun #define GEN4_PPD_CONN_MASK 0x0300 49*4882a593Smuzhiyun #define SPR_PPD_CONN_MASK 0x0700 50*4882a593Smuzhiyun #define GEN4_PPD_CONN_B2B 0x0200 51*4882a593Smuzhiyun #define GEN4_PPD_DEV_MASK 0x1000 52*4882a593Smuzhiyun #define GEN4_PPD_DEV_DSD 0x1000 53*4882a593Smuzhiyun #define GEN4_PPD_DEV_USD 0x0000 54*4882a593Smuzhiyun #define SPR_PPD_DEV_MASK 0x4000 55*4882a593Smuzhiyun #define SPR_PPD_DEV_DSD 0x4000 56*4882a593Smuzhiyun #define SPR_PPD_DEV_USD 0x0000 57*4882a593Smuzhiyun #define GEN4_LINK_CTRL_LINK_DISABLE 0x0010 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define GEN4_SLOTSTS 0xb05a 60*4882a593Smuzhiyun #define GEN4_SLOTSTS_DLLSCS 0x100 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK) 63*4882a593Smuzhiyun #define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD) 64*4882a593Smuzhiyun #define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SPR_PPD_TOPO_MASK (SPR_PPD_CONN_MASK | SPR_PPD_DEV_MASK) 67*4882a593Smuzhiyun #define SPR_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_USD) 68*4882a593Smuzhiyun #define SPR_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_DSD) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define GEN4_DB_COUNT 32 71*4882a593Smuzhiyun #define GEN4_DB_LINK 32 72*4882a593Smuzhiyun #define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK) 73*4882a593Smuzhiyun #define GEN4_DB_MSIX_VECTOR_COUNT 33 74*4882a593Smuzhiyun #define GEN4_DB_MSIX_VECTOR_SHIFT 1 75*4882a593Smuzhiyun #define GEN4_DB_TOTAL_SHIFT 33 76*4882a593Smuzhiyun #define GEN4_SPAD_COUNT 16 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define NTB_CTL_E2I_BAR23_SNOOP 0x000004 79*4882a593Smuzhiyun #define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008 80*4882a593Smuzhiyun #define NTB_CTL_I2E_BAR23_SNOOP 0x000010 81*4882a593Smuzhiyun #define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020 82*4882a593Smuzhiyun #define NTB_CTL_E2I_BAR45_SNOOP 0x000040 83*4882a593Smuzhiyun #define NTB_CTL_E2I_BAR45_NOSNOO 0x000080 84*4882a593Smuzhiyun #define NTB_CTL_I2E_BAR45_SNOOP 0x000100 85*4882a593Smuzhiyun #define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200 86*4882a593Smuzhiyun #define NTB_CTL_BUSNO_DIS_INC 0x000400 87*4882a593Smuzhiyun #define NTB_CTL_LINK_DOWN 0x010000 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define NTB_SJC_FORCEDETECT 0x000004 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, 92*4882a593Smuzhiyun size_t count, loff_t *offp); 93*4882a593Smuzhiyun int gen4_init_dev(struct intel_ntb_dev *ndev); 94*4882a593Smuzhiyun ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, 95*4882a593Smuzhiyun size_t count, loff_t *offp); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun extern const struct ntb_dev_ops intel_ntb4_ops; 98*4882a593Smuzhiyun pdev_is_ICX(struct pci_dev * pdev)99*4882a593Smuzhiyunstatic inline int pdev_is_ICX(struct pci_dev *pdev) 100*4882a593Smuzhiyun { 101*4882a593Smuzhiyun if (pdev_is_gen4(pdev) && 102*4882a593Smuzhiyun pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN && 103*4882a593Smuzhiyun pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX) 104*4882a593Smuzhiyun return 1; 105*4882a593Smuzhiyun return 0; 106*4882a593Smuzhiyun } 107*4882a593Smuzhiyun pdev_is_SPR(struct pci_dev * pdev)108*4882a593Smuzhiyunstatic inline int pdev_is_SPR(struct pci_dev *pdev) 109*4882a593Smuzhiyun { 110*4882a593Smuzhiyun if (pdev_is_gen4(pdev) && 111*4882a593Smuzhiyun pdev->revision > PCI_DEVICE_REVISION_ICX_MAX) 112*4882a593Smuzhiyun return 1; 113*4882a593Smuzhiyun return 0; 114*4882a593Smuzhiyun } 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif 117