1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
3*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * GPL LICENSE SUMMARY
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * BSD LICENSE
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
18*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
19*4882a593Smuzhiyun * are met:
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright
22*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
23*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copy
24*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
25*4882a593Smuzhiyun * the documentation and/or other materials provided with the
26*4882a593Smuzhiyun * distribution.
27*4882a593Smuzhiyun * * Neither the name of Intel Corporation nor the names of its
28*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
29*4882a593Smuzhiyun * from this software without specific prior written permission.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #ifndef _NTB_INTEL_GEN3_H_
45*4882a593Smuzhiyun #define _NTB_INTEL_GEN3_H_
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #include "ntb_hw_intel.h"
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Intel Skylake Xeon hardware */
50*4882a593Smuzhiyun #define GEN3_IMBAR1SZ_OFFSET 0x00d0
51*4882a593Smuzhiyun #define GEN3_IMBAR2SZ_OFFSET 0x00d1
52*4882a593Smuzhiyun #define GEN3_EMBAR1SZ_OFFSET 0x00d2
53*4882a593Smuzhiyun #define GEN3_EMBAR2SZ_OFFSET 0x00d3
54*4882a593Smuzhiyun #define GEN3_DEVCTRL_OFFSET 0x0098
55*4882a593Smuzhiyun #define GEN3_DEVSTS_OFFSET 0x009a
56*4882a593Smuzhiyun #define GEN3_UNCERRSTS_OFFSET 0x014c
57*4882a593Smuzhiyun #define GEN3_CORERRSTS_OFFSET 0x0158
58*4882a593Smuzhiyun #define GEN3_LINK_STATUS_OFFSET 0x01a2
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define GEN3_NTBCNTL_OFFSET 0x0000
61*4882a593Smuzhiyun #define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
62*4882a593Smuzhiyun #define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
63*4882a593Smuzhiyun #define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
64*4882a593Smuzhiyun #define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
65*4882a593Smuzhiyun #define GEN3_IM_INT_STATUS_OFFSET 0x0040
66*4882a593Smuzhiyun #define GEN3_IM_INT_DISABLE_OFFSET 0x0048
67*4882a593Smuzhiyun #define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */
68*4882a593Smuzhiyun #define GEN3_USMEMMISS_OFFSET 0x0070
69*4882a593Smuzhiyun #define GEN3_INTVEC_OFFSET 0x00d0
70*4882a593Smuzhiyun #define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
71*4882a593Smuzhiyun #define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
72*4882a593Smuzhiyun #define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
73*4882a593Smuzhiyun #define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
74*4882a593Smuzhiyun #define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
75*4882a593Smuzhiyun #define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
76*4882a593Smuzhiyun #define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
77*4882a593Smuzhiyun #define GEN3_EM_INT_STATUS_OFFSET 0x4040
78*4882a593Smuzhiyun #define GEN3_EM_INT_DISABLE_OFFSET 0x4048
79*4882a593Smuzhiyun #define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
80*4882a593Smuzhiyun #define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
81*4882a593Smuzhiyun #define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */
82*4882a593Smuzhiyun #define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
83*4882a593Smuzhiyun #define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
84*4882a593Smuzhiyun #define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define GEN3_DB_COUNT 32
87*4882a593Smuzhiyun #define GEN3_DB_LINK 32
88*4882a593Smuzhiyun #define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
89*4882a593Smuzhiyun #define GEN3_DB_MSIX_VECTOR_COUNT 33
90*4882a593Smuzhiyun #define GEN3_DB_MSIX_VECTOR_SHIFT 1
91*4882a593Smuzhiyun #define GEN3_DB_TOTAL_SHIFT 33
92*4882a593Smuzhiyun #define GEN3_SPAD_COUNT 16
93*4882a593Smuzhiyun
gen3_db_ioread(const void __iomem * mmio)94*4882a593Smuzhiyun static inline u64 gen3_db_ioread(const void __iomem *mmio)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun return ioread64(mmio);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
gen3_db_iowrite(u64 bits,void __iomem * mmio)99*4882a593Smuzhiyun static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun iowrite64(bits, mmio);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
105*4882a593Smuzhiyun size_t count, loff_t *offp);
106*4882a593Smuzhiyun int gen3_init_dev(struct intel_ntb_dev *ndev);
107*4882a593Smuzhiyun int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
108*4882a593Smuzhiyun enum ntb_width max_width);
109*4882a593Smuzhiyun u64 intel_ntb3_db_read(struct ntb_dev *ntb);
110*4882a593Smuzhiyun int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits);
111*4882a593Smuzhiyun int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits);
112*4882a593Smuzhiyun int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
113*4882a593Smuzhiyun resource_size_t *db_size,
114*4882a593Smuzhiyun u64 *db_data, int db_bit);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun extern const struct ntb_dev_ops intel_ntb3_ops;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #endif
119