xref: /OK3568_Linux_fs/kernel/drivers/nfc/nfcmrvl/spi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun  * Marvell NFC-over-SPI driver: SPI interface related functions
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2015, Marvell International Ltd.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This software file (the "File") is distributed by Marvell International
7*4882a593Smuzhiyun  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8*4882a593Smuzhiyun  * (the "License").  You may use, redistribute and/or modify this File in
9*4882a593Smuzhiyun  * accordance with the terms and conditions of the License, a copy of which
10*4882a593Smuzhiyun  * is available on the worldwide web at
11*4882a593Smuzhiyun  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
14*4882a593Smuzhiyun  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
15*4882a593Smuzhiyun  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
16*4882a593Smuzhiyun  * this warranty disclaimer.
17*4882a593Smuzhiyun  **/
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/pm_runtime.h>
22*4882a593Smuzhiyun #include <linux/nfc.h>
23*4882a593Smuzhiyun #include <linux/gpio.h>
24*4882a593Smuzhiyun #include <linux/of_irq.h>
25*4882a593Smuzhiyun #include <linux/of_gpio.h>
26*4882a593Smuzhiyun #include <net/nfc/nci.h>
27*4882a593Smuzhiyun #include <net/nfc/nci_core.h>
28*4882a593Smuzhiyun #include <linux/spi/spi.h>
29*4882a593Smuzhiyun #include "nfcmrvl.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define SPI_WAIT_HANDSHAKE	1
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct nfcmrvl_spi_drv_data {
34*4882a593Smuzhiyun 	unsigned long flags;
35*4882a593Smuzhiyun 	struct spi_device *spi;
36*4882a593Smuzhiyun 	struct nci_spi *nci_spi;
37*4882a593Smuzhiyun 	struct completion handshake_completion;
38*4882a593Smuzhiyun 	struct nfcmrvl_private *priv;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
nfcmrvl_spi_int_irq_thread_fn(int irq,void * drv_data_ptr)41*4882a593Smuzhiyun static irqreturn_t nfcmrvl_spi_int_irq_thread_fn(int irq, void *drv_data_ptr)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct nfcmrvl_spi_drv_data *drv_data = drv_data_ptr;
44*4882a593Smuzhiyun 	struct sk_buff *skb;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/*
47*4882a593Smuzhiyun 	 * Special case where we are waiting for SPI_INT deassertion to start a
48*4882a593Smuzhiyun 	 * transfer.
49*4882a593Smuzhiyun 	 */
50*4882a593Smuzhiyun 	if (test_and_clear_bit(SPI_WAIT_HANDSHAKE, &drv_data->flags)) {
51*4882a593Smuzhiyun 		complete(&drv_data->handshake_completion);
52*4882a593Smuzhiyun 		return IRQ_HANDLED;
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/* Normal case, SPI_INT deasserted by slave to trigger a master read */
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	skb = nci_spi_read(drv_data->nci_spi);
58*4882a593Smuzhiyun 	if (!skb) {
59*4882a593Smuzhiyun 		nfc_err(&drv_data->spi->dev, "failed to read spi packet");
60*4882a593Smuzhiyun 		return IRQ_HANDLED;
61*4882a593Smuzhiyun 	}
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	if (nfcmrvl_nci_recv_frame(drv_data->priv, skb) < 0)
64*4882a593Smuzhiyun 		nfc_err(&drv_data->spi->dev, "corrupted RX packet");
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	return IRQ_HANDLED;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
nfcmrvl_spi_nci_open(struct nfcmrvl_private * priv)69*4882a593Smuzhiyun static int nfcmrvl_spi_nci_open(struct nfcmrvl_private *priv)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
nfcmrvl_spi_nci_close(struct nfcmrvl_private * priv)74*4882a593Smuzhiyun static int nfcmrvl_spi_nci_close(struct nfcmrvl_private *priv)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
nfcmrvl_spi_nci_send(struct nfcmrvl_private * priv,struct sk_buff * skb)79*4882a593Smuzhiyun static int nfcmrvl_spi_nci_send(struct nfcmrvl_private *priv,
80*4882a593Smuzhiyun 				struct sk_buff *skb)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	struct nfcmrvl_spi_drv_data *drv_data = priv->drv_data;
83*4882a593Smuzhiyun 	int err;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* Reinit completion for slave handshake */
86*4882a593Smuzhiyun 	reinit_completion(&drv_data->handshake_completion);
87*4882a593Smuzhiyun 	set_bit(SPI_WAIT_HANDSHAKE, &drv_data->flags);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/*
90*4882a593Smuzhiyun 	 * Append a dummy byte at the end of SPI frame. This is due to a
91*4882a593Smuzhiyun 	 * specific DMA implementation in the controller
92*4882a593Smuzhiyun 	 */
93*4882a593Smuzhiyun 	skb_put(skb, 1);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* Send the SPI packet */
96*4882a593Smuzhiyun 	err = nci_spi_send(drv_data->nci_spi, &drv_data->handshake_completion,
97*4882a593Smuzhiyun 			   skb);
98*4882a593Smuzhiyun 	if (err)
99*4882a593Smuzhiyun 		nfc_err(priv->dev, "spi_send failed %d", err);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return err;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
nfcmrvl_spi_nci_update_config(struct nfcmrvl_private * priv,const void * param)104*4882a593Smuzhiyun static void nfcmrvl_spi_nci_update_config(struct nfcmrvl_private *priv,
105*4882a593Smuzhiyun 					  const void *param)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct nfcmrvl_spi_drv_data *drv_data = priv->drv_data;
108*4882a593Smuzhiyun 	const struct nfcmrvl_fw_spi_config *config = param;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	drv_data->nci_spi->xfer_speed_hz = config->clk;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static struct nfcmrvl_if_ops spi_ops = {
114*4882a593Smuzhiyun 	.nci_open = nfcmrvl_spi_nci_open,
115*4882a593Smuzhiyun 	.nci_close = nfcmrvl_spi_nci_close,
116*4882a593Smuzhiyun 	.nci_send = nfcmrvl_spi_nci_send,
117*4882a593Smuzhiyun 	.nci_update_config = nfcmrvl_spi_nci_update_config,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
nfcmrvl_spi_parse_dt(struct device_node * node,struct nfcmrvl_platform_data * pdata)120*4882a593Smuzhiyun static int nfcmrvl_spi_parse_dt(struct device_node *node,
121*4882a593Smuzhiyun 				struct nfcmrvl_platform_data *pdata)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	int ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	ret = nfcmrvl_parse_dt(node, pdata);
126*4882a593Smuzhiyun 	if (ret < 0) {
127*4882a593Smuzhiyun 		pr_err("Failed to get generic entries\n");
128*4882a593Smuzhiyun 		return ret;
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	ret = irq_of_parse_and_map(node, 0);
132*4882a593Smuzhiyun 	if (!ret) {
133*4882a593Smuzhiyun 		pr_err("Unable to get irq\n");
134*4882a593Smuzhiyun 		return -EINVAL;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 	pdata->irq = ret;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
nfcmrvl_spi_probe(struct spi_device * spi)141*4882a593Smuzhiyun static int nfcmrvl_spi_probe(struct spi_device *spi)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	struct nfcmrvl_platform_data *pdata;
144*4882a593Smuzhiyun 	struct nfcmrvl_platform_data config;
145*4882a593Smuzhiyun 	struct nfcmrvl_spi_drv_data *drv_data;
146*4882a593Smuzhiyun 	int ret = 0;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	drv_data = devm_kzalloc(&spi->dev, sizeof(*drv_data), GFP_KERNEL);
149*4882a593Smuzhiyun 	if (!drv_data)
150*4882a593Smuzhiyun 		return -ENOMEM;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	drv_data->spi = spi;
153*4882a593Smuzhiyun 	drv_data->priv = NULL;
154*4882a593Smuzhiyun 	spi_set_drvdata(spi, drv_data);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	pdata = spi->dev.platform_data;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	if (!pdata && spi->dev.of_node)
159*4882a593Smuzhiyun 		if (nfcmrvl_spi_parse_dt(spi->dev.of_node, &config) == 0)
160*4882a593Smuzhiyun 			pdata = &config;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (!pdata)
163*4882a593Smuzhiyun 		return -EINVAL;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(&drv_data->spi->dev, pdata->irq,
166*4882a593Smuzhiyun 					NULL, nfcmrvl_spi_int_irq_thread_fn,
167*4882a593Smuzhiyun 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
168*4882a593Smuzhiyun 					"nfcmrvl_spi_int", drv_data);
169*4882a593Smuzhiyun 	if (ret < 0) {
170*4882a593Smuzhiyun 		nfc_err(&drv_data->spi->dev, "Unable to register IRQ handler");
171*4882a593Smuzhiyun 		return -ENODEV;
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	drv_data->priv = nfcmrvl_nci_register_dev(NFCMRVL_PHY_SPI,
175*4882a593Smuzhiyun 						  drv_data, &spi_ops,
176*4882a593Smuzhiyun 						  &drv_data->spi->dev,
177*4882a593Smuzhiyun 						  pdata);
178*4882a593Smuzhiyun 	if (IS_ERR(drv_data->priv))
179*4882a593Smuzhiyun 		return PTR_ERR(drv_data->priv);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	drv_data->priv->support_fw_dnld = true;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	drv_data->nci_spi = nci_spi_allocate_spi(drv_data->spi, 0, 10,
184*4882a593Smuzhiyun 						 drv_data->priv->ndev);
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	/* Init completion for slave handshake */
187*4882a593Smuzhiyun 	init_completion(&drv_data->handshake_completion);
188*4882a593Smuzhiyun 	return 0;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
nfcmrvl_spi_remove(struct spi_device * spi)191*4882a593Smuzhiyun static int nfcmrvl_spi_remove(struct spi_device *spi)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct nfcmrvl_spi_drv_data *drv_data = spi_get_drvdata(spi);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	nfcmrvl_nci_unregister_dev(drv_data->priv);
196*4882a593Smuzhiyun 	return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static const struct of_device_id of_nfcmrvl_spi_match[] = {
200*4882a593Smuzhiyun 	{ .compatible = "marvell,nfc-spi", },
201*4882a593Smuzhiyun 	{},
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_nfcmrvl_spi_match);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct spi_device_id nfcmrvl_spi_id_table[] = {
206*4882a593Smuzhiyun 	{ "nfcmrvl_spi", 0 },
207*4882a593Smuzhiyun 	{ }
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, nfcmrvl_spi_id_table);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun static struct spi_driver nfcmrvl_spi_driver = {
212*4882a593Smuzhiyun 	.probe		= nfcmrvl_spi_probe,
213*4882a593Smuzhiyun 	.remove		= nfcmrvl_spi_remove,
214*4882a593Smuzhiyun 	.id_table	= nfcmrvl_spi_id_table,
215*4882a593Smuzhiyun 	.driver		= {
216*4882a593Smuzhiyun 		.name		= "nfcmrvl_spi",
217*4882a593Smuzhiyun 		.owner		= THIS_MODULE,
218*4882a593Smuzhiyun 		.of_match_table	= of_match_ptr(of_nfcmrvl_spi_match),
219*4882a593Smuzhiyun 	},
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun module_spi_driver(nfcmrvl_spi_driver);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun MODULE_AUTHOR("Marvell International Ltd.");
225*4882a593Smuzhiyun MODULE_DESCRIPTION("Marvell NFC-over-SPI driver");
226*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
227