1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /* ZD1211 USB-WLAN driver for Linux
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ZD_MAC_H
9*4882a593Smuzhiyun #define _ZD_MAC_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <net/mac80211.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "zd_chip.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct zd_ctrlset {
17*4882a593Smuzhiyun u8 modulation;
18*4882a593Smuzhiyun __le16 tx_length;
19*4882a593Smuzhiyun u8 control;
20*4882a593Smuzhiyun /* stores only the difference to tx_length on ZD1211B */
21*4882a593Smuzhiyun __le16 packet_length;
22*4882a593Smuzhiyun __le16 current_length;
23*4882a593Smuzhiyun u8 service;
24*4882a593Smuzhiyun __le16 next_frame_length;
25*4882a593Smuzhiyun } __packed;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define ZD_CS_RESERVED_SIZE 25
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* The field modulation of struct zd_ctrlset controls the bit rate, the use
30*4882a593Smuzhiyun * of short or long preambles in 802.11b (CCK mode) or the use of 802.11a or
31*4882a593Smuzhiyun * 802.11g in OFDM mode.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * The term zd-rate is used for the combination of the modulation type flag
34*4882a593Smuzhiyun * and the "pure" rate value.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define ZD_PURE_RATE_MASK 0x0f
37*4882a593Smuzhiyun #define ZD_MODULATION_TYPE_MASK 0x10
38*4882a593Smuzhiyun #define ZD_RATE_MASK (ZD_PURE_RATE_MASK|ZD_MODULATION_TYPE_MASK)
39*4882a593Smuzhiyun #define ZD_PURE_RATE(modulation) ((modulation) & ZD_PURE_RATE_MASK)
40*4882a593Smuzhiyun #define ZD_MODULATION_TYPE(modulation) ((modulation) & ZD_MODULATION_TYPE_MASK)
41*4882a593Smuzhiyun #define ZD_RATE(modulation) ((modulation) & ZD_RATE_MASK)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* The two possible modulation types. Notify that 802.11b doesn't use the CCK
44*4882a593Smuzhiyun * codeing for the 1 and 2 MBit/s rate. We stay with the term here to remain
45*4882a593Smuzhiyun * consistent with uses the term at other places.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun #define ZD_CCK 0x00
48*4882a593Smuzhiyun #define ZD_OFDM 0x10
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* The ZD1211 firmware uses proprietary encodings of the 802.11b (CCK) rates.
51*4882a593Smuzhiyun * For OFDM the PLCP rate encodings are used. We combine these "pure" rates
52*4882a593Smuzhiyun * with the modulation type flag and call the resulting values zd-rates.
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun #define ZD_CCK_RATE_1M (ZD_CCK|0x00)
55*4882a593Smuzhiyun #define ZD_CCK_RATE_2M (ZD_CCK|0x01)
56*4882a593Smuzhiyun #define ZD_CCK_RATE_5_5M (ZD_CCK|0x02)
57*4882a593Smuzhiyun #define ZD_CCK_RATE_11M (ZD_CCK|0x03)
58*4882a593Smuzhiyun #define ZD_OFDM_RATE_6M (ZD_OFDM|ZD_OFDM_PLCP_RATE_6M)
59*4882a593Smuzhiyun #define ZD_OFDM_RATE_9M (ZD_OFDM|ZD_OFDM_PLCP_RATE_9M)
60*4882a593Smuzhiyun #define ZD_OFDM_RATE_12M (ZD_OFDM|ZD_OFDM_PLCP_RATE_12M)
61*4882a593Smuzhiyun #define ZD_OFDM_RATE_18M (ZD_OFDM|ZD_OFDM_PLCP_RATE_18M)
62*4882a593Smuzhiyun #define ZD_OFDM_RATE_24M (ZD_OFDM|ZD_OFDM_PLCP_RATE_24M)
63*4882a593Smuzhiyun #define ZD_OFDM_RATE_36M (ZD_OFDM|ZD_OFDM_PLCP_RATE_36M)
64*4882a593Smuzhiyun #define ZD_OFDM_RATE_48M (ZD_OFDM|ZD_OFDM_PLCP_RATE_48M)
65*4882a593Smuzhiyun #define ZD_OFDM_RATE_54M (ZD_OFDM|ZD_OFDM_PLCP_RATE_54M)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* The bit 5 of the zd_ctrlset modulation field controls the preamble in CCK
68*4882a593Smuzhiyun * mode or the 802.11a/802.11g selection in OFDM mode.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun #define ZD_CCK_PREA_LONG 0x00
71*4882a593Smuzhiyun #define ZD_CCK_PREA_SHORT 0x20
72*4882a593Smuzhiyun #define ZD_OFDM_MODE_11G 0x00
73*4882a593Smuzhiyun #define ZD_OFDM_MODE_11A 0x20
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* zd_ctrlset control field */
76*4882a593Smuzhiyun #define ZD_CS_NEED_RANDOM_BACKOFF 0x01
77*4882a593Smuzhiyun #define ZD_CS_NO_ACK 0x02
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define ZD_CS_FRAME_TYPE_MASK 0x0c
80*4882a593Smuzhiyun #define ZD_CS_DATA_FRAME 0x00
81*4882a593Smuzhiyun #define ZD_CS_PS_POLL_FRAME 0x04
82*4882a593Smuzhiyun #define ZD_CS_MANAGEMENT_FRAME 0x08
83*4882a593Smuzhiyun #define ZD_CS_NO_SEQUENCE_CTL_FRAME 0x0c
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define ZD_CS_WAKE_DESTINATION 0x10
86*4882a593Smuzhiyun #define ZD_CS_RTS 0x20
87*4882a593Smuzhiyun #define ZD_CS_ENCRYPT 0x40
88*4882a593Smuzhiyun #define ZD_CS_SELF_CTS 0x80
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Incoming frames are prepended by a PLCP header */
91*4882a593Smuzhiyun #define ZD_PLCP_HEADER_SIZE 5
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct rx_length_info {
94*4882a593Smuzhiyun __le16 length[3];
95*4882a593Smuzhiyun __le16 tag;
96*4882a593Smuzhiyun } __packed;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define RX_LENGTH_INFO_TAG 0x697e
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct rx_status {
101*4882a593Smuzhiyun u8 signal_quality_cck;
102*4882a593Smuzhiyun /* rssi */
103*4882a593Smuzhiyun u8 signal_strength;
104*4882a593Smuzhiyun u8 signal_quality_ofdm;
105*4882a593Smuzhiyun u8 decryption_type;
106*4882a593Smuzhiyun u8 frame_status;
107*4882a593Smuzhiyun } __packed;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* rx_status field decryption_type */
110*4882a593Smuzhiyun #define ZD_RX_NO_WEP 0
111*4882a593Smuzhiyun #define ZD_RX_WEP64 1
112*4882a593Smuzhiyun #define ZD_RX_TKIP 2
113*4882a593Smuzhiyun #define ZD_RX_AES 4
114*4882a593Smuzhiyun #define ZD_RX_WEP128 5
115*4882a593Smuzhiyun #define ZD_RX_WEP256 6
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* rx_status field frame_status */
118*4882a593Smuzhiyun #define ZD_RX_FRAME_MODULATION_MASK 0x01
119*4882a593Smuzhiyun #define ZD_RX_CCK 0x00
120*4882a593Smuzhiyun #define ZD_RX_OFDM 0x01
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define ZD_RX_TIMEOUT_ERROR 0x02
123*4882a593Smuzhiyun #define ZD_RX_FIFO_OVERRUN_ERROR 0x04
124*4882a593Smuzhiyun #define ZD_RX_DECRYPTION_ERROR 0x08
125*4882a593Smuzhiyun #define ZD_RX_CRC32_ERROR 0x10
126*4882a593Smuzhiyun #define ZD_RX_NO_ADDR1_MATCH_ERROR 0x20
127*4882a593Smuzhiyun #define ZD_RX_CRC16_ERROR 0x40
128*4882a593Smuzhiyun #define ZD_RX_ERROR 0x80
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun struct tx_retry_rate {
131*4882a593Smuzhiyun int count; /* number of valid element in rate[] array */
132*4882a593Smuzhiyun int rate[10]; /* retry rates, described by an index in zd_rates[] */
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun struct tx_status {
136*4882a593Smuzhiyun u8 type; /* must always be 0x01 : USB_INT_TYPE */
137*4882a593Smuzhiyun u8 id; /* must always be 0xa0 : USB_INT_ID_RETRY_FAILED */
138*4882a593Smuzhiyun u8 rate;
139*4882a593Smuzhiyun u8 pad;
140*4882a593Smuzhiyun u8 mac[ETH_ALEN];
141*4882a593Smuzhiyun u8 retry;
142*4882a593Smuzhiyun u8 failure;
143*4882a593Smuzhiyun } __packed;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun enum mac_flags {
146*4882a593Smuzhiyun MAC_FIXED_CHANNEL = 0x01,
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun struct housekeeping {
150*4882a593Smuzhiyun struct delayed_work link_led_work;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun struct beacon {
154*4882a593Smuzhiyun struct delayed_work watchdog_work;
155*4882a593Smuzhiyun struct sk_buff *cur_beacon;
156*4882a593Smuzhiyun unsigned long last_update;
157*4882a593Smuzhiyun u16 interval;
158*4882a593Smuzhiyun u8 period;
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun enum zd_device_flags {
162*4882a593Smuzhiyun ZD_DEVICE_RUNNING,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun #define ZD_MAC_STATS_BUFFER_SIZE 16
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun #define ZD_MAC_MAX_ACK_WAITERS 50
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun struct zd_mac {
170*4882a593Smuzhiyun struct zd_chip chip;
171*4882a593Smuzhiyun spinlock_t lock;
172*4882a593Smuzhiyun spinlock_t intr_lock;
173*4882a593Smuzhiyun struct ieee80211_hw *hw;
174*4882a593Smuzhiyun struct ieee80211_vif *vif;
175*4882a593Smuzhiyun struct housekeeping housekeeping;
176*4882a593Smuzhiyun struct beacon beacon;
177*4882a593Smuzhiyun struct work_struct set_rts_cts_work;
178*4882a593Smuzhiyun struct work_struct process_intr;
179*4882a593Smuzhiyun struct zd_mc_hash multicast_hash;
180*4882a593Smuzhiyun u8 intr_buffer[USB_MAX_EP_INT_BUFFER];
181*4882a593Smuzhiyun u8 regdomain;
182*4882a593Smuzhiyun u8 default_regdomain;
183*4882a593Smuzhiyun u8 channel;
184*4882a593Smuzhiyun int type;
185*4882a593Smuzhiyun int associated;
186*4882a593Smuzhiyun unsigned long flags;
187*4882a593Smuzhiyun struct sk_buff_head ack_wait_queue;
188*4882a593Smuzhiyun struct ieee80211_channel channels[14];
189*4882a593Smuzhiyun struct ieee80211_rate rates[12];
190*4882a593Smuzhiyun struct ieee80211_supported_band band;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Short preamble (used for RTS/CTS) */
193*4882a593Smuzhiyun unsigned int short_preamble:1;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* whether to pass frames with CRC errors to stack */
196*4882a593Smuzhiyun unsigned int pass_failed_fcs:1;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* whether to pass control frames to stack */
199*4882a593Smuzhiyun unsigned int pass_ctrl:1;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun /* whether we have received a 802.11 ACK that is pending */
202*4882a593Smuzhiyun unsigned int ack_pending:1;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* signal strength of the last 802.11 ACK received */
205*4882a593Smuzhiyun int ack_signal;
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun #define ZD_REGDOMAIN_FCC 0x10
209*4882a593Smuzhiyun #define ZD_REGDOMAIN_IC 0x20
210*4882a593Smuzhiyun #define ZD_REGDOMAIN_ETSI 0x30
211*4882a593Smuzhiyun #define ZD_REGDOMAIN_SPAIN 0x31
212*4882a593Smuzhiyun #define ZD_REGDOMAIN_FRANCE 0x32
213*4882a593Smuzhiyun #define ZD_REGDOMAIN_JAPAN_2 0x40
214*4882a593Smuzhiyun #define ZD_REGDOMAIN_JAPAN 0x41
215*4882a593Smuzhiyun #define ZD_REGDOMAIN_JAPAN_3 0x49
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun enum {
218*4882a593Smuzhiyun MIN_CHANNEL24 = 1,
219*4882a593Smuzhiyun MAX_CHANNEL24 = 14,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #define ZD_PLCP_SERVICE_LENGTH_EXTENSION 0x80
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun struct ofdm_plcp_header {
225*4882a593Smuzhiyun u8 prefix[3];
226*4882a593Smuzhiyun __le16 service;
227*4882a593Smuzhiyun } __packed;
228*4882a593Smuzhiyun
zd_ofdm_plcp_header_rate(const struct ofdm_plcp_header * header)229*4882a593Smuzhiyun static inline u8 zd_ofdm_plcp_header_rate(const struct ofdm_plcp_header *header)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun return header->prefix[0] & 0xf;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* The following defines give the encoding of the 4-bit rate field in the
235*4882a593Smuzhiyun * OFDM (802.11a/802.11g) PLCP header. Notify that these values are used to
236*4882a593Smuzhiyun * define the zd-rate values for OFDM.
237*4882a593Smuzhiyun *
238*4882a593Smuzhiyun * See the struct zd_ctrlset definition in zd_mac.h.
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_6M 0xb
241*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_9M 0xf
242*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_12M 0xa
243*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_18M 0xe
244*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_24M 0x9
245*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_36M 0xd
246*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_48M 0x8
247*4882a593Smuzhiyun #define ZD_OFDM_PLCP_RATE_54M 0xc
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun struct cck_plcp_header {
250*4882a593Smuzhiyun u8 signal;
251*4882a593Smuzhiyun u8 service;
252*4882a593Smuzhiyun __le16 length;
253*4882a593Smuzhiyun __le16 crc16;
254*4882a593Smuzhiyun } __packed;
255*4882a593Smuzhiyun
zd_cck_plcp_header_signal(const struct cck_plcp_header * header)256*4882a593Smuzhiyun static inline u8 zd_cck_plcp_header_signal(const struct cck_plcp_header *header)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun return header->signal;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* These defines give the encodings of the signal field in the 802.11b PLCP
262*4882a593Smuzhiyun * header. The signal field gives the bit rate of the following packet. Even
263*4882a593Smuzhiyun * if technically wrong we use CCK here also for the 1 MBit/s and 2 MBit/s
264*4882a593Smuzhiyun * rate to stay consistent with Zydas and our use of the term.
265*4882a593Smuzhiyun *
266*4882a593Smuzhiyun * Notify that these values are *not* used in the zd-rates.
267*4882a593Smuzhiyun */
268*4882a593Smuzhiyun #define ZD_CCK_PLCP_SIGNAL_1M 0x0a
269*4882a593Smuzhiyun #define ZD_CCK_PLCP_SIGNAL_2M 0x14
270*4882a593Smuzhiyun #define ZD_CCK_PLCP_SIGNAL_5M5 0x37
271*4882a593Smuzhiyun #define ZD_CCK_PLCP_SIGNAL_11M 0x6e
272*4882a593Smuzhiyun
zd_hw_mac(struct ieee80211_hw * hw)273*4882a593Smuzhiyun static inline struct zd_mac *zd_hw_mac(struct ieee80211_hw *hw)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun return hw->priv;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
zd_chip_to_mac(struct zd_chip * chip)278*4882a593Smuzhiyun static inline struct zd_mac *zd_chip_to_mac(struct zd_chip *chip)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun return container_of(chip, struct zd_mac, chip);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
zd_usb_to_mac(struct zd_usb * usb)283*4882a593Smuzhiyun static inline struct zd_mac *zd_usb_to_mac(struct zd_usb *usb)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun return zd_chip_to_mac(zd_usb_to_chip(usb));
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
zd_mac_get_perm_addr(struct zd_mac * mac)288*4882a593Smuzhiyun static inline u8 *zd_mac_get_perm_addr(struct zd_mac *mac)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun return mac->hw->wiphy->perm_addr;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun #define zd_mac_dev(mac) (zd_chip_dev(&(mac)->chip))
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun struct ieee80211_hw *zd_mac_alloc_hw(struct usb_interface *intf);
296*4882a593Smuzhiyun void zd_mac_clear(struct zd_mac *mac);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun int zd_mac_preinit_hw(struct ieee80211_hw *hw);
299*4882a593Smuzhiyun int zd_mac_init_hw(struct ieee80211_hw *hw);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length);
302*4882a593Smuzhiyun void zd_mac_tx_failed(struct urb *urb);
303*4882a593Smuzhiyun void zd_mac_tx_to_dev(struct sk_buff *skb, int error);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun int zd_op_start(struct ieee80211_hw *hw);
306*4882a593Smuzhiyun void zd_op_stop(struct ieee80211_hw *hw);
307*4882a593Smuzhiyun int zd_restore_settings(struct zd_mac *mac);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun #ifdef DEBUG
310*4882a593Smuzhiyun void zd_dump_rx_status(const struct rx_status *status);
311*4882a593Smuzhiyun #else
312*4882a593Smuzhiyun #define zd_dump_rx_status(status)
313*4882a593Smuzhiyun #endif /* DEBUG */
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun #endif /* _ZD_MAC_H */
316