xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/wl3501.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __WL3501_H__
3*4882a593Smuzhiyun #define __WL3501_H__
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/spinlock.h>
6*4882a593Smuzhiyun #include <linux/ieee80211.h>
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /* define for WLA 2.0 */
9*4882a593Smuzhiyun #define WL3501_BLKSZ 256
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun  * ID for input Signals of DRIVER block
12*4882a593Smuzhiyun  * bit[7-5] is block ID: 000
13*4882a593Smuzhiyun  * bit[4-0] is signal ID
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun enum wl3501_signals {
16*4882a593Smuzhiyun 	WL3501_SIG_ALARM,
17*4882a593Smuzhiyun 	WL3501_SIG_MD_CONFIRM,
18*4882a593Smuzhiyun 	WL3501_SIG_MD_IND,
19*4882a593Smuzhiyun 	WL3501_SIG_ASSOC_CONFIRM,
20*4882a593Smuzhiyun 	WL3501_SIG_ASSOC_IND,
21*4882a593Smuzhiyun 	WL3501_SIG_AUTH_CONFIRM,
22*4882a593Smuzhiyun 	WL3501_SIG_AUTH_IND,
23*4882a593Smuzhiyun 	WL3501_SIG_DEAUTH_CONFIRM,
24*4882a593Smuzhiyun 	WL3501_SIG_DEAUTH_IND,
25*4882a593Smuzhiyun 	WL3501_SIG_DISASSOC_CONFIRM,
26*4882a593Smuzhiyun 	WL3501_SIG_DISASSOC_IND,
27*4882a593Smuzhiyun 	WL3501_SIG_GET_CONFIRM,
28*4882a593Smuzhiyun 	WL3501_SIG_JOIN_CONFIRM,
29*4882a593Smuzhiyun 	WL3501_SIG_PWR_MGMT_CONFIRM,
30*4882a593Smuzhiyun 	WL3501_SIG_REASSOC_CONFIRM,
31*4882a593Smuzhiyun 	WL3501_SIG_REASSOC_IND,
32*4882a593Smuzhiyun 	WL3501_SIG_SCAN_CONFIRM,
33*4882a593Smuzhiyun 	WL3501_SIG_SET_CONFIRM,
34*4882a593Smuzhiyun 	WL3501_SIG_START_CONFIRM,
35*4882a593Smuzhiyun 	WL3501_SIG_RESYNC_CONFIRM,
36*4882a593Smuzhiyun 	WL3501_SIG_SITE_CONFIRM,
37*4882a593Smuzhiyun 	WL3501_SIG_SAVE_CONFIRM,
38*4882a593Smuzhiyun 	WL3501_SIG_RFTEST_CONFIRM,
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * ID for input Signals of MLME block
41*4882a593Smuzhiyun  * bit[7-5] is block ID: 010
42*4882a593Smuzhiyun  * bit[4-0] is signal ID
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun 	WL3501_SIG_ASSOC_REQ = 0x20,
45*4882a593Smuzhiyun 	WL3501_SIG_AUTH_REQ,
46*4882a593Smuzhiyun 	WL3501_SIG_DEAUTH_REQ,
47*4882a593Smuzhiyun 	WL3501_SIG_DISASSOC_REQ,
48*4882a593Smuzhiyun 	WL3501_SIG_GET_REQ,
49*4882a593Smuzhiyun 	WL3501_SIG_JOIN_REQ,
50*4882a593Smuzhiyun 	WL3501_SIG_PWR_MGMT_REQ,
51*4882a593Smuzhiyun 	WL3501_SIG_REASSOC_REQ,
52*4882a593Smuzhiyun 	WL3501_SIG_SCAN_REQ,
53*4882a593Smuzhiyun 	WL3501_SIG_SET_REQ,
54*4882a593Smuzhiyun 	WL3501_SIG_START_REQ,
55*4882a593Smuzhiyun 	WL3501_SIG_MD_REQ,
56*4882a593Smuzhiyun 	WL3501_SIG_RESYNC_REQ,
57*4882a593Smuzhiyun 	WL3501_SIG_SITE_REQ,
58*4882a593Smuzhiyun 	WL3501_SIG_SAVE_REQ,
59*4882a593Smuzhiyun 	WL3501_SIG_RF_TEST_REQ,
60*4882a593Smuzhiyun 	WL3501_SIG_MM_CONFIRM = 0x60,
61*4882a593Smuzhiyun 	WL3501_SIG_MM_IND,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun enum wl3501_mib_attribs {
65*4882a593Smuzhiyun 	WL3501_MIB_ATTR_STATION_ID,
66*4882a593Smuzhiyun 	WL3501_MIB_ATTR_AUTH_ALGORITHMS,
67*4882a593Smuzhiyun 	WL3501_MIB_ATTR_AUTH_TYPE,
68*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MEDIUM_OCCUPANCY_LIMIT,
69*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CF_POLLABLE,
70*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CFP_PERIOD,
71*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CFPMAX_DURATION,
72*4882a593Smuzhiyun 	WL3501_MIB_ATTR_AUTH_RESP_TMOUT,
73*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_DTIMS,
74*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PRIV_OPT_IMPLEMENTED,
75*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PRIV_INVOKED,
76*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_DEFAULT_KEYS,
77*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_DEFAULT_KEY_ID,
78*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_KEY_MAPPINGS,
79*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_KEY_MAPPINGS_LEN,
80*4882a593Smuzhiyun 	WL3501_MIB_ATTR_EXCLUDE_UNENCRYPTED,
81*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_ICV_ERROR_COUNT,
82*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_UNDECRYPTABLE_COUNT,
83*4882a593Smuzhiyun 	WL3501_MIB_ATTR_WEP_EXCLUDED_COUNT,
84*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MAC_ADDR,
85*4882a593Smuzhiyun 	WL3501_MIB_ATTR_GROUP_ADDRS,
86*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RTS_THRESHOLD,
87*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SHORT_RETRY_LIMIT,
88*4882a593Smuzhiyun 	WL3501_MIB_ATTR_LONG_RETRY_LIMIT,
89*4882a593Smuzhiyun 	WL3501_MIB_ATTR_FRAG_THRESHOLD,
90*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MAX_TX_MSDU_LIFETIME,
91*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MAX_RX_LIFETIME,
92*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MANUFACTURER_ID,
93*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PRODUCT_ID,
94*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_FRAG_COUNT,
95*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MULTICAST_TX_FRAME_COUNT,
96*4882a593Smuzhiyun 	WL3501_MIB_ATTR_FAILED_COUNT,
97*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_FRAG_COUNT,
98*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MULTICAST_RX_COUNT,
99*4882a593Smuzhiyun 	WL3501_MIB_ATTR_FCS_ERROR_COUNT,
100*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RETRY_COUNT,
101*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MULTIPLE_RETRY_COUNT,
102*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RTS_SUCCESS_COUNT,
103*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RTS_FAILURE_COUNT,
104*4882a593Smuzhiyun 	WL3501_MIB_ATTR_ACK_FAILURE_COUNT,
105*4882a593Smuzhiyun 	WL3501_MIB_ATTR_FRAME_DUPLICATE_COUNT,
106*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PHY_TYPE,
107*4882a593Smuzhiyun 	WL3501_MIB_ATTR_REG_DOMAINS_SUPPORT,
108*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_REG_DOMAIN,
109*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SLOT_TIME,
110*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CCA_TIME,
111*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_TX_TURNAROUND_TIME,
112*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PLCP_DELAY,
113*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_TX_SWITCH_TIME,
114*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_RAMP_ON_TIME,
115*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_RF_DELAY,
116*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SIFS_TIME,
117*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_RF_DELAY,
118*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RX_PLCP_DELAY,
119*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MAC_PROCESSING_DELAY,
120*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_RAMP_OFF_TIME,
121*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PREAMBLE_LEN,
122*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PLCP_HEADER_LEN,
123*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MPDU_DURATION_FACTOR,
124*4882a593Smuzhiyun 	WL3501_MIB_ATTR_AIR_PROPAGATION_TIME,
125*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TEMP_TYPE,
126*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CW_MIN,
127*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CW_MAX,
128*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SUPPORT_DATA_RATES_TX,
129*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SUPPORT_DATA_RATES_RX,
130*4882a593Smuzhiyun 	WL3501_MIB_ATTR_MPDU_MAX_LEN,
131*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SUPPORT_TX_ANTENNAS,
132*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_TX_ANTENNA,
133*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SUPPORT_RX_ANTENNAS,
134*4882a593Smuzhiyun 	WL3501_MIB_ATTR_DIVERSITY_SUPPORT,
135*4882a593Smuzhiyun 	WL3501_MIB_ATTR_DIVERSITY_SELECTION_RS,
136*4882a593Smuzhiyun 	WL3501_MIB_ATTR_NR_SUPPORTED_PWR_LEVELS,
137*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL1,
138*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL2,
139*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL3,
140*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL4,
141*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL5,
142*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL6,
143*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL7,
144*4882a593Smuzhiyun 	WL3501_MIB_ATTR_TX_PWR_LEVEL8,
145*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_TX_PWR_LEVEL,
146*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_CHAN,
147*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CCA_MODE_SUPPORTED,
148*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_CCA_MODE,
149*4882a593Smuzhiyun 	WL3501_MIB_ATTR_ED_THRESHOLD,
150*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SINTHESIZER_LOCKED,
151*4882a593Smuzhiyun 	WL3501_MIB_ATTR_CURRENT_PWR_STATE,
152*4882a593Smuzhiyun 	WL3501_MIB_ATTR_DOZE_TURNON_TIME,
153*4882a593Smuzhiyun 	WL3501_MIB_ATTR_RCR33,
154*4882a593Smuzhiyun 	WL3501_MIB_ATTR_DEFAULT_CHAN,
155*4882a593Smuzhiyun 	WL3501_MIB_ATTR_SSID,
156*4882a593Smuzhiyun 	WL3501_MIB_ATTR_PWR_MGMT_ENABLE,
157*4882a593Smuzhiyun 	WL3501_MIB_ATTR_NET_CAPABILITY,
158*4882a593Smuzhiyun 	WL3501_MIB_ATTR_ROUTING,
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun enum wl3501_net_type {
162*4882a593Smuzhiyun 	WL3501_NET_TYPE_INFRA,
163*4882a593Smuzhiyun 	WL3501_NET_TYPE_ADHOC,
164*4882a593Smuzhiyun 	WL3501_NET_TYPE_ANY_BSS,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun enum wl3501_scan_type {
168*4882a593Smuzhiyun 	WL3501_SCAN_TYPE_ACTIVE,
169*4882a593Smuzhiyun 	WL3501_SCAN_TYPE_PASSIVE,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun enum wl3501_tx_result {
173*4882a593Smuzhiyun 	WL3501_TX_RESULT_SUCCESS,
174*4882a593Smuzhiyun 	WL3501_TX_RESULT_NO_BSS,
175*4882a593Smuzhiyun 	WL3501_TX_RESULT_RETRY_LIMIT,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun enum wl3501_sys_type {
179*4882a593Smuzhiyun 	WL3501_SYS_TYPE_OPEN,
180*4882a593Smuzhiyun 	WL3501_SYS_TYPE_SHARE_KEY,
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun enum wl3501_status {
184*4882a593Smuzhiyun 	WL3501_STATUS_SUCCESS,
185*4882a593Smuzhiyun 	WL3501_STATUS_INVALID,
186*4882a593Smuzhiyun 	WL3501_STATUS_TIMEOUT,
187*4882a593Smuzhiyun 	WL3501_STATUS_REFUSED,
188*4882a593Smuzhiyun 	WL3501_STATUS_MANY_REQ,
189*4882a593Smuzhiyun 	WL3501_STATUS_ALREADY_BSS,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #define WL3501_MGMT_CAPABILITY_ESS		0x0001  /* see 802.11 p.58 */
193*4882a593Smuzhiyun #define WL3501_MGMT_CAPABILITY_IBSS		0x0002  /*      - " -	   */
194*4882a593Smuzhiyun #define WL3501_MGMT_CAPABILITY_CF_POLLABLE	0x0004  /*      - " -	   */
195*4882a593Smuzhiyun #define WL3501_MGMT_CAPABILITY_CF_POLL_REQUEST	0x0008  /*      - " -	   */
196*4882a593Smuzhiyun #define WL3501_MGMT_CAPABILITY_PRIVACY		0x0010  /*      - " -	   */
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #define IW_REG_DOMAIN_FCC	0x10	/* Channel 1 to 11	USA    */
199*4882a593Smuzhiyun #define IW_REG_DOMAIN_DOC	0x20	/* Channel 1 to 11	Canada */
200*4882a593Smuzhiyun #define IW_REG_DOMAIN_ETSI	0x30	/* Channel 1 to 13	Europe */
201*4882a593Smuzhiyun #define IW_REG_DOMAIN_SPAIN	0x31	/* Channel 10 to 11	Spain  */
202*4882a593Smuzhiyun #define IW_REG_DOMAIN_FRANCE	0x32	/* Channel 10 to 13	France */
203*4882a593Smuzhiyun #define IW_REG_DOMAIN_MKK	0x40	/* Channel 14		Japan  */
204*4882a593Smuzhiyun #define IW_REG_DOMAIN_MKK1	0x41	/* Channel 1-14		Japan  */
205*4882a593Smuzhiyun #define IW_REG_DOMAIN_ISRAEL	0x50	/* Channel 3 - 9	Israel */
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun #define IW_MGMT_RATE_LABEL_MANDATORY 128 /* MSB */
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun enum iw_mgmt_rate_labels {
210*4882a593Smuzhiyun 	IW_MGMT_RATE_LABEL_1MBIT   = 2,
211*4882a593Smuzhiyun 	IW_MGMT_RATE_LABEL_2MBIT   = 4,
212*4882a593Smuzhiyun 	IW_MGMT_RATE_LABEL_5_5MBIT = 11,
213*4882a593Smuzhiyun 	IW_MGMT_RATE_LABEL_11MBIT  = 22,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun enum iw_mgmt_info_element_ids {
217*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_SSID,		  /* Service Set Identity */
218*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_SUPPORTED_RATES,
219*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_FH_PARAMETER_SET,
220*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_DS_PARAMETER_SET,
221*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_CS_PARAMETER_SET,
222*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_CS_TIM,		  /* Traffic Information Map */
223*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_IBSS_PARAMETER_SET,
224*4882a593Smuzhiyun 	/* 7-15: Reserved, unused */
225*4882a593Smuzhiyun 	IW_MGMT_INFO_ELEMENT_CHALLENGE_TEXT = 16,
226*4882a593Smuzhiyun 	/* 17-31 Reserved for challenge text extension */
227*4882a593Smuzhiyun 	/* 32-255 Reserved, unused */
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun struct iw_mgmt_info_element {
231*4882a593Smuzhiyun 	u8 id; /* one of enum iw_mgmt_info_element_ids,
232*4882a593Smuzhiyun 		  but sizeof(enum) > sizeof(u8) :-( */
233*4882a593Smuzhiyun 	u8 len;
234*4882a593Smuzhiyun 	u8 data[];
235*4882a593Smuzhiyun } __packed;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun struct iw_mgmt_essid_pset {
238*4882a593Smuzhiyun 	struct iw_mgmt_info_element el;
239*4882a593Smuzhiyun 	u8 			    essid[IW_ESSID_MAX_SIZE];
240*4882a593Smuzhiyun } __packed;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /*
243*4882a593Smuzhiyun  * According to 802.11 Wireless Netowors, the definitive guide - O'Reilly
244*4882a593Smuzhiyun  * Pg 75
245*4882a593Smuzhiyun  */
246*4882a593Smuzhiyun #define IW_DATA_RATE_MAX_LABELS 8
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun struct iw_mgmt_data_rset {
249*4882a593Smuzhiyun 	struct iw_mgmt_info_element el;
250*4882a593Smuzhiyun 	u8 			    data_rate_labels[IW_DATA_RATE_MAX_LABELS];
251*4882a593Smuzhiyun } __packed;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun struct iw_mgmt_ds_pset {
254*4882a593Smuzhiyun 	struct iw_mgmt_info_element el;
255*4882a593Smuzhiyun 	u8 			    chan;
256*4882a593Smuzhiyun } __packed;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun struct iw_mgmt_cf_pset {
259*4882a593Smuzhiyun 	struct iw_mgmt_info_element el;
260*4882a593Smuzhiyun 	u8 			    cfp_count;
261*4882a593Smuzhiyun 	u8 			    cfp_period;
262*4882a593Smuzhiyun 	u16 			    cfp_max_duration;
263*4882a593Smuzhiyun 	u16 			    cfp_dur_remaining;
264*4882a593Smuzhiyun } __packed;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun struct iw_mgmt_ibss_pset {
267*4882a593Smuzhiyun 	struct iw_mgmt_info_element el;
268*4882a593Smuzhiyun 	u16 			    atim_window;
269*4882a593Smuzhiyun } __packed;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun struct wl3501_tx_hdr {
272*4882a593Smuzhiyun 	u16	tx_cnt;
273*4882a593Smuzhiyun 	u8	sync[16];
274*4882a593Smuzhiyun 	u16	sfd;
275*4882a593Smuzhiyun 	u8	signal;
276*4882a593Smuzhiyun 	u8	service;
277*4882a593Smuzhiyun 	u16	len;
278*4882a593Smuzhiyun 	u16	crc16;
279*4882a593Smuzhiyun 	u16	frame_ctrl;
280*4882a593Smuzhiyun 	u16	duration_id;
281*4882a593Smuzhiyun 	u8	addr1[ETH_ALEN];
282*4882a593Smuzhiyun 	u8	addr2[ETH_ALEN];
283*4882a593Smuzhiyun 	u8	addr3[ETH_ALEN];
284*4882a593Smuzhiyun 	u16	seq_ctrl;
285*4882a593Smuzhiyun 	u8	addr4[ETH_ALEN];
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun struct wl3501_rx_hdr {
289*4882a593Smuzhiyun 	u16	rx_next_blk;
290*4882a593Smuzhiyun 	u16	rc_next_frame_blk;
291*4882a593Smuzhiyun 	u8	rx_blk_ctrl;
292*4882a593Smuzhiyun 	u8	rx_next_frame;
293*4882a593Smuzhiyun 	u8	rx_next_frame1;
294*4882a593Smuzhiyun 	u8	rssi;
295*4882a593Smuzhiyun 	char	time[8];
296*4882a593Smuzhiyun 	u8	signal;
297*4882a593Smuzhiyun 	u8	service;
298*4882a593Smuzhiyun 	u16	len;
299*4882a593Smuzhiyun 	u16	crc16;
300*4882a593Smuzhiyun 	u16	frame_ctrl;
301*4882a593Smuzhiyun 	u16	duration;
302*4882a593Smuzhiyun 	u8	addr1[ETH_ALEN];
303*4882a593Smuzhiyun 	u8	addr2[ETH_ALEN];
304*4882a593Smuzhiyun 	u8	addr3[ETH_ALEN];
305*4882a593Smuzhiyun 	u16	seq;
306*4882a593Smuzhiyun 	u8	addr4[ETH_ALEN];
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun struct wl3501_start_req {
310*4882a593Smuzhiyun 	u16			    next_blk;
311*4882a593Smuzhiyun 	u8			    sig_id;
312*4882a593Smuzhiyun 	u8			    bss_type;
313*4882a593Smuzhiyun 	u16			    beacon_period;
314*4882a593Smuzhiyun 	u16			    dtim_period;
315*4882a593Smuzhiyun 	u16			    probe_delay;
316*4882a593Smuzhiyun 	u16			    cap_info;
317*4882a593Smuzhiyun 	struct iw_mgmt_essid_pset   ssid;
318*4882a593Smuzhiyun 	struct iw_mgmt_data_rset    bss_basic_rset;
319*4882a593Smuzhiyun 	struct iw_mgmt_data_rset    operational_rset;
320*4882a593Smuzhiyun 	struct iw_mgmt_cf_pset	    cf_pset;
321*4882a593Smuzhiyun 	struct iw_mgmt_ds_pset	    ds_pset;
322*4882a593Smuzhiyun 	struct iw_mgmt_ibss_pset    ibss_pset;
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun struct wl3501_assoc_req {
326*4882a593Smuzhiyun 	u16	next_blk;
327*4882a593Smuzhiyun 	u8	sig_id;
328*4882a593Smuzhiyun 	u8	reserved;
329*4882a593Smuzhiyun 	u16	timeout;
330*4882a593Smuzhiyun 	u16	cap_info;
331*4882a593Smuzhiyun 	u16	listen_interval;
332*4882a593Smuzhiyun 	u8	mac_addr[ETH_ALEN];
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun struct wl3501_assoc_confirm {
336*4882a593Smuzhiyun 	u16	next_blk;
337*4882a593Smuzhiyun 	u8	sig_id;
338*4882a593Smuzhiyun 	u8	reserved;
339*4882a593Smuzhiyun 	u16	status;
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun struct wl3501_assoc_ind {
343*4882a593Smuzhiyun 	u16	next_blk;
344*4882a593Smuzhiyun 	u8	sig_id;
345*4882a593Smuzhiyun 	u8	mac_addr[ETH_ALEN];
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun struct wl3501_auth_req {
349*4882a593Smuzhiyun 	u16	next_blk;
350*4882a593Smuzhiyun 	u8	sig_id;
351*4882a593Smuzhiyun 	u8	reserved;
352*4882a593Smuzhiyun 	u16	type;
353*4882a593Smuzhiyun 	u16	timeout;
354*4882a593Smuzhiyun 	u8	mac_addr[ETH_ALEN];
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun struct wl3501_auth_confirm {
358*4882a593Smuzhiyun 	u16	next_blk;
359*4882a593Smuzhiyun 	u8	sig_id;
360*4882a593Smuzhiyun 	u8	reserved;
361*4882a593Smuzhiyun 	u16	type;
362*4882a593Smuzhiyun 	u16	status;
363*4882a593Smuzhiyun 	u8	mac_addr[ETH_ALEN];
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun struct wl3501_get_req {
367*4882a593Smuzhiyun 	u16	next_blk;
368*4882a593Smuzhiyun 	u8	sig_id;
369*4882a593Smuzhiyun 	u8	reserved;
370*4882a593Smuzhiyun 	u16	mib_attrib;
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun struct wl3501_get_confirm {
374*4882a593Smuzhiyun 	u16	next_blk;
375*4882a593Smuzhiyun 	u8	sig_id;
376*4882a593Smuzhiyun 	u8	reserved;
377*4882a593Smuzhiyun 	u16	mib_status;
378*4882a593Smuzhiyun 	u16	mib_attrib;
379*4882a593Smuzhiyun 	u8	mib_value[100];
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun struct wl3501_req {
383*4882a593Smuzhiyun 	u16			    beacon_period;
384*4882a593Smuzhiyun 	u16			    dtim_period;
385*4882a593Smuzhiyun 	u16			    cap_info;
386*4882a593Smuzhiyun 	u8			    bss_type;
387*4882a593Smuzhiyun 	u8			    bssid[ETH_ALEN];
388*4882a593Smuzhiyun 	struct iw_mgmt_essid_pset   ssid;
389*4882a593Smuzhiyun 	struct iw_mgmt_ds_pset	    ds_pset;
390*4882a593Smuzhiyun 	struct iw_mgmt_cf_pset	    cf_pset;
391*4882a593Smuzhiyun 	struct iw_mgmt_ibss_pset    ibss_pset;
392*4882a593Smuzhiyun 	struct iw_mgmt_data_rset    bss_basic_rset;
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun struct wl3501_join_req {
396*4882a593Smuzhiyun 	u16			    next_blk;
397*4882a593Smuzhiyun 	u8			    sig_id;
398*4882a593Smuzhiyun 	u8			    reserved;
399*4882a593Smuzhiyun 	struct iw_mgmt_data_rset    operational_rset;
400*4882a593Smuzhiyun 	u16			    reserved2;
401*4882a593Smuzhiyun 	u16			    timeout;
402*4882a593Smuzhiyun 	u16			    probe_delay;
403*4882a593Smuzhiyun 	u8			    timestamp[8];
404*4882a593Smuzhiyun 	u8			    local_time[8];
405*4882a593Smuzhiyun 	struct wl3501_req	    req;
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun struct wl3501_join_confirm {
409*4882a593Smuzhiyun 	u16	next_blk;
410*4882a593Smuzhiyun 	u8	sig_id;
411*4882a593Smuzhiyun 	u8	reserved;
412*4882a593Smuzhiyun 	u16	status;
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun struct wl3501_pwr_mgmt_req {
416*4882a593Smuzhiyun 	u16	next_blk;
417*4882a593Smuzhiyun 	u8	sig_id;
418*4882a593Smuzhiyun 	u8	pwr_save;
419*4882a593Smuzhiyun 	u8	wake_up;
420*4882a593Smuzhiyun 	u8	receive_dtims;
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun struct wl3501_pwr_mgmt_confirm {
424*4882a593Smuzhiyun 	u16	next_blk;
425*4882a593Smuzhiyun 	u8	sig_id;
426*4882a593Smuzhiyun 	u8	reserved;
427*4882a593Smuzhiyun 	u16	status;
428*4882a593Smuzhiyun };
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun struct wl3501_scan_req {
431*4882a593Smuzhiyun 	u16			    next_blk;
432*4882a593Smuzhiyun 	u8			    sig_id;
433*4882a593Smuzhiyun 	u8			    bss_type;
434*4882a593Smuzhiyun 	u16			    probe_delay;
435*4882a593Smuzhiyun 	u16			    min_chan_time;
436*4882a593Smuzhiyun 	u16			    max_chan_time;
437*4882a593Smuzhiyun 	u8			    chan_list[14];
438*4882a593Smuzhiyun 	u8			    bssid[ETH_ALEN];
439*4882a593Smuzhiyun 	struct iw_mgmt_essid_pset   ssid;
440*4882a593Smuzhiyun 	enum wl3501_scan_type	    scan_type;
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun struct wl3501_scan_confirm {
444*4882a593Smuzhiyun 	u16			    next_blk;
445*4882a593Smuzhiyun 	u8			    sig_id;
446*4882a593Smuzhiyun 	u8			    reserved;
447*4882a593Smuzhiyun 	u16			    status;
448*4882a593Smuzhiyun 	char			    timestamp[8];
449*4882a593Smuzhiyun 	char			    localtime[8];
450*4882a593Smuzhiyun 	struct wl3501_req	    req;
451*4882a593Smuzhiyun 	u8			    rssi;
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun struct wl3501_start_confirm {
455*4882a593Smuzhiyun 	u16	next_blk;
456*4882a593Smuzhiyun 	u8	sig_id;
457*4882a593Smuzhiyun 	u8	reserved;
458*4882a593Smuzhiyun 	u16	status;
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun struct wl3501_md_req {
462*4882a593Smuzhiyun 	u16	next_blk;
463*4882a593Smuzhiyun 	u8	sig_id;
464*4882a593Smuzhiyun 	u8	routing;
465*4882a593Smuzhiyun 	u16	data;
466*4882a593Smuzhiyun 	u16	size;
467*4882a593Smuzhiyun 	u8	pri;
468*4882a593Smuzhiyun 	u8	service_class;
469*4882a593Smuzhiyun 	struct {
470*4882a593Smuzhiyun 		u8	daddr[ETH_ALEN];
471*4882a593Smuzhiyun 		u8	saddr[ETH_ALEN];
472*4882a593Smuzhiyun 	} addr;
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun struct wl3501_md_ind {
476*4882a593Smuzhiyun 	u16	next_blk;
477*4882a593Smuzhiyun 	u8	sig_id;
478*4882a593Smuzhiyun 	u8	routing;
479*4882a593Smuzhiyun 	u16	data;
480*4882a593Smuzhiyun 	u16	size;
481*4882a593Smuzhiyun 	u8	reception;
482*4882a593Smuzhiyun 	u8	pri;
483*4882a593Smuzhiyun 	u8	service_class;
484*4882a593Smuzhiyun 	struct {
485*4882a593Smuzhiyun 		u8	daddr[ETH_ALEN];
486*4882a593Smuzhiyun 		u8	saddr[ETH_ALEN];
487*4882a593Smuzhiyun 	} addr;
488*4882a593Smuzhiyun };
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun struct wl3501_md_confirm {
491*4882a593Smuzhiyun 	u16	next_blk;
492*4882a593Smuzhiyun 	u8	sig_id;
493*4882a593Smuzhiyun 	u8	reserved;
494*4882a593Smuzhiyun 	u16	data;
495*4882a593Smuzhiyun 	u8	status;
496*4882a593Smuzhiyun 	u8	pri;
497*4882a593Smuzhiyun 	u8	service_class;
498*4882a593Smuzhiyun };
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun struct wl3501_resync_req {
501*4882a593Smuzhiyun 	u16	next_blk;
502*4882a593Smuzhiyun 	u8	sig_id;
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun /* Definitions for supporting clone adapters. */
506*4882a593Smuzhiyun /* System Interface Registers (SIR space) */
507*4882a593Smuzhiyun #define WL3501_NIC_GCR ((u8)0x00)	/* SIR0 - General Conf Register */
508*4882a593Smuzhiyun #define WL3501_NIC_BSS ((u8)0x01)	/* SIR1 - Bank Switching Select Reg */
509*4882a593Smuzhiyun #define WL3501_NIC_LMAL ((u8)0x02)	/* SIR2 - Local Mem addr Reg [7:0] */
510*4882a593Smuzhiyun #define WL3501_NIC_LMAH ((u8)0x03)	/* SIR3 - Local Mem addr Reg [14:8] */
511*4882a593Smuzhiyun #define WL3501_NIC_IODPA ((u8)0x04)	/* SIR4 - I/O Data Port A */
512*4882a593Smuzhiyun #define WL3501_NIC_IODPB ((u8)0x05)	/* SIR5 - I/O Data Port B */
513*4882a593Smuzhiyun #define WL3501_NIC_IODPC ((u8)0x06)	/* SIR6 - I/O Data Port C */
514*4882a593Smuzhiyun #define WL3501_NIC_IODPD ((u8)0x07)	/* SIR7 - I/O Data Port D */
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun /* Bits in GCR */
517*4882a593Smuzhiyun #define WL3501_GCR_SWRESET ((u8)0x80)
518*4882a593Smuzhiyun #define WL3501_GCR_CORESET ((u8)0x40)
519*4882a593Smuzhiyun #define WL3501_GCR_DISPWDN ((u8)0x20)
520*4882a593Smuzhiyun #define WL3501_GCR_ECWAIT  ((u8)0x10)
521*4882a593Smuzhiyun #define WL3501_GCR_ECINT   ((u8)0x08)
522*4882a593Smuzhiyun #define WL3501_GCR_INT2EC  ((u8)0x04)
523*4882a593Smuzhiyun #define WL3501_GCR_ENECINT ((u8)0x02)
524*4882a593Smuzhiyun #define WL3501_GCR_DAM     ((u8)0x01)
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun /* Bits in BSS (Bank Switching Select Register) */
527*4882a593Smuzhiyun #define WL3501_BSS_FPAGE0 ((u8)0x20)	/* Flash memory page0 */
528*4882a593Smuzhiyun #define WL3501_BSS_FPAGE1 ((u8)0x28)
529*4882a593Smuzhiyun #define WL3501_BSS_FPAGE2 ((u8)0x30)
530*4882a593Smuzhiyun #define WL3501_BSS_FPAGE3 ((u8)0x38)
531*4882a593Smuzhiyun #define WL3501_BSS_SPAGE0 ((u8)0x00)	/* SRAM page0 */
532*4882a593Smuzhiyun #define WL3501_BSS_SPAGE1 ((u8)0x08)
533*4882a593Smuzhiyun #define WL3501_BSS_SPAGE2 ((u8)0x10)
534*4882a593Smuzhiyun #define WL3501_BSS_SPAGE3 ((u8)0x18)
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun /* Define Driver Interface */
537*4882a593Smuzhiyun /* Refer IEEE 802.11 */
538*4882a593Smuzhiyun /* Tx packet header, include PLCP and MPDU */
539*4882a593Smuzhiyun /* Tx PLCP Header */
540*4882a593Smuzhiyun struct wl3501_80211_tx_plcp_hdr {
541*4882a593Smuzhiyun 	u8	sync[16];
542*4882a593Smuzhiyun 	u16	sfd;
543*4882a593Smuzhiyun 	u8	signal;
544*4882a593Smuzhiyun 	u8	service;
545*4882a593Smuzhiyun 	u16	len;
546*4882a593Smuzhiyun 	u16	crc16;
547*4882a593Smuzhiyun } __packed;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun struct wl3501_80211_tx_hdr {
550*4882a593Smuzhiyun 	struct wl3501_80211_tx_plcp_hdr	pclp_hdr;
551*4882a593Smuzhiyun 	struct ieee80211_hdr		mac_hdr;
552*4882a593Smuzhiyun } __packed;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun /*
555*4882a593Smuzhiyun    Reserve the beginning Tx space for descriptor use.
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun    TxBlockOffset -->	*----*----*----*----* \
558*4882a593Smuzhiyun 	(TxFreeDesc)	|  0 |  1 |  2 |  3 |  \
559*4882a593Smuzhiyun 			|  4 |  5 |  6 |  7 |   |
560*4882a593Smuzhiyun 			|  8 |  9 | 10 | 11 |   TX_DESC * 20
561*4882a593Smuzhiyun 			| 12 | 13 | 14 | 15 |   |
562*4882a593Smuzhiyun 			| 16 | 17 | 18 | 19 |  /
563*4882a593Smuzhiyun    TxBufferBegin -->	*----*----*----*----* /
564*4882a593Smuzhiyun    (TxBufferHead)	| 		    |
565*4882a593Smuzhiyun    (TxBufferTail)	| 		    |
566*4882a593Smuzhiyun 			|    Send Buffer    |
567*4882a593Smuzhiyun 			| 		    |
568*4882a593Smuzhiyun 			|		    |
569*4882a593Smuzhiyun 			*-------------------*
570*4882a593Smuzhiyun    TxBufferEnd    -------------------------/
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun */
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun struct wl3501_card {
575*4882a593Smuzhiyun 	int				base_addr;
576*4882a593Smuzhiyun 	u8				mac_addr[ETH_ALEN];
577*4882a593Smuzhiyun 	spinlock_t			lock;
578*4882a593Smuzhiyun 	wait_queue_head_t		wait;
579*4882a593Smuzhiyun 	struct wl3501_get_confirm	sig_get_confirm;
580*4882a593Smuzhiyun 	struct wl3501_pwr_mgmt_confirm	sig_pwr_mgmt_confirm;
581*4882a593Smuzhiyun 	u16				tx_buffer_size;
582*4882a593Smuzhiyun 	u16				tx_buffer_head;
583*4882a593Smuzhiyun 	u16				tx_buffer_tail;
584*4882a593Smuzhiyun 	u16				tx_buffer_cnt;
585*4882a593Smuzhiyun 	u16				esbq_req_start;
586*4882a593Smuzhiyun 	u16				esbq_req_end;
587*4882a593Smuzhiyun 	u16				esbq_req_head;
588*4882a593Smuzhiyun 	u16				esbq_req_tail;
589*4882a593Smuzhiyun 	u16				esbq_confirm_start;
590*4882a593Smuzhiyun 	u16				esbq_confirm_end;
591*4882a593Smuzhiyun 	u16				esbq_confirm;
592*4882a593Smuzhiyun 	struct iw_mgmt_essid_pset  	essid;
593*4882a593Smuzhiyun 	struct iw_mgmt_essid_pset  	keep_essid;
594*4882a593Smuzhiyun 	u8				bssid[ETH_ALEN];
595*4882a593Smuzhiyun 	int				net_type;
596*4882a593Smuzhiyun 	char				nick[32];
597*4882a593Smuzhiyun 	char				card_name[32];
598*4882a593Smuzhiyun 	char				firmware_date[32];
599*4882a593Smuzhiyun 	u8				chan;
600*4882a593Smuzhiyun 	u8				cap_info;
601*4882a593Smuzhiyun 	u16				start_seg;
602*4882a593Smuzhiyun 	u16				bss_cnt;
603*4882a593Smuzhiyun 	u16				join_sta_bss;
604*4882a593Smuzhiyun 	u8				rssi;
605*4882a593Smuzhiyun 	u8				adhoc_times;
606*4882a593Smuzhiyun 	u8				reg_domain;
607*4882a593Smuzhiyun 	u8				version[2];
608*4882a593Smuzhiyun 	struct wl3501_scan_confirm	bss_set[20];
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	struct iw_statistics		wstats;
611*4882a593Smuzhiyun 	struct iw_spy_data		spy_data;
612*4882a593Smuzhiyun 	struct iw_public_data		wireless_data;
613*4882a593Smuzhiyun 	struct pcmcia_device		*p_dev;
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun #endif
616