1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of wl18xx 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __WL18XX_CONF_H__ 9*4882a593Smuzhiyun #define __WL18XX_CONF_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WL18XX_CONF_MAGIC 0x10e100ca 12*4882a593Smuzhiyun #define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0007) 13*4882a593Smuzhiyun #define WL18XX_CONF_MASK 0x0000ffff 14*4882a593Smuzhiyun #define WL18XX_CONF_SIZE (WLCORE_CONF_SIZE + \ 15*4882a593Smuzhiyun sizeof(struct wl18xx_priv_conf)) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define NUM_OF_CHANNELS_11_ABG 150 18*4882a593Smuzhiyun #define NUM_OF_CHANNELS_11_P 7 19*4882a593Smuzhiyun #define SRF_TABLE_LEN 16 20*4882a593Smuzhiyun #define PIN_MUXING_SIZE 2 21*4882a593Smuzhiyun #define WL18XX_TRACE_LOSS_GAPS_TX 10 22*4882a593Smuzhiyun #define WL18XX_TRACE_LOSS_GAPS_RX 18 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct wl18xx_mac_and_phy_params { 25*4882a593Smuzhiyun u8 phy_standalone; 26*4882a593Smuzhiyun u8 spare0; 27*4882a593Smuzhiyun u8 enable_clpc; 28*4882a593Smuzhiyun u8 enable_tx_low_pwr_on_siso_rdl; 29*4882a593Smuzhiyun u8 auto_detect; 30*4882a593Smuzhiyun u8 dedicated_fem; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u8 low_band_component; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ 35*4882a593Smuzhiyun u8 low_band_component_type; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u8 high_band_component; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ 40*4882a593Smuzhiyun u8 high_band_component_type; 41*4882a593Smuzhiyun u8 number_of_assembled_ant2_4; 42*4882a593Smuzhiyun u8 number_of_assembled_ant5; 43*4882a593Smuzhiyun u8 pin_muxing_platform_options[PIN_MUXING_SIZE]; 44*4882a593Smuzhiyun u8 external_pa_dc2dc; 45*4882a593Smuzhiyun u8 tcxo_ldo_voltage; 46*4882a593Smuzhiyun u8 xtal_itrim_val; 47*4882a593Smuzhiyun u8 srf_state; 48*4882a593Smuzhiyun u8 srf1[SRF_TABLE_LEN]; 49*4882a593Smuzhiyun u8 srf2[SRF_TABLE_LEN]; 50*4882a593Smuzhiyun u8 srf3[SRF_TABLE_LEN]; 51*4882a593Smuzhiyun u8 io_configuration; 52*4882a593Smuzhiyun u8 sdio_configuration; 53*4882a593Smuzhiyun u8 settings; 54*4882a593Smuzhiyun u8 rx_profile; 55*4882a593Smuzhiyun u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG]; 56*4882a593Smuzhiyun u8 pwr_limit_reference_11_abg; 57*4882a593Smuzhiyun u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P]; 58*4882a593Smuzhiyun u8 pwr_limit_reference_11p; 59*4882a593Smuzhiyun u8 spare1; 60*4882a593Smuzhiyun u8 per_chan_bo_mode_11_abg[13]; 61*4882a593Smuzhiyun u8 per_chan_bo_mode_11_p[4]; 62*4882a593Smuzhiyun u8 primary_clock_setting_time; 63*4882a593Smuzhiyun u8 clock_valid_on_wake_up; 64*4882a593Smuzhiyun u8 secondary_clock_setting_time; 65*4882a593Smuzhiyun u8 board_type; 66*4882a593Smuzhiyun /* enable point saturation */ 67*4882a593Smuzhiyun u8 psat; 68*4882a593Smuzhiyun /* low/medium/high Tx power in dBm for STA-HP BG */ 69*4882a593Smuzhiyun s8 low_power_val; 70*4882a593Smuzhiyun s8 med_power_val; 71*4882a593Smuzhiyun s8 high_power_val; 72*4882a593Smuzhiyun s8 per_sub_band_tx_trace_loss[WL18XX_TRACE_LOSS_GAPS_TX]; 73*4882a593Smuzhiyun s8 per_sub_band_rx_trace_loss[WL18XX_TRACE_LOSS_GAPS_RX]; 74*4882a593Smuzhiyun u8 tx_rf_margin; 75*4882a593Smuzhiyun /* low/medium/high Tx power in dBm for other role */ 76*4882a593Smuzhiyun s8 low_power_val_2nd; 77*4882a593Smuzhiyun s8 med_power_val_2nd; 78*4882a593Smuzhiyun s8 high_power_val_2nd; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun u8 padding[1]; 81*4882a593Smuzhiyun } __packed; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum wl18xx_ht_mode { 84*4882a593Smuzhiyun /* Default - use MIMO, fallback to SISO20 */ 85*4882a593Smuzhiyun HT_MODE_DEFAULT = 0, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Wide - use SISO40 */ 88*4882a593Smuzhiyun HT_MODE_WIDE = 1, 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Use SISO20 */ 91*4882a593Smuzhiyun HT_MODE_SISO20 = 2, 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct wl18xx_ht_settings { 95*4882a593Smuzhiyun /* DEFAULT / WIDE / SISO20 */ 96*4882a593Smuzhiyun u8 mode; 97*4882a593Smuzhiyun } __packed; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct conf_ap_sleep_settings { 100*4882a593Smuzhiyun /* Duty Cycle (20-80% of staying Awake) for IDLE AP 101*4882a593Smuzhiyun * (0: disable) 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun u8 idle_duty_cycle; 104*4882a593Smuzhiyun /* Duty Cycle (20-80% of staying Awake) for Connected AP 105*4882a593Smuzhiyun * (0: disable) 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun u8 connected_duty_cycle; 108*4882a593Smuzhiyun /* Maximum stations that are allowed to be connected to AP 109*4882a593Smuzhiyun * (255: no limit) 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun u8 max_stations_thresh; 112*4882a593Smuzhiyun /* Timeout till enabling the Sleep Mechanism after data stops 113*4882a593Smuzhiyun * [unit: 100 msec] 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun u8 idle_conn_thresh; 116*4882a593Smuzhiyun } __packed; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct wl18xx_priv_conf { 119*4882a593Smuzhiyun /* Module params structures */ 120*4882a593Smuzhiyun struct wl18xx_ht_settings ht; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* this structure is copied wholesale to FW */ 123*4882a593Smuzhiyun struct wl18xx_mac_and_phy_params phy; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun struct conf_ap_sleep_settings ap_sleep; 126*4882a593Smuzhiyun } __packed; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun enum wl18xx_sg_params { 129*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_0 = 0, 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Configuration Parameters */ 132*4882a593Smuzhiyun WL18XX_CONF_SG_ANTENNA_CONFIGURATION, 133*4882a593Smuzhiyun WL18XX_CONF_SG_ZIGBEE_COEX, 134*4882a593Smuzhiyun WL18XX_CONF_SG_TIME_SYNC, 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_4, 137*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_5, 138*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_6, 139*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_7, 140*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_8, 141*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_9, 142*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_10, 143*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_11, 144*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_12, 145*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_13, 146*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_14, 147*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_15, 148*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_16, 149*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_17, 150*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_18, 151*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_19, 152*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_20, 153*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_21, 154*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_22, 155*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_23, 156*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_24, 157*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_25, 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* Active Scan Parameters */ 160*4882a593Smuzhiyun WL18XX_CONF_SG_AUTO_SCAN_PROBE_REQ, 161*4882a593Smuzhiyun WL18XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3, 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_28, 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* Passive Scan Parameters */ 166*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_29, 167*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_30, 168*4882a593Smuzhiyun WL18XX_CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3, 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Passive Scan in Dual Antenna Parameters */ 171*4882a593Smuzhiyun WL18XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN, 172*4882a593Smuzhiyun WL18XX_CONF_SG_BEACON_HV3_COLL_TH_IN_PASSIVE_SCAN, 173*4882a593Smuzhiyun WL18XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN, 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* General Parameters */ 176*4882a593Smuzhiyun WL18XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO, 177*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_36, 178*4882a593Smuzhiyun WL18XX_CONF_SG_BEACON_MISS_PERCENT, 179*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_38, 180*4882a593Smuzhiyun WL18XX_CONF_SG_RXT, 181*4882a593Smuzhiyun WL18XX_CONF_SG_UNUSED, 182*4882a593Smuzhiyun WL18XX_CONF_SG_ADAPTIVE_RXT_TXT, 183*4882a593Smuzhiyun WL18XX_CONF_SG_GENERAL_USAGE_BIT_MAP, 184*4882a593Smuzhiyun WL18XX_CONF_SG_HV3_MAX_SERVED, 185*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_44, 186*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_45, 187*4882a593Smuzhiyun WL18XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD, 188*4882a593Smuzhiyun WL18XX_CONF_SG_GEMINI_PARAM_47, 189*4882a593Smuzhiyun WL18XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME, 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* AP Parameters */ 192*4882a593Smuzhiyun WL18XX_CONF_SG_AP_BEACON_MISS_TX, 193*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_50, 194*4882a593Smuzhiyun WL18XX_CONF_SG_AP_BEACON_WINDOW_INTERVAL, 195*4882a593Smuzhiyun WL18XX_CONF_SG_AP_CONNECTION_PROTECTION_TIME, 196*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_53, 197*4882a593Smuzhiyun WL18XX_CONF_SG_PARAM_54, 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* CTS Diluting Parameters */ 200*4882a593Smuzhiyun WL18XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH, 201*4882a593Smuzhiyun WL18XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER, 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_1, 204*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_2, 205*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_3, 206*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_4, 207*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_5, 208*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_6, 209*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_7, 210*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_8, 211*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_9, 212*4882a593Smuzhiyun WL18XX_CONF_SG_TEMP_PARAM_10, 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun WL18XX_CONF_SG_PARAMS_MAX, 215*4882a593Smuzhiyun WL18XX_CONF_SG_PARAMS_ALL = 0xff 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #endif /* __WL18XX_CONF_H__ */ 219