1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of wl18xx 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __WL18XX_ACX_H__ 9*4882a593Smuzhiyun #define __WL18XX_ACX_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "../wlcore/wlcore.h" 12*4882a593Smuzhiyun #include "../wlcore/acx.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun enum { 15*4882a593Smuzhiyun ACX_NS_IPV6_FILTER = 0x0050, 16*4882a593Smuzhiyun ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051, 17*4882a593Smuzhiyun ACX_CSUM_CONFIG = 0x0052, 18*4882a593Smuzhiyun ACX_SIM_CONFIG = 0x0053, 19*4882a593Smuzhiyun ACX_CLEAR_STATISTICS = 0x0054, 20*4882a593Smuzhiyun ACX_AUTO_RX_STREAMING = 0x0055, 21*4882a593Smuzhiyun ACX_PEER_CAP = 0x0056, 22*4882a593Smuzhiyun ACX_INTERRUPT_NOTIFY = 0x0057, 23*4882a593Smuzhiyun ACX_RX_BA_FILTER = 0x0058, 24*4882a593Smuzhiyun ACX_AP_SLEEP_CFG = 0x0059, 25*4882a593Smuzhiyun ACX_DYNAMIC_TRACES_CFG = 0x005A, 26*4882a593Smuzhiyun ACX_TIME_SYNC_CFG = 0x005B, 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* numbers of bits the length field takes (add 1 for the actual number) */ 30*4882a593Smuzhiyun #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ 33*4882a593Smuzhiyun WL1271_ACX_INTR_INIT_COMPLETE | \ 34*4882a593Smuzhiyun WL1271_ACX_INTR_EVENT_A | \ 35*4882a593Smuzhiyun WL1271_ACX_INTR_EVENT_B | \ 36*4882a593Smuzhiyun WL1271_ACX_INTR_CMD_COMPLETE | \ 37*4882a593Smuzhiyun WL1271_ACX_INTR_HW_AVAILABLE | \ 38*4882a593Smuzhiyun WL1271_ACX_INTR_DATA | \ 39*4882a593Smuzhiyun WL1271_ACX_SW_INTR_WATCHDOG) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ 42*4882a593Smuzhiyun WL1271_ACX_INTR_EVENT_A | \ 43*4882a593Smuzhiyun WL1271_ACX_INTR_EVENT_B | \ 44*4882a593Smuzhiyun WL1271_ACX_INTR_HW_AVAILABLE | \ 45*4882a593Smuzhiyun WL1271_ACX_INTR_DATA | \ 46*4882a593Smuzhiyun WL1271_ACX_SW_INTR_WATCHDOG) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct wl18xx_acx_host_config_bitmap { 49*4882a593Smuzhiyun struct acx_header header; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun __le32 host_cfg_bitmap; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun __le32 host_sdio_block_size; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* extra mem blocks per frame in TX. */ 56*4882a593Smuzhiyun __le32 extra_mem_blocks; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * number of bits of the length field in the first TX word 60*4882a593Smuzhiyun * (up to 15 - for using the entire 16 bits). 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun __le32 length_field_size; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun } __packed; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum { 67*4882a593Smuzhiyun CHECKSUM_OFFLOAD_DISABLED = 0, 68*4882a593Smuzhiyun CHECKSUM_OFFLOAD_ENABLED = 1, 69*4882a593Smuzhiyun CHECKSUM_OFFLOAD_FAKE_RX = 2, 70*4882a593Smuzhiyun CHECKSUM_OFFLOAD_INVALID = 0xFF 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct wl18xx_acx_checksum_state { 74*4882a593Smuzhiyun struct acx_header header; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* enum acx_checksum_state */ 77*4882a593Smuzhiyun u8 checksum_state; 78*4882a593Smuzhiyun u8 pad[3]; 79*4882a593Smuzhiyun } __packed; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct wl18xx_acx_error_stats { 83*4882a593Smuzhiyun u32 error_frame_non_ctrl; 84*4882a593Smuzhiyun u32 error_frame_ctrl; 85*4882a593Smuzhiyun u32 error_frame_during_protection; 86*4882a593Smuzhiyun u32 null_frame_tx_start; 87*4882a593Smuzhiyun u32 null_frame_cts_start; 88*4882a593Smuzhiyun u32 bar_retry; 89*4882a593Smuzhiyun u32 num_frame_cts_nul_flid; 90*4882a593Smuzhiyun u32 tx_abort_failure; 91*4882a593Smuzhiyun u32 tx_resume_failure; 92*4882a593Smuzhiyun u32 rx_cmplt_db_overflow_cnt; 93*4882a593Smuzhiyun u32 elp_while_rx_exch; 94*4882a593Smuzhiyun u32 elp_while_tx_exch; 95*4882a593Smuzhiyun u32 elp_while_tx; 96*4882a593Smuzhiyun u32 elp_while_nvic_pending; 97*4882a593Smuzhiyun u32 rx_excessive_frame_len; 98*4882a593Smuzhiyun u32 burst_mismatch; 99*4882a593Smuzhiyun u32 tbc_exch_mismatch; 100*4882a593Smuzhiyun } __packed; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define NUM_OF_RATES_INDEXES 30 103*4882a593Smuzhiyun struct wl18xx_acx_tx_stats { 104*4882a593Smuzhiyun u32 tx_prepared_descs; 105*4882a593Smuzhiyun u32 tx_cmplt; 106*4882a593Smuzhiyun u32 tx_template_prepared; 107*4882a593Smuzhiyun u32 tx_data_prepared; 108*4882a593Smuzhiyun u32 tx_template_programmed; 109*4882a593Smuzhiyun u32 tx_data_programmed; 110*4882a593Smuzhiyun u32 tx_burst_programmed; 111*4882a593Smuzhiyun u32 tx_starts; 112*4882a593Smuzhiyun u32 tx_stop; 113*4882a593Smuzhiyun u32 tx_start_templates; 114*4882a593Smuzhiyun u32 tx_start_int_templates; 115*4882a593Smuzhiyun u32 tx_start_fw_gen; 116*4882a593Smuzhiyun u32 tx_start_data; 117*4882a593Smuzhiyun u32 tx_start_null_frame; 118*4882a593Smuzhiyun u32 tx_exch; 119*4882a593Smuzhiyun u32 tx_retry_template; 120*4882a593Smuzhiyun u32 tx_retry_data; 121*4882a593Smuzhiyun u32 tx_retry_per_rate[NUM_OF_RATES_INDEXES]; 122*4882a593Smuzhiyun u32 tx_exch_pending; 123*4882a593Smuzhiyun u32 tx_exch_expiry; 124*4882a593Smuzhiyun u32 tx_done_template; 125*4882a593Smuzhiyun u32 tx_done_data; 126*4882a593Smuzhiyun u32 tx_done_int_template; 127*4882a593Smuzhiyun u32 tx_cfe1; 128*4882a593Smuzhiyun u32 tx_cfe2; 129*4882a593Smuzhiyun u32 frag_called; 130*4882a593Smuzhiyun u32 frag_mpdu_alloc_failed; 131*4882a593Smuzhiyun u32 frag_init_called; 132*4882a593Smuzhiyun u32 frag_in_process_called; 133*4882a593Smuzhiyun u32 frag_tkip_called; 134*4882a593Smuzhiyun u32 frag_key_not_found; 135*4882a593Smuzhiyun u32 frag_need_fragmentation; 136*4882a593Smuzhiyun u32 frag_bad_mblk_num; 137*4882a593Smuzhiyun u32 frag_failed; 138*4882a593Smuzhiyun u32 frag_cache_hit; 139*4882a593Smuzhiyun u32 frag_cache_miss; 140*4882a593Smuzhiyun } __packed; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun struct wl18xx_acx_rx_stats { 143*4882a593Smuzhiyun u32 rx_beacon_early_term; 144*4882a593Smuzhiyun u32 rx_out_of_mpdu_nodes; 145*4882a593Smuzhiyun u32 rx_hdr_overflow; 146*4882a593Smuzhiyun u32 rx_dropped_frame; 147*4882a593Smuzhiyun u32 rx_done_stage; 148*4882a593Smuzhiyun u32 rx_done; 149*4882a593Smuzhiyun u32 rx_defrag; 150*4882a593Smuzhiyun u32 rx_defrag_end; 151*4882a593Smuzhiyun u32 rx_cmplt; 152*4882a593Smuzhiyun u32 rx_pre_complt; 153*4882a593Smuzhiyun u32 rx_cmplt_task; 154*4882a593Smuzhiyun u32 rx_phy_hdr; 155*4882a593Smuzhiyun u32 rx_timeout; 156*4882a593Smuzhiyun u32 rx_rts_timeout; 157*4882a593Smuzhiyun u32 rx_timeout_wa; 158*4882a593Smuzhiyun u32 defrag_called; 159*4882a593Smuzhiyun u32 defrag_init_called; 160*4882a593Smuzhiyun u32 defrag_in_process_called; 161*4882a593Smuzhiyun u32 defrag_tkip_called; 162*4882a593Smuzhiyun u32 defrag_need_defrag; 163*4882a593Smuzhiyun u32 defrag_decrypt_failed; 164*4882a593Smuzhiyun u32 decrypt_key_not_found; 165*4882a593Smuzhiyun u32 defrag_need_decrypt; 166*4882a593Smuzhiyun u32 rx_tkip_replays; 167*4882a593Smuzhiyun u32 rx_xfr; 168*4882a593Smuzhiyun } __packed; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun struct wl18xx_acx_isr_stats { 171*4882a593Smuzhiyun u32 irqs; 172*4882a593Smuzhiyun } __packed; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun struct wl18xx_acx_pwr_stats { 177*4882a593Smuzhiyun u32 missing_bcns_cnt; 178*4882a593Smuzhiyun u32 rcvd_bcns_cnt; 179*4882a593Smuzhiyun u32 connection_out_of_sync; 180*4882a593Smuzhiyun u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD]; 181*4882a593Smuzhiyun u32 rcvd_awake_bcns_cnt; 182*4882a593Smuzhiyun u32 sleep_time_count; 183*4882a593Smuzhiyun u32 sleep_time_avg; 184*4882a593Smuzhiyun u32 sleep_cycle_avg; 185*4882a593Smuzhiyun u32 sleep_percent; 186*4882a593Smuzhiyun u32 ap_sleep_active_conf; 187*4882a593Smuzhiyun u32 ap_sleep_user_conf; 188*4882a593Smuzhiyun u32 ap_sleep_counter; 189*4882a593Smuzhiyun } __packed; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun struct wl18xx_acx_rx_filter_stats { 192*4882a593Smuzhiyun u32 beacon_filter; 193*4882a593Smuzhiyun u32 arp_filter; 194*4882a593Smuzhiyun u32 mc_filter; 195*4882a593Smuzhiyun u32 dup_filter; 196*4882a593Smuzhiyun u32 data_filter; 197*4882a593Smuzhiyun u32 ibss_filter; 198*4882a593Smuzhiyun u32 protection_filter; 199*4882a593Smuzhiyun u32 accum_arp_pend_requests; 200*4882a593Smuzhiyun u32 max_arp_queue_dep; 201*4882a593Smuzhiyun } __packed; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun struct wl18xx_acx_rx_rate_stats { 204*4882a593Smuzhiyun u32 rx_frames_per_rates[50]; 205*4882a593Smuzhiyun } __packed; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define AGGR_STATS_TX_AGG 16 208*4882a593Smuzhiyun #define AGGR_STATS_RX_SIZE_LEN 16 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun struct wl18xx_acx_aggr_stats { 211*4882a593Smuzhiyun u32 tx_agg_rate[AGGR_STATS_TX_AGG]; 212*4882a593Smuzhiyun u32 tx_agg_len[AGGR_STATS_TX_AGG]; 213*4882a593Smuzhiyun u32 rx_size[AGGR_STATS_RX_SIZE_LEN]; 214*4882a593Smuzhiyun } __packed; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define PIPE_STATS_HW_FIFO 11 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun struct wl18xx_acx_pipeline_stats { 219*4882a593Smuzhiyun u32 hs_tx_stat_fifo_int; 220*4882a593Smuzhiyun u32 hs_rx_stat_fifo_int; 221*4882a593Smuzhiyun u32 enc_tx_stat_fifo_int; 222*4882a593Smuzhiyun u32 enc_rx_stat_fifo_int; 223*4882a593Smuzhiyun u32 rx_complete_stat_fifo_int; 224*4882a593Smuzhiyun u32 pre_proc_swi; 225*4882a593Smuzhiyun u32 post_proc_swi; 226*4882a593Smuzhiyun u32 sec_frag_swi; 227*4882a593Smuzhiyun u32 pre_to_defrag_swi; 228*4882a593Smuzhiyun u32 defrag_to_rx_xfer_swi; 229*4882a593Smuzhiyun u32 dec_packet_in; 230*4882a593Smuzhiyun u32 dec_packet_in_fifo_full; 231*4882a593Smuzhiyun u32 dec_packet_out; 232*4882a593Smuzhiyun u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO]; 233*4882a593Smuzhiyun u16 padding; 234*4882a593Smuzhiyun } __packed; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define DIVERSITY_STATS_NUM_OF_ANT 2 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun struct wl18xx_acx_diversity_stats { 239*4882a593Smuzhiyun u32 num_of_packets_per_ant[DIVERSITY_STATS_NUM_OF_ANT]; 240*4882a593Smuzhiyun u32 total_num_of_toggles; 241*4882a593Smuzhiyun } __packed; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun struct wl18xx_acx_thermal_stats { 244*4882a593Smuzhiyun u16 irq_thr_low; 245*4882a593Smuzhiyun u16 irq_thr_high; 246*4882a593Smuzhiyun u16 tx_stop; 247*4882a593Smuzhiyun u16 tx_resume; 248*4882a593Smuzhiyun u16 false_irq; 249*4882a593Smuzhiyun u16 adc_source_unexpected; 250*4882a593Smuzhiyun } __packed; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define WL18XX_NUM_OF_CALIBRATIONS_ERRORS 18 253*4882a593Smuzhiyun struct wl18xx_acx_calib_failure_stats { 254*4882a593Smuzhiyun u16 fail_count[WL18XX_NUM_OF_CALIBRATIONS_ERRORS]; 255*4882a593Smuzhiyun u32 calib_count; 256*4882a593Smuzhiyun } __packed; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun struct wl18xx_roaming_stats { 259*4882a593Smuzhiyun s32 rssi_level; 260*4882a593Smuzhiyun } __packed; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun struct wl18xx_dfs_stats { 263*4882a593Smuzhiyun u32 num_of_radar_detections; 264*4882a593Smuzhiyun } __packed; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun struct wl18xx_acx_statistics { 267*4882a593Smuzhiyun struct acx_header header; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun struct wl18xx_acx_error_stats error; 270*4882a593Smuzhiyun struct wl18xx_acx_tx_stats tx; 271*4882a593Smuzhiyun struct wl18xx_acx_rx_stats rx; 272*4882a593Smuzhiyun struct wl18xx_acx_isr_stats isr; 273*4882a593Smuzhiyun struct wl18xx_acx_pwr_stats pwr; 274*4882a593Smuzhiyun struct wl18xx_acx_rx_filter_stats rx_filter; 275*4882a593Smuzhiyun struct wl18xx_acx_rx_rate_stats rx_rate; 276*4882a593Smuzhiyun struct wl18xx_acx_aggr_stats aggr_size; 277*4882a593Smuzhiyun struct wl18xx_acx_pipeline_stats pipeline; 278*4882a593Smuzhiyun struct wl18xx_acx_diversity_stats diversity; 279*4882a593Smuzhiyun struct wl18xx_acx_thermal_stats thermal; 280*4882a593Smuzhiyun struct wl18xx_acx_calib_failure_stats calib; 281*4882a593Smuzhiyun struct wl18xx_roaming_stats roaming; 282*4882a593Smuzhiyun struct wl18xx_dfs_stats dfs; 283*4882a593Smuzhiyun } __packed; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun struct wl18xx_acx_clear_statistics { 286*4882a593Smuzhiyun struct acx_header header; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun enum wlcore_bandwidth { 290*4882a593Smuzhiyun WLCORE_BANDWIDTH_20MHZ, 291*4882a593Smuzhiyun WLCORE_BANDWIDTH_40MHZ, 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun struct wlcore_peer_ht_operation_mode { 295*4882a593Smuzhiyun struct acx_header header; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun u8 hlid; 298*4882a593Smuzhiyun u8 bandwidth; /* enum wlcore_bandwidth */ 299*4882a593Smuzhiyun u8 padding[2]; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun /* 303*4882a593Smuzhiyun * ACX_PEER_CAP 304*4882a593Smuzhiyun * this struct is very similar to wl1271_acx_ht_capabilities, with the 305*4882a593Smuzhiyun * addition of supported rates 306*4882a593Smuzhiyun */ 307*4882a593Smuzhiyun struct wlcore_acx_peer_cap { 308*4882a593Smuzhiyun struct acx_header header; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* bitmask of capability bits supported by the peer */ 311*4882a593Smuzhiyun __le32 ht_capabilites; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* rates supported by the remote peer */ 314*4882a593Smuzhiyun __le32 supported_rates; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* Indicates to which link these capabilities apply. */ 317*4882a593Smuzhiyun u8 hlid; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* 320*4882a593Smuzhiyun * This the maximum A-MPDU length supported by the AP. The FW may not 321*4882a593Smuzhiyun * exceed this length when sending A-MPDUs 322*4882a593Smuzhiyun */ 323*4882a593Smuzhiyun u8 ampdu_max_length; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun /* This is the minimal spacing required when sending A-MPDUs to the AP*/ 326*4882a593Smuzhiyun u8 ampdu_min_spacing; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun u8 padding; 329*4882a593Smuzhiyun } __packed; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* 332*4882a593Smuzhiyun * ACX_INTERRUPT_NOTIFY 333*4882a593Smuzhiyun * enable/disable fast-link/PSM notification from FW 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun struct wl18xx_acx_interrupt_notify { 336*4882a593Smuzhiyun struct acx_header header; 337*4882a593Smuzhiyun u32 enable; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* 341*4882a593Smuzhiyun * ACX_RX_BA_FILTER 342*4882a593Smuzhiyun * enable/disable RX BA filtering in FW 343*4882a593Smuzhiyun */ 344*4882a593Smuzhiyun struct wl18xx_acx_rx_ba_filter { 345*4882a593Smuzhiyun struct acx_header header; 346*4882a593Smuzhiyun u32 enable; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun struct acx_ap_sleep_cfg { 350*4882a593Smuzhiyun struct acx_header header; 351*4882a593Smuzhiyun /* Duty Cycle (20-80% of staying Awake) for IDLE AP 352*4882a593Smuzhiyun * (0: disable) 353*4882a593Smuzhiyun */ 354*4882a593Smuzhiyun u8 idle_duty_cycle; 355*4882a593Smuzhiyun /* Duty Cycle (20-80% of staying Awake) for Connected AP 356*4882a593Smuzhiyun * (0: disable) 357*4882a593Smuzhiyun */ 358*4882a593Smuzhiyun u8 connected_duty_cycle; 359*4882a593Smuzhiyun /* Maximum stations that are allowed to be connected to AP 360*4882a593Smuzhiyun * (255: no limit) 361*4882a593Smuzhiyun */ 362*4882a593Smuzhiyun u8 max_stations_thresh; 363*4882a593Smuzhiyun /* Timeout till enabling the Sleep Mechanism after data stops 364*4882a593Smuzhiyun * [unit: 100 msec] 365*4882a593Smuzhiyun */ 366*4882a593Smuzhiyun u8 idle_conn_thresh; 367*4882a593Smuzhiyun } __packed; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* 370*4882a593Smuzhiyun * ACX_DYNAMIC_TRACES_CFG 371*4882a593Smuzhiyun * configure the FW dynamic traces 372*4882a593Smuzhiyun */ 373*4882a593Smuzhiyun struct acx_dynamic_fw_traces_cfg { 374*4882a593Smuzhiyun struct acx_header header; 375*4882a593Smuzhiyun __le32 dynamic_fw_traces; 376*4882a593Smuzhiyun } __packed; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun /* 379*4882a593Smuzhiyun * ACX_TIME_SYNC_CFG 380*4882a593Smuzhiyun * configure the time sync parameters 381*4882a593Smuzhiyun */ 382*4882a593Smuzhiyun struct acx_time_sync_cfg { 383*4882a593Smuzhiyun struct acx_header header; 384*4882a593Smuzhiyun u8 sync_mode; 385*4882a593Smuzhiyun u8 zone_mac_addr[ETH_ALEN]; 386*4882a593Smuzhiyun u8 padding[1]; 387*4882a593Smuzhiyun } __packed; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap, 390*4882a593Smuzhiyun u32 sdio_blk_size, u32 extra_mem_blks, 391*4882a593Smuzhiyun u32 len_field_size); 392*4882a593Smuzhiyun int wl18xx_acx_set_checksum_state(struct wl1271 *wl); 393*4882a593Smuzhiyun int wl18xx_acx_clear_statistics(struct wl1271 *wl); 394*4882a593Smuzhiyun int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide); 395*4882a593Smuzhiyun int wl18xx_acx_set_peer_cap(struct wl1271 *wl, 396*4882a593Smuzhiyun struct ieee80211_sta_ht_cap *ht_cap, 397*4882a593Smuzhiyun bool allow_ht_operation, 398*4882a593Smuzhiyun u32 rate_set, u8 hlid); 399*4882a593Smuzhiyun int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action); 400*4882a593Smuzhiyun int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action); 401*4882a593Smuzhiyun int wl18xx_acx_ap_sleep(struct wl1271 *wl); 402*4882a593Smuzhiyun int wl18xx_acx_dynamic_fw_traces(struct wl1271 *wl); 403*4882a593Smuzhiyun int wl18xx_acx_time_sync_cfg(struct wl1271 *wl); 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #endif /* __WL18XX_ACX_H__ */ 406