1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of wl12xx 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __WL12XX_PRIV_H__ 9*4882a593Smuzhiyun #define __WL12XX_PRIV_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "conf.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* WiLink 6/7 chip IDs */ 14*4882a593Smuzhiyun #define CHIP_ID_127X_PG10 (0x04030101) 15*4882a593Smuzhiyun #define CHIP_ID_127X_PG20 (0x04030111) 16*4882a593Smuzhiyun #define CHIP_ID_128X_PG10 (0x05030101) 17*4882a593Smuzhiyun #define CHIP_ID_128X_PG20 (0x05030111) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* FW chip version for wl127x */ 20*4882a593Smuzhiyun #define WL127X_CHIP_VER 6 21*4882a593Smuzhiyun /* minimum single-role FW version for wl127x */ 22*4882a593Smuzhiyun #define WL127X_IFTYPE_SR_VER 3 23*4882a593Smuzhiyun #define WL127X_MAJOR_SR_VER 10 24*4882a593Smuzhiyun #define WL127X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE 25*4882a593Smuzhiyun #define WL127X_MINOR_SR_VER 133 26*4882a593Smuzhiyun /* minimum multi-role FW version for wl127x */ 27*4882a593Smuzhiyun #define WL127X_IFTYPE_MR_VER 5 28*4882a593Smuzhiyun #define WL127X_MAJOR_MR_VER 7 29*4882a593Smuzhiyun #define WL127X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE 30*4882a593Smuzhiyun #define WL127X_MINOR_MR_VER 42 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* FW chip version for wl128x */ 33*4882a593Smuzhiyun #define WL128X_CHIP_VER 7 34*4882a593Smuzhiyun /* minimum single-role FW version for wl128x */ 35*4882a593Smuzhiyun #define WL128X_IFTYPE_SR_VER 3 36*4882a593Smuzhiyun #define WL128X_MAJOR_SR_VER 10 37*4882a593Smuzhiyun #define WL128X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE 38*4882a593Smuzhiyun #define WL128X_MINOR_SR_VER 133 39*4882a593Smuzhiyun /* minimum multi-role FW version for wl128x */ 40*4882a593Smuzhiyun #define WL128X_IFTYPE_MR_VER 5 41*4882a593Smuzhiyun #define WL128X_MAJOR_MR_VER 7 42*4882a593Smuzhiyun #define WL128X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE 43*4882a593Smuzhiyun #define WL128X_MINOR_MR_VER 42 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define WL12XX_NUM_TX_DESCRIPTORS 16 48*4882a593Smuzhiyun #define WL12XX_NUM_RX_DESCRIPTORS 8 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define WL12XX_NUM_MAC_ADDRESSES 2 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define WL12XX_RX_BA_MAX_SESSIONS 3 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define WL12XX_MAX_AP_STATIONS 8 55*4882a593Smuzhiyun #define WL12XX_MAX_LINKS 12 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct wl127x_rx_mem_pool_addr { 58*4882a593Smuzhiyun u32 addr; 59*4882a593Smuzhiyun u32 addr_extra; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct wl12xx_priv { 63*4882a593Smuzhiyun struct wl12xx_priv_conf conf; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun int ref_clock; 66*4882a593Smuzhiyun int tcxo_clock; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct wl127x_rx_mem_pool_addr *rx_mem_addr; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Reference clock values */ 72*4882a593Smuzhiyun enum { 73*4882a593Smuzhiyun WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ 74*4882a593Smuzhiyun WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ 75*4882a593Smuzhiyun WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ 76*4882a593Smuzhiyun WL12XX_REFCLOCK_52 = 3, /* 52 MHz */ 77*4882a593Smuzhiyun WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */ 78*4882a593Smuzhiyun WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* TCXO clock values */ 82*4882a593Smuzhiyun enum { 83*4882a593Smuzhiyun WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */ 84*4882a593Smuzhiyun WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */ 85*4882a593Smuzhiyun WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */ 86*4882a593Smuzhiyun WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */ 87*4882a593Smuzhiyun WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */ 88*4882a593Smuzhiyun WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */ 89*4882a593Smuzhiyun WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */ 90*4882a593Smuzhiyun WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */ 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct wl12xx_clock { 94*4882a593Smuzhiyun u32 freq; 95*4882a593Smuzhiyun bool xtal; 96*4882a593Smuzhiyun u8 hw_idx; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct wl12xx_fw_packet_counters { 100*4882a593Smuzhiyun /* Cumulative counter of released packets per AC */ 101*4882a593Smuzhiyun u8 tx_released_pkts[NUM_TX_QUEUES]; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Cumulative counter of freed packets per HLID */ 104*4882a593Smuzhiyun u8 tx_lnk_free_pkts[WL12XX_MAX_LINKS]; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Cumulative counter of released Voice memory blocks */ 107*4882a593Smuzhiyun u8 tx_voice_released_blks; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Tx rate of the last transmitted packet */ 110*4882a593Smuzhiyun u8 tx_last_rate; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun u8 padding[2]; 113*4882a593Smuzhiyun } __packed; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* FW status registers */ 116*4882a593Smuzhiyun struct wl12xx_fw_status { 117*4882a593Smuzhiyun __le32 intr; 118*4882a593Smuzhiyun u8 fw_rx_counter; 119*4882a593Smuzhiyun u8 drv_rx_counter; 120*4882a593Smuzhiyun u8 reserved; 121*4882a593Smuzhiyun u8 tx_results_counter; 122*4882a593Smuzhiyun __le32 rx_pkt_descs[WL12XX_NUM_RX_DESCRIPTORS]; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun __le32 fw_localtime; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * A bitmap (where each bit represents a single HLID) 128*4882a593Smuzhiyun * to indicate if the station is in PS mode. 129*4882a593Smuzhiyun */ 130*4882a593Smuzhiyun __le32 link_ps_bitmap; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* 133*4882a593Smuzhiyun * A bitmap (where each bit represents a single HLID) to indicate 134*4882a593Smuzhiyun * if the station is in Fast mode 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun __le32 link_fast_bitmap; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Cumulative counter of total released mem blocks since FW-reset */ 139*4882a593Smuzhiyun __le32 total_released_blks; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Size (in Memory Blocks) of TX pool */ 142*4882a593Smuzhiyun __le32 tx_total; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct wl12xx_fw_packet_counters counters; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun __le32 log_start_addr; 147*4882a593Smuzhiyun } __packed; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #endif /* __WL12XX_PRIV_H__ */ 150