1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of wl1251 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 1998-2007 Texas Instruments Incorporated 6*4882a593Smuzhiyun * Copyright (C) 2008 Nokia Corporation 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __WL1251_EVENT_H__ 10*4882a593Smuzhiyun #define __WL1251_EVENT_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Mbox events 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * The event mechanism is based on a pair of event buffers (buffers A and 16*4882a593Smuzhiyun * B) at fixed locations in the target's memory. The host processes one 17*4882a593Smuzhiyun * buffer while the other buffer continues to collect events. If the host 18*4882a593Smuzhiyun * is not processing events, an interrupt is issued to signal that a buffer 19*4882a593Smuzhiyun * is ready. Once the host is done with processing events from one buffer, 20*4882a593Smuzhiyun * it signals the target (with an ACK interrupt) that the event buffer is 21*4882a593Smuzhiyun * free. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum { 25*4882a593Smuzhiyun RESERVED1_EVENT_ID = BIT(0), 26*4882a593Smuzhiyun RESERVED2_EVENT_ID = BIT(1), 27*4882a593Smuzhiyun MEASUREMENT_START_EVENT_ID = BIT(2), 28*4882a593Smuzhiyun SCAN_COMPLETE_EVENT_ID = BIT(3), 29*4882a593Smuzhiyun CALIBRATION_COMPLETE_EVENT_ID = BIT(4), 30*4882a593Smuzhiyun ROAMING_TRIGGER_LOW_RSSI_EVENT_ID = BIT(5), 31*4882a593Smuzhiyun PS_REPORT_EVENT_ID = BIT(6), 32*4882a593Smuzhiyun SYNCHRONIZATION_TIMEOUT_EVENT_ID = BIT(7), 33*4882a593Smuzhiyun HEALTH_REPORT_EVENT_ID = BIT(8), 34*4882a593Smuzhiyun ACI_DETECTION_EVENT_ID = BIT(9), 35*4882a593Smuzhiyun DEBUG_REPORT_EVENT_ID = BIT(10), 36*4882a593Smuzhiyun MAC_STATUS_EVENT_ID = BIT(11), 37*4882a593Smuzhiyun DISCONNECT_EVENT_COMPLETE_ID = BIT(12), 38*4882a593Smuzhiyun JOIN_EVENT_COMPLETE_ID = BIT(13), 39*4882a593Smuzhiyun CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(14), 40*4882a593Smuzhiyun BSS_LOSE_EVENT_ID = BIT(15), 41*4882a593Smuzhiyun ROAMING_TRIGGER_MAX_TX_RETRY_EVENT_ID = BIT(16), 42*4882a593Smuzhiyun MEASUREMENT_COMPLETE_EVENT_ID = BIT(17), 43*4882a593Smuzhiyun AP_DISCOVERY_COMPLETE_EVENT_ID = BIT(18), 44*4882a593Smuzhiyun SCHEDULED_SCAN_COMPLETE_EVENT_ID = BIT(19), 45*4882a593Smuzhiyun PSPOLL_DELIVERY_FAILURE_EVENT_ID = BIT(20), 46*4882a593Smuzhiyun RESET_BSS_EVENT_ID = BIT(21), 47*4882a593Smuzhiyun REGAINED_BSS_EVENT_ID = BIT(22), 48*4882a593Smuzhiyun ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID = BIT(23), 49*4882a593Smuzhiyun ROAMING_TRIGGER_LOW_SNR_EVENT_ID = BIT(24), 50*4882a593Smuzhiyun ROAMING_TRIGGER_REGAINED_SNR_EVENT_ID = BIT(25), 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun DBG_EVENT_ID = BIT(26), 53*4882a593Smuzhiyun BT_PTA_SENSE_EVENT_ID = BIT(27), 54*4882a593Smuzhiyun BT_PTA_PREDICTION_EVENT_ID = BIT(28), 55*4882a593Smuzhiyun BT_PTA_AVALANCHE_EVENT_ID = BIT(29), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun PLT_RX_CALIBRATION_COMPLETE_EVENT_ID = BIT(30), 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun EVENT_MBOX_ALL_EVENT_ID = 0x7fffffff, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct event_debug_report { 63*4882a593Smuzhiyun u8 debug_event_id; 64*4882a593Smuzhiyun u8 num_params; 65*4882a593Smuzhiyun u16 pad; 66*4882a593Smuzhiyun u32 report_1; 67*4882a593Smuzhiyun u32 report_2; 68*4882a593Smuzhiyun u32 report_3; 69*4882a593Smuzhiyun } __packed; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct event_mailbox { 72*4882a593Smuzhiyun u32 events_vector; 73*4882a593Smuzhiyun u32 events_mask; 74*4882a593Smuzhiyun u32 reserved_1; 75*4882a593Smuzhiyun u32 reserved_2; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun char average_rssi_level; 78*4882a593Smuzhiyun u8 ps_status; 79*4882a593Smuzhiyun u8 channel_switch_status; 80*4882a593Smuzhiyun u8 scheduled_scan_status; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Channels scanned by the scheduled scan */ 83*4882a593Smuzhiyun u16 scheduled_scan_channels; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* If bit 0 is set -> target's fatal error */ 86*4882a593Smuzhiyun u16 health_report; 87*4882a593Smuzhiyun u16 bad_fft_counter; 88*4882a593Smuzhiyun u8 bt_pta_sense_info; 89*4882a593Smuzhiyun u8 bt_pta_protective_info; 90*4882a593Smuzhiyun u32 reserved; 91*4882a593Smuzhiyun u32 debug_report[2]; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Number of FCS errors since last event */ 94*4882a593Smuzhiyun u32 fcs_err_counter; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct event_debug_report report; 97*4882a593Smuzhiyun u8 average_snr_level; 98*4882a593Smuzhiyun u8 padding[19]; 99*4882a593Smuzhiyun } __packed; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum { 102*4882a593Smuzhiyun EVENT_ENTER_POWER_SAVE_FAIL = 0, 103*4882a593Smuzhiyun EVENT_ENTER_POWER_SAVE_SUCCESS, 104*4882a593Smuzhiyun EVENT_EXIT_POWER_SAVE_FAIL, 105*4882a593Smuzhiyun EVENT_EXIT_POWER_SAVE_SUCCESS, 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun int wl1251_event_unmask(struct wl1251 *wl); 109*4882a593Smuzhiyun void wl1251_event_mbox_config(struct wl1251 *wl); 110*4882a593Smuzhiyun int wl1251_event_handle(struct wl1251 *wl, u8 mbox); 111*4882a593Smuzhiyun int wl1251_event_wait(struct wl1251 *wl, u32 mask, int timeout_ms); 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114