1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of wl1251 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 1998-2007 Texas Instruments Incorporated 6*4882a593Smuzhiyun * Copyright (C) 2008 Nokia Corporation 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __WL1251_CMD_H__ 10*4882a593Smuzhiyun #define __WL1251_CMD_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "wl1251.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <net/cfg80211.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct acx_header; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun int wl1251_cmd_send(struct wl1251 *wl, u16 type, void *buf, size_t buf_len); 19*4882a593Smuzhiyun int wl1251_cmd_test(struct wl1251 *wl, void *buf, size_t buf_len, u8 answer); 20*4882a593Smuzhiyun int wl1251_cmd_interrogate(struct wl1251 *wl, u16 id, void *buf, size_t len); 21*4882a593Smuzhiyun int wl1251_cmd_configure(struct wl1251 *wl, u16 id, void *buf, size_t len); 22*4882a593Smuzhiyun int wl1251_cmd_vbm(struct wl1251 *wl, u8 identity, 23*4882a593Smuzhiyun void *bitmap, u16 bitmap_len, u8 bitmap_control); 24*4882a593Smuzhiyun int wl1251_cmd_data_path_rx(struct wl1251 *wl, u8 channel, bool enable); 25*4882a593Smuzhiyun int wl1251_cmd_data_path_tx(struct wl1251 *wl, u8 channel, bool enable); 26*4882a593Smuzhiyun int wl1251_cmd_join(struct wl1251 *wl, u8 bss_type, u8 channel, 27*4882a593Smuzhiyun u16 beacon_interval, u8 dtim_interval); 28*4882a593Smuzhiyun int wl1251_cmd_ps_mode(struct wl1251 *wl, u8 ps_mode); 29*4882a593Smuzhiyun int wl1251_cmd_read_memory(struct wl1251 *wl, u32 addr, void *answer, 30*4882a593Smuzhiyun size_t len); 31*4882a593Smuzhiyun int wl1251_cmd_template_set(struct wl1251 *wl, u16 cmd_id, 32*4882a593Smuzhiyun void *buf, size_t buf_len); 33*4882a593Smuzhiyun int wl1251_cmd_scan(struct wl1251 *wl, u8 *ssid, size_t ssid_len, 34*4882a593Smuzhiyun struct ieee80211_channel *channels[], 35*4882a593Smuzhiyun unsigned int n_channels, unsigned int n_probes); 36*4882a593Smuzhiyun int wl1251_cmd_trigger_scan_to(struct wl1251 *wl, u32 timeout); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* unit ms */ 39*4882a593Smuzhiyun #define WL1251_COMMAND_TIMEOUT 2000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum wl1251_commands { 42*4882a593Smuzhiyun CMD_RESET = 0, 43*4882a593Smuzhiyun CMD_INTERROGATE = 1, /*use this to read information elements*/ 44*4882a593Smuzhiyun CMD_CONFIGURE = 2, /*use this to write information elements*/ 45*4882a593Smuzhiyun CMD_ENABLE_RX = 3, 46*4882a593Smuzhiyun CMD_ENABLE_TX = 4, 47*4882a593Smuzhiyun CMD_DISABLE_RX = 5, 48*4882a593Smuzhiyun CMD_DISABLE_TX = 6, 49*4882a593Smuzhiyun CMD_SCAN = 8, 50*4882a593Smuzhiyun CMD_STOP_SCAN = 9, 51*4882a593Smuzhiyun CMD_VBM = 10, 52*4882a593Smuzhiyun CMD_START_JOIN = 11, 53*4882a593Smuzhiyun CMD_SET_KEYS = 12, 54*4882a593Smuzhiyun CMD_READ_MEMORY = 13, 55*4882a593Smuzhiyun CMD_WRITE_MEMORY = 14, 56*4882a593Smuzhiyun CMD_BEACON = 19, 57*4882a593Smuzhiyun CMD_PROBE_RESP = 20, 58*4882a593Smuzhiyun CMD_NULL_DATA = 21, 59*4882a593Smuzhiyun CMD_PROBE_REQ = 22, 60*4882a593Smuzhiyun CMD_TEST = 23, 61*4882a593Smuzhiyun CMD_RADIO_CALIBRATE = 25, /* OBSOLETE */ 62*4882a593Smuzhiyun CMD_ENABLE_RX_PATH = 27, /* OBSOLETE */ 63*4882a593Smuzhiyun CMD_NOISE_HIST = 28, 64*4882a593Smuzhiyun CMD_RX_RESET = 29, 65*4882a593Smuzhiyun CMD_PS_POLL = 30, 66*4882a593Smuzhiyun CMD_QOS_NULL_DATA = 31, 67*4882a593Smuzhiyun CMD_LNA_CONTROL = 32, 68*4882a593Smuzhiyun CMD_SET_BCN_MODE = 33, 69*4882a593Smuzhiyun CMD_MEASUREMENT = 34, 70*4882a593Smuzhiyun CMD_STOP_MEASUREMENT = 35, 71*4882a593Smuzhiyun CMD_DISCONNECT = 36, 72*4882a593Smuzhiyun CMD_SET_PS_MODE = 37, 73*4882a593Smuzhiyun CMD_CHANNEL_SWITCH = 38, 74*4882a593Smuzhiyun CMD_STOP_CHANNEL_SWICTH = 39, 75*4882a593Smuzhiyun CMD_AP_DISCOVERY = 40, 76*4882a593Smuzhiyun CMD_STOP_AP_DISCOVERY = 41, 77*4882a593Smuzhiyun CMD_SPS_SCAN = 42, 78*4882a593Smuzhiyun CMD_STOP_SPS_SCAN = 43, 79*4882a593Smuzhiyun CMD_HEALTH_CHECK = 45, 80*4882a593Smuzhiyun CMD_DEBUG = 46, 81*4882a593Smuzhiyun CMD_TRIGGER_SCAN_TO = 47, 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun NUM_COMMANDS, 84*4882a593Smuzhiyun MAX_COMMAND_ID = 0xFFFF, 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MAX_CMD_PARAMS 572 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct wl1251_cmd_header { 90*4882a593Smuzhiyun u16 id; 91*4882a593Smuzhiyun u16 status; 92*4882a593Smuzhiyun /* payload */ 93*4882a593Smuzhiyun u8 data[]; 94*4882a593Smuzhiyun } __packed; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct wl1251_command { 97*4882a593Smuzhiyun struct wl1251_cmd_header header; 98*4882a593Smuzhiyun u8 parameters[MAX_CMD_PARAMS]; 99*4882a593Smuzhiyun } __packed; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum { 102*4882a593Smuzhiyun CMD_MAILBOX_IDLE = 0, 103*4882a593Smuzhiyun CMD_STATUS_SUCCESS = 1, 104*4882a593Smuzhiyun CMD_STATUS_UNKNOWN_CMD = 2, 105*4882a593Smuzhiyun CMD_STATUS_UNKNOWN_IE = 3, 106*4882a593Smuzhiyun CMD_STATUS_REJECT_MEAS_SG_ACTIVE = 11, 107*4882a593Smuzhiyun CMD_STATUS_RX_BUSY = 13, 108*4882a593Smuzhiyun CMD_STATUS_INVALID_PARAM = 14, 109*4882a593Smuzhiyun CMD_STATUS_TEMPLATE_TOO_LARGE = 15, 110*4882a593Smuzhiyun CMD_STATUS_OUT_OF_MEMORY = 16, 111*4882a593Smuzhiyun CMD_STATUS_STA_TABLE_FULL = 17, 112*4882a593Smuzhiyun CMD_STATUS_RADIO_ERROR = 18, 113*4882a593Smuzhiyun CMD_STATUS_WRONG_NESTING = 19, 114*4882a593Smuzhiyun CMD_STATUS_TIMEOUT = 21, /* Driver internal use.*/ 115*4882a593Smuzhiyun CMD_STATUS_FW_RESET = 22, /* Driver internal use.*/ 116*4882a593Smuzhiyun MAX_COMMAND_STATUS = 0xff 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * CMD_READ_MEMORY 122*4882a593Smuzhiyun * 123*4882a593Smuzhiyun * The host issues this command to read the WiLink device memory/registers. 124*4882a593Smuzhiyun * 125*4882a593Smuzhiyun * Note: The Base Band address has special handling (16 bits registers and 126*4882a593Smuzhiyun * addresses). For more information, see the hardware specification. 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun /* 129*4882a593Smuzhiyun * CMD_WRITE_MEMORY 130*4882a593Smuzhiyun * 131*4882a593Smuzhiyun * The host issues this command to write the WiLink device memory/registers. 132*4882a593Smuzhiyun * 133*4882a593Smuzhiyun * The Base Band address has special handling (16 bits registers and 134*4882a593Smuzhiyun * addresses). For more information, see the hardware specification. 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun #define MAX_READ_SIZE 256 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun struct cmd_read_write_memory { 139*4882a593Smuzhiyun struct wl1251_cmd_header header; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* The address of the memory to read from or write to.*/ 142*4882a593Smuzhiyun u32 addr; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* The amount of data in bytes to read from or write to the WiLink 145*4882a593Smuzhiyun * device.*/ 146*4882a593Smuzhiyun u32 size; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* The actual value read from or written to the Wilink. The source 149*4882a593Smuzhiyun of this field is the Host in WRITE command or the Wilink in READ 150*4882a593Smuzhiyun command. */ 151*4882a593Smuzhiyun u8 value[MAX_READ_SIZE]; 152*4882a593Smuzhiyun } __packed; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define CMDMBOX_HEADER_LEN 4 155*4882a593Smuzhiyun #define CMDMBOX_INFO_ELEM_HEADER_LEN 4 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define WL1251_SCAN_OPT_PASSIVE 1 158*4882a593Smuzhiyun #define WL1251_SCAN_OPT_5GHZ_BAND 2 159*4882a593Smuzhiyun #define WL1251_SCAN_OPT_TRIGGERD_SCAN 4 160*4882a593Smuzhiyun #define WL1251_SCAN_OPT_PRIORITY_HIGH 8 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define WL1251_SCAN_MIN_DURATION 30000 163*4882a593Smuzhiyun #define WL1251_SCAN_MAX_DURATION 60000 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define WL1251_SCAN_NUM_PROBES 3 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun struct wl1251_scan_parameters { 168*4882a593Smuzhiyun __le32 rx_config_options; 169*4882a593Smuzhiyun __le32 rx_filter_options; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * Scan options: 173*4882a593Smuzhiyun * bit 0: When this bit is set, passive scan. 174*4882a593Smuzhiyun * bit 1: Band, when this bit is set we scan 175*4882a593Smuzhiyun * in the 5Ghz band. 176*4882a593Smuzhiyun * bit 2: voice mode, 0 for normal scan. 177*4882a593Smuzhiyun * bit 3: scan priority, 1 for high priority. 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun __le16 scan_options; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* Number of channels to scan */ 182*4882a593Smuzhiyun u8 num_channels; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* Number opf probe requests to send, per channel */ 185*4882a593Smuzhiyun u8 num_probe_requests; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* Rate and modulation for probe requests */ 188*4882a593Smuzhiyun __le16 tx_rate; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun u8 tid_trigger; 191*4882a593Smuzhiyun u8 ssid_len; 192*4882a593Smuzhiyun u8 ssid[32]; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun } __packed; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun struct wl1251_scan_ch_parameters { 197*4882a593Smuzhiyun __le32 min_duration; /* in TU */ 198*4882a593Smuzhiyun __le32 max_duration; /* in TU */ 199*4882a593Smuzhiyun u32 bssid_lsb; 200*4882a593Smuzhiyun u16 bssid_msb; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* 203*4882a593Smuzhiyun * bits 0-3: Early termination count. 204*4882a593Smuzhiyun * bits 4-5: Early termination condition. 205*4882a593Smuzhiyun */ 206*4882a593Smuzhiyun u8 early_termination; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun u8 tx_power_att; 209*4882a593Smuzhiyun u8 channel; 210*4882a593Smuzhiyun u8 pad[3]; 211*4882a593Smuzhiyun } __packed; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* SCAN parameters */ 214*4882a593Smuzhiyun #define SCAN_MAX_NUM_OF_CHANNELS 16 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun struct wl1251_cmd_scan { 217*4882a593Smuzhiyun struct wl1251_cmd_header header; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun struct wl1251_scan_parameters params; 220*4882a593Smuzhiyun struct wl1251_scan_ch_parameters channels[SCAN_MAX_NUM_OF_CHANNELS]; 221*4882a593Smuzhiyun } __packed; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun enum { 224*4882a593Smuzhiyun BSS_TYPE_IBSS = 0, 225*4882a593Smuzhiyun BSS_TYPE_STA_BSS = 2, 226*4882a593Smuzhiyun BSS_TYPE_AP_BSS = 3, 227*4882a593Smuzhiyun MAX_BSS_TYPE = 0xFF 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define JOIN_CMD_CTRL_TX_FLUSH 0x80 /* Firmware flushes all Tx */ 231*4882a593Smuzhiyun #define JOIN_CMD_CTRL_EARLY_WAKEUP_ENABLE 0x01 /* Early wakeup time */ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun struct cmd_join { 235*4882a593Smuzhiyun struct wl1251_cmd_header header; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun u32 bssid_lsb; 238*4882a593Smuzhiyun u16 bssid_msb; 239*4882a593Smuzhiyun u16 beacon_interval; /* in TBTTs */ 240*4882a593Smuzhiyun u32 rx_config_options; 241*4882a593Smuzhiyun u32 rx_filter_options; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* 244*4882a593Smuzhiyun * The target uses this field to determine the rate at 245*4882a593Smuzhiyun * which to transmit control frame responses (such as 246*4882a593Smuzhiyun * ACK or CTS frames). 247*4882a593Smuzhiyun */ 248*4882a593Smuzhiyun u16 basic_rate_set; 249*4882a593Smuzhiyun u8 dtim_interval; 250*4882a593Smuzhiyun u8 tx_ctrl_frame_rate; /* OBSOLETE */ 251*4882a593Smuzhiyun u8 tx_ctrl_frame_mod; /* OBSOLETE */ 252*4882a593Smuzhiyun /* 253*4882a593Smuzhiyun * bits 0-2: This bitwise field specifies the type 254*4882a593Smuzhiyun * of BSS to start or join (BSS_TYPE_*). 255*4882a593Smuzhiyun * bit 4: Band - The radio band in which to join 256*4882a593Smuzhiyun * or start. 257*4882a593Smuzhiyun * 0 - 2.4GHz band 258*4882a593Smuzhiyun * 1 - 5GHz band 259*4882a593Smuzhiyun * bits 3, 5-7: Reserved 260*4882a593Smuzhiyun */ 261*4882a593Smuzhiyun u8 bss_type; 262*4882a593Smuzhiyun u8 channel; 263*4882a593Smuzhiyun u8 ssid_len; 264*4882a593Smuzhiyun u8 ssid[IEEE80211_MAX_SSID_LEN]; 265*4882a593Smuzhiyun u8 ctrl; /* JOIN_CMD_CTRL_* */ 266*4882a593Smuzhiyun u8 tx_mgt_frame_rate; /* OBSOLETE */ 267*4882a593Smuzhiyun u8 tx_mgt_frame_mod; /* OBSOLETE */ 268*4882a593Smuzhiyun u8 reserved; 269*4882a593Smuzhiyun } __packed; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun struct cmd_enabledisable_path { 272*4882a593Smuzhiyun struct wl1251_cmd_header header; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun u8 channel; 275*4882a593Smuzhiyun u8 padding[3]; 276*4882a593Smuzhiyun } __packed; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define WL1251_MAX_TEMPLATE_SIZE 300 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun struct wl1251_cmd_packet_template { 281*4882a593Smuzhiyun struct wl1251_cmd_header header; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun __le16 size; 284*4882a593Smuzhiyun u8 data[]; 285*4882a593Smuzhiyun } __packed; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define TIM_ELE_ID 5 288*4882a593Smuzhiyun #define PARTIAL_VBM_MAX 251 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun struct wl1251_tim { 291*4882a593Smuzhiyun u8 identity; 292*4882a593Smuzhiyun u8 length; 293*4882a593Smuzhiyun u8 dtim_count; 294*4882a593Smuzhiyun u8 dtim_period; 295*4882a593Smuzhiyun u8 bitmap_ctrl; 296*4882a593Smuzhiyun u8 pvb_field[PARTIAL_VBM_MAX]; /* Partial Virtual Bitmap */ 297*4882a593Smuzhiyun } __packed; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* Virtual Bit Map update */ 300*4882a593Smuzhiyun struct wl1251_cmd_vbm_update { 301*4882a593Smuzhiyun struct wl1251_cmd_header header; 302*4882a593Smuzhiyun __le16 len; 303*4882a593Smuzhiyun u8 padding[2]; 304*4882a593Smuzhiyun struct wl1251_tim tim; 305*4882a593Smuzhiyun } __packed; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun enum wl1251_cmd_ps_mode { 308*4882a593Smuzhiyun CHIP_ACTIVE_MODE, 309*4882a593Smuzhiyun CHIP_POWER_SAVE_MODE 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun struct wl1251_cmd_ps_params { 313*4882a593Smuzhiyun struct wl1251_cmd_header header; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun u8 ps_mode; /* STATION_* */ 316*4882a593Smuzhiyun u8 send_null_data; /* Do we have to send NULL data packet ? */ 317*4882a593Smuzhiyun u8 retries; /* Number of retires for the initial NULL data packet */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* 320*4882a593Smuzhiyun * TUs during which the target stays awake after switching 321*4882a593Smuzhiyun * to power save mode. 322*4882a593Smuzhiyun */ 323*4882a593Smuzhiyun u8 hang_over_period; 324*4882a593Smuzhiyun u16 null_data_rate; 325*4882a593Smuzhiyun u8 pad[2]; 326*4882a593Smuzhiyun } __packed; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun struct wl1251_cmd_trigger_scan_to { 329*4882a593Smuzhiyun struct wl1251_cmd_header header; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun u32 timeout; 332*4882a593Smuzhiyun } __packed; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /* HW encryption keys */ 335*4882a593Smuzhiyun #define NUM_ACCESS_CATEGORIES_COPY 4 336*4882a593Smuzhiyun #define MAX_KEY_SIZE 32 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* When set, disable HW encryption */ 339*4882a593Smuzhiyun #define DF_ENCRYPTION_DISABLE 0x01 340*4882a593Smuzhiyun /* When set, disable HW decryption */ 341*4882a593Smuzhiyun #define DF_SNIFF_MODE_ENABLE 0x80 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun enum wl1251_cmd_key_action { 344*4882a593Smuzhiyun KEY_ADD_OR_REPLACE = 1, 345*4882a593Smuzhiyun KEY_REMOVE = 2, 346*4882a593Smuzhiyun KEY_SET_ID = 3, 347*4882a593Smuzhiyun MAX_KEY_ACTION = 0xffff, 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun enum wl1251_cmd_key_type { 351*4882a593Smuzhiyun KEY_WEP_DEFAULT = 0, 352*4882a593Smuzhiyun KEY_WEP_ADDR = 1, 353*4882a593Smuzhiyun KEY_AES_GROUP = 4, 354*4882a593Smuzhiyun KEY_AES_PAIRWISE = 5, 355*4882a593Smuzhiyun KEY_WEP_GROUP = 6, 356*4882a593Smuzhiyun KEY_TKIP_MIC_GROUP = 10, 357*4882a593Smuzhiyun KEY_TKIP_MIC_PAIRWISE = 11, 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* 361*4882a593Smuzhiyun * 362*4882a593Smuzhiyun * key_type_e key size key format 363*4882a593Smuzhiyun * ---------- --------- ---------- 364*4882a593Smuzhiyun * 0x00 5, 13, 29 Key data 365*4882a593Smuzhiyun * 0x01 5, 13, 29 Key data 366*4882a593Smuzhiyun * 0x04 16 16 bytes of key data 367*4882a593Smuzhiyun * 0x05 16 16 bytes of key data 368*4882a593Smuzhiyun * 0x0a 32 16 bytes of TKIP key data 369*4882a593Smuzhiyun * 8 bytes of RX MIC key data 370*4882a593Smuzhiyun * 8 bytes of TX MIC key data 371*4882a593Smuzhiyun * 0x0b 32 16 bytes of TKIP key data 372*4882a593Smuzhiyun * 8 bytes of RX MIC key data 373*4882a593Smuzhiyun * 8 bytes of TX MIC key data 374*4882a593Smuzhiyun * 375*4882a593Smuzhiyun */ 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun struct wl1251_cmd_set_keys { 378*4882a593Smuzhiyun struct wl1251_cmd_header header; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun /* Ignored for default WEP key */ 381*4882a593Smuzhiyun u8 addr[ETH_ALEN]; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /* key_action_e */ 384*4882a593Smuzhiyun u16 key_action; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun u16 reserved_1; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* key size in bytes */ 389*4882a593Smuzhiyun u8 key_size; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun /* key_type_e */ 392*4882a593Smuzhiyun u8 key_type; 393*4882a593Smuzhiyun u8 ssid_profile; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun /* 396*4882a593Smuzhiyun * TKIP, AES: frame's key id field. 397*4882a593Smuzhiyun * For WEP default key: key id; 398*4882a593Smuzhiyun */ 399*4882a593Smuzhiyun u8 id; 400*4882a593Smuzhiyun u8 reserved_2[6]; 401*4882a593Smuzhiyun u8 key[MAX_KEY_SIZE]; 402*4882a593Smuzhiyun u16 ac_seq_num16[NUM_ACCESS_CATEGORIES_COPY]; 403*4882a593Smuzhiyun u32 ac_seq_num32[NUM_ACCESS_CATEGORIES_COPY]; 404*4882a593Smuzhiyun } __packed; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun #endif /* __WL1251_CMD_H__ */ 408