xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/st/cw1200/main.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mac80211 glue code for mac80211 ST-Ericsson CW1200 drivers
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2010, ST-Ericsson
6*4882a593Smuzhiyun  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on:
9*4882a593Smuzhiyun  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
10*4882a593Smuzhiyun  * Copyright (c) 2007-2009, Christian Lamparter <chunkeey@web.de>
11*4882a593Smuzhiyun  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Based on:
14*4882a593Smuzhiyun  * - the islsm (softmac prism54) driver, which is:
15*4882a593Smuzhiyun  *   Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
16*4882a593Smuzhiyun  * - stlc45xx driver
17*4882a593Smuzhiyun  *   Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/firmware.h>
22*4882a593Smuzhiyun #include <linux/etherdevice.h>
23*4882a593Smuzhiyun #include <linux/vmalloc.h>
24*4882a593Smuzhiyun #include <linux/random.h>
25*4882a593Smuzhiyun #include <linux/sched.h>
26*4882a593Smuzhiyun #include <net/mac80211.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "cw1200.h"
29*4882a593Smuzhiyun #include "txrx.h"
30*4882a593Smuzhiyun #include "hwbus.h"
31*4882a593Smuzhiyun #include "fwio.h"
32*4882a593Smuzhiyun #include "hwio.h"
33*4882a593Smuzhiyun #include "bh.h"
34*4882a593Smuzhiyun #include "sta.h"
35*4882a593Smuzhiyun #include "scan.h"
36*4882a593Smuzhiyun #include "debug.h"
37*4882a593Smuzhiyun #include "pm.h"
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun MODULE_AUTHOR("Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>");
40*4882a593Smuzhiyun MODULE_DESCRIPTION("Softmac ST-Ericsson CW1200 common code");
41*4882a593Smuzhiyun MODULE_LICENSE("GPL");
42*4882a593Smuzhiyun MODULE_ALIAS("cw1200_core");
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* Accept MAC address of the form macaddr=0x00,0x80,0xE1,0x30,0x40,0x50 */
45*4882a593Smuzhiyun static u8 cw1200_mac_template[ETH_ALEN] = {0x02, 0x80, 0xe1, 0x00, 0x00, 0x00};
46*4882a593Smuzhiyun module_param_array_named(macaddr, cw1200_mac_template, byte, NULL, 0444);
47*4882a593Smuzhiyun MODULE_PARM_DESC(macaddr, "Override platform_data MAC address");
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static char *cw1200_sdd_path;
50*4882a593Smuzhiyun module_param(cw1200_sdd_path, charp, 0644);
51*4882a593Smuzhiyun MODULE_PARM_DESC(cw1200_sdd_path, "Override platform_data SDD file");
52*4882a593Smuzhiyun static int cw1200_refclk;
53*4882a593Smuzhiyun module_param(cw1200_refclk, int, 0644);
54*4882a593Smuzhiyun MODULE_PARM_DESC(cw1200_refclk, "Override platform_data reference clock");
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun int cw1200_power_mode = wsm_power_mode_quiescent;
57*4882a593Smuzhiyun module_param(cw1200_power_mode, int, 0644);
58*4882a593Smuzhiyun MODULE_PARM_DESC(cw1200_power_mode, "WSM power mode.  0 == active, 1 == doze, 2 == quiescent (default)");
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define RATETAB_ENT(_rate, _rateid, _flags)		\
61*4882a593Smuzhiyun 	{						\
62*4882a593Smuzhiyun 		.bitrate	= (_rate),		\
63*4882a593Smuzhiyun 		.hw_value	= (_rateid),		\
64*4882a593Smuzhiyun 		.flags		= (_flags),		\
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun static struct ieee80211_rate cw1200_rates[] = {
68*4882a593Smuzhiyun 	RATETAB_ENT(10,  0,   0),
69*4882a593Smuzhiyun 	RATETAB_ENT(20,  1,   0),
70*4882a593Smuzhiyun 	RATETAB_ENT(55,  2,   0),
71*4882a593Smuzhiyun 	RATETAB_ENT(110, 3,   0),
72*4882a593Smuzhiyun 	RATETAB_ENT(60,  6,  0),
73*4882a593Smuzhiyun 	RATETAB_ENT(90,  7,  0),
74*4882a593Smuzhiyun 	RATETAB_ENT(120, 8,  0),
75*4882a593Smuzhiyun 	RATETAB_ENT(180, 9,  0),
76*4882a593Smuzhiyun 	RATETAB_ENT(240, 10, 0),
77*4882a593Smuzhiyun 	RATETAB_ENT(360, 11, 0),
78*4882a593Smuzhiyun 	RATETAB_ENT(480, 12, 0),
79*4882a593Smuzhiyun 	RATETAB_ENT(540, 13, 0),
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static struct ieee80211_rate cw1200_mcs_rates[] = {
83*4882a593Smuzhiyun 	RATETAB_ENT(65,  14, IEEE80211_TX_RC_MCS),
84*4882a593Smuzhiyun 	RATETAB_ENT(130, 15, IEEE80211_TX_RC_MCS),
85*4882a593Smuzhiyun 	RATETAB_ENT(195, 16, IEEE80211_TX_RC_MCS),
86*4882a593Smuzhiyun 	RATETAB_ENT(260, 17, IEEE80211_TX_RC_MCS),
87*4882a593Smuzhiyun 	RATETAB_ENT(390, 18, IEEE80211_TX_RC_MCS),
88*4882a593Smuzhiyun 	RATETAB_ENT(520, 19, IEEE80211_TX_RC_MCS),
89*4882a593Smuzhiyun 	RATETAB_ENT(585, 20, IEEE80211_TX_RC_MCS),
90*4882a593Smuzhiyun 	RATETAB_ENT(650, 21, IEEE80211_TX_RC_MCS),
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define cw1200_a_rates		(cw1200_rates + 4)
94*4882a593Smuzhiyun #define cw1200_a_rates_size	(ARRAY_SIZE(cw1200_rates) - 4)
95*4882a593Smuzhiyun #define cw1200_g_rates		(cw1200_rates + 0)
96*4882a593Smuzhiyun #define cw1200_g_rates_size	(ARRAY_SIZE(cw1200_rates))
97*4882a593Smuzhiyun #define cw1200_n_rates		(cw1200_mcs_rates)
98*4882a593Smuzhiyun #define cw1200_n_rates_size	(ARRAY_SIZE(cw1200_mcs_rates))
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun #define CHAN2G(_channel, _freq, _flags) {			\
102*4882a593Smuzhiyun 	.band			= NL80211_BAND_2GHZ,		\
103*4882a593Smuzhiyun 	.center_freq		= (_freq),			\
104*4882a593Smuzhiyun 	.hw_value		= (_channel),			\
105*4882a593Smuzhiyun 	.flags			= (_flags),			\
106*4882a593Smuzhiyun 	.max_antenna_gain	= 0,				\
107*4882a593Smuzhiyun 	.max_power		= 30,				\
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define CHAN5G(_channel, _flags) {				\
111*4882a593Smuzhiyun 	.band			= NL80211_BAND_5GHZ,		\
112*4882a593Smuzhiyun 	.center_freq	= 5000 + (5 * (_channel)),		\
113*4882a593Smuzhiyun 	.hw_value		= (_channel),			\
114*4882a593Smuzhiyun 	.flags			= (_flags),			\
115*4882a593Smuzhiyun 	.max_antenna_gain	= 0,				\
116*4882a593Smuzhiyun 	.max_power		= 30,				\
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static struct ieee80211_channel cw1200_2ghz_chantable[] = {
120*4882a593Smuzhiyun 	CHAN2G(1, 2412, 0),
121*4882a593Smuzhiyun 	CHAN2G(2, 2417, 0),
122*4882a593Smuzhiyun 	CHAN2G(3, 2422, 0),
123*4882a593Smuzhiyun 	CHAN2G(4, 2427, 0),
124*4882a593Smuzhiyun 	CHAN2G(5, 2432, 0),
125*4882a593Smuzhiyun 	CHAN2G(6, 2437, 0),
126*4882a593Smuzhiyun 	CHAN2G(7, 2442, 0),
127*4882a593Smuzhiyun 	CHAN2G(8, 2447, 0),
128*4882a593Smuzhiyun 	CHAN2G(9, 2452, 0),
129*4882a593Smuzhiyun 	CHAN2G(10, 2457, 0),
130*4882a593Smuzhiyun 	CHAN2G(11, 2462, 0),
131*4882a593Smuzhiyun 	CHAN2G(12, 2467, 0),
132*4882a593Smuzhiyun 	CHAN2G(13, 2472, 0),
133*4882a593Smuzhiyun 	CHAN2G(14, 2484, 0),
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static struct ieee80211_channel cw1200_5ghz_chantable[] = {
137*4882a593Smuzhiyun 	CHAN5G(34, 0),		CHAN5G(36, 0),
138*4882a593Smuzhiyun 	CHAN5G(38, 0),		CHAN5G(40, 0),
139*4882a593Smuzhiyun 	CHAN5G(42, 0),		CHAN5G(44, 0),
140*4882a593Smuzhiyun 	CHAN5G(46, 0),		CHAN5G(48, 0),
141*4882a593Smuzhiyun 	CHAN5G(52, 0),		CHAN5G(56, 0),
142*4882a593Smuzhiyun 	CHAN5G(60, 0),		CHAN5G(64, 0),
143*4882a593Smuzhiyun 	CHAN5G(100, 0),		CHAN5G(104, 0),
144*4882a593Smuzhiyun 	CHAN5G(108, 0),		CHAN5G(112, 0),
145*4882a593Smuzhiyun 	CHAN5G(116, 0),		CHAN5G(120, 0),
146*4882a593Smuzhiyun 	CHAN5G(124, 0),		CHAN5G(128, 0),
147*4882a593Smuzhiyun 	CHAN5G(132, 0),		CHAN5G(136, 0),
148*4882a593Smuzhiyun 	CHAN5G(140, 0),		CHAN5G(149, 0),
149*4882a593Smuzhiyun 	CHAN5G(153, 0),		CHAN5G(157, 0),
150*4882a593Smuzhiyun 	CHAN5G(161, 0),		CHAN5G(165, 0),
151*4882a593Smuzhiyun 	CHAN5G(184, 0),		CHAN5G(188, 0),
152*4882a593Smuzhiyun 	CHAN5G(192, 0),		CHAN5G(196, 0),
153*4882a593Smuzhiyun 	CHAN5G(200, 0),		CHAN5G(204, 0),
154*4882a593Smuzhiyun 	CHAN5G(208, 0),		CHAN5G(212, 0),
155*4882a593Smuzhiyun 	CHAN5G(216, 0),
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static struct ieee80211_supported_band cw1200_band_2ghz = {
159*4882a593Smuzhiyun 	.channels = cw1200_2ghz_chantable,
160*4882a593Smuzhiyun 	.n_channels = ARRAY_SIZE(cw1200_2ghz_chantable),
161*4882a593Smuzhiyun 	.bitrates = cw1200_g_rates,
162*4882a593Smuzhiyun 	.n_bitrates = cw1200_g_rates_size,
163*4882a593Smuzhiyun 	.ht_cap = {
164*4882a593Smuzhiyun 		.cap = IEEE80211_HT_CAP_GRN_FLD |
165*4882a593Smuzhiyun 			(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
166*4882a593Smuzhiyun 			IEEE80211_HT_CAP_MAX_AMSDU,
167*4882a593Smuzhiyun 		.ht_supported = 1,
168*4882a593Smuzhiyun 		.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
169*4882a593Smuzhiyun 		.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE,
170*4882a593Smuzhiyun 		.mcs = {
171*4882a593Smuzhiyun 			.rx_mask[0] = 0xFF,
172*4882a593Smuzhiyun 			.rx_highest = __cpu_to_le16(0x41),
173*4882a593Smuzhiyun 			.tx_params = IEEE80211_HT_MCS_TX_DEFINED,
174*4882a593Smuzhiyun 		},
175*4882a593Smuzhiyun 	},
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static struct ieee80211_supported_band cw1200_band_5ghz = {
179*4882a593Smuzhiyun 	.channels = cw1200_5ghz_chantable,
180*4882a593Smuzhiyun 	.n_channels = ARRAY_SIZE(cw1200_5ghz_chantable),
181*4882a593Smuzhiyun 	.bitrates = cw1200_a_rates,
182*4882a593Smuzhiyun 	.n_bitrates = cw1200_a_rates_size,
183*4882a593Smuzhiyun 	.ht_cap = {
184*4882a593Smuzhiyun 		.cap = IEEE80211_HT_CAP_GRN_FLD |
185*4882a593Smuzhiyun 			(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
186*4882a593Smuzhiyun 			IEEE80211_HT_CAP_MAX_AMSDU,
187*4882a593Smuzhiyun 		.ht_supported = 1,
188*4882a593Smuzhiyun 		.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
189*4882a593Smuzhiyun 		.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE,
190*4882a593Smuzhiyun 		.mcs = {
191*4882a593Smuzhiyun 			.rx_mask[0] = 0xFF,
192*4882a593Smuzhiyun 			.rx_highest = __cpu_to_le16(0x41),
193*4882a593Smuzhiyun 			.tx_params = IEEE80211_HT_MCS_TX_DEFINED,
194*4882a593Smuzhiyun 		},
195*4882a593Smuzhiyun 	},
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static const unsigned long cw1200_ttl[] = {
199*4882a593Smuzhiyun 	1 * HZ,	/* VO */
200*4882a593Smuzhiyun 	2 * HZ,	/* VI */
201*4882a593Smuzhiyun 	5 * HZ, /* BE */
202*4882a593Smuzhiyun 	10 * HZ	/* BK */
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct ieee80211_ops cw1200_ops = {
206*4882a593Smuzhiyun 	.start			= cw1200_start,
207*4882a593Smuzhiyun 	.stop			= cw1200_stop,
208*4882a593Smuzhiyun 	.add_interface		= cw1200_add_interface,
209*4882a593Smuzhiyun 	.remove_interface	= cw1200_remove_interface,
210*4882a593Smuzhiyun 	.change_interface	= cw1200_change_interface,
211*4882a593Smuzhiyun 	.tx			= cw1200_tx,
212*4882a593Smuzhiyun 	.hw_scan		= cw1200_hw_scan,
213*4882a593Smuzhiyun 	.set_tim		= cw1200_set_tim,
214*4882a593Smuzhiyun 	.sta_notify		= cw1200_sta_notify,
215*4882a593Smuzhiyun 	.sta_add		= cw1200_sta_add,
216*4882a593Smuzhiyun 	.sta_remove		= cw1200_sta_remove,
217*4882a593Smuzhiyun 	.set_key		= cw1200_set_key,
218*4882a593Smuzhiyun 	.set_rts_threshold	= cw1200_set_rts_threshold,
219*4882a593Smuzhiyun 	.config			= cw1200_config,
220*4882a593Smuzhiyun 	.bss_info_changed	= cw1200_bss_info_changed,
221*4882a593Smuzhiyun 	.prepare_multicast	= cw1200_prepare_multicast,
222*4882a593Smuzhiyun 	.configure_filter	= cw1200_configure_filter,
223*4882a593Smuzhiyun 	.conf_tx		= cw1200_conf_tx,
224*4882a593Smuzhiyun 	.get_stats		= cw1200_get_stats,
225*4882a593Smuzhiyun 	.ampdu_action		= cw1200_ampdu_action,
226*4882a593Smuzhiyun 	.flush			= cw1200_flush,
227*4882a593Smuzhiyun #ifdef CONFIG_PM
228*4882a593Smuzhiyun 	.suspend		= cw1200_wow_suspend,
229*4882a593Smuzhiyun 	.resume			= cw1200_wow_resume,
230*4882a593Smuzhiyun #endif
231*4882a593Smuzhiyun 	/* Intentionally not offloaded:					*/
232*4882a593Smuzhiyun 	/*.channel_switch	= cw1200_channel_switch,		*/
233*4882a593Smuzhiyun 	/*.remain_on_channel	= cw1200_remain_on_channel,		*/
234*4882a593Smuzhiyun 	/*.cancel_remain_on_channel = cw1200_cancel_remain_on_channel,	*/
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun static int cw1200_ba_rx_tids = -1;
238*4882a593Smuzhiyun static int cw1200_ba_tx_tids = -1;
239*4882a593Smuzhiyun module_param(cw1200_ba_rx_tids, int, 0644);
240*4882a593Smuzhiyun module_param(cw1200_ba_tx_tids, int, 0644);
241*4882a593Smuzhiyun MODULE_PARM_DESC(cw1200_ba_rx_tids, "Block ACK RX TIDs");
242*4882a593Smuzhiyun MODULE_PARM_DESC(cw1200_ba_tx_tids, "Block ACK TX TIDs");
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #ifdef CONFIG_PM
245*4882a593Smuzhiyun static const struct wiphy_wowlan_support cw1200_wowlan_support = {
246*4882a593Smuzhiyun 	/* Support only for limited wowlan functionalities */
247*4882a593Smuzhiyun 	.flags = WIPHY_WOWLAN_ANY | WIPHY_WOWLAN_DISCONNECT,
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun #endif
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 
cw1200_init_common(const u8 * macaddr,const bool have_5ghz)252*4882a593Smuzhiyun static struct ieee80211_hw *cw1200_init_common(const u8 *macaddr,
253*4882a593Smuzhiyun 						const bool have_5ghz)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	int i, band;
256*4882a593Smuzhiyun 	struct ieee80211_hw *hw;
257*4882a593Smuzhiyun 	struct cw1200_common *priv;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	hw = ieee80211_alloc_hw(sizeof(struct cw1200_common), &cw1200_ops);
260*4882a593Smuzhiyun 	if (!hw)
261*4882a593Smuzhiyun 		return NULL;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	priv = hw->priv;
264*4882a593Smuzhiyun 	priv->hw = hw;
265*4882a593Smuzhiyun 	priv->hw_type = -1;
266*4882a593Smuzhiyun 	priv->mode = NL80211_IFTYPE_UNSPECIFIED;
267*4882a593Smuzhiyun 	priv->rates = cw1200_rates; /* TODO: fetch from FW */
268*4882a593Smuzhiyun 	priv->mcs_rates = cw1200_n_rates;
269*4882a593Smuzhiyun 	if (cw1200_ba_rx_tids != -1)
270*4882a593Smuzhiyun 		priv->ba_rx_tid_mask = cw1200_ba_rx_tids;
271*4882a593Smuzhiyun 	else
272*4882a593Smuzhiyun 		priv->ba_rx_tid_mask = 0xFF; /* Enable RX BLKACK for all TIDs */
273*4882a593Smuzhiyun 	if (cw1200_ba_tx_tids != -1)
274*4882a593Smuzhiyun 		priv->ba_tx_tid_mask = cw1200_ba_tx_tids;
275*4882a593Smuzhiyun 	else
276*4882a593Smuzhiyun 		priv->ba_tx_tid_mask = 0xff; /* Enable TX BLKACK for all TIDs */
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC);
279*4882a593Smuzhiyun 	ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW);
280*4882a593Smuzhiyun 	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
281*4882a593Smuzhiyun 	ieee80211_hw_set(hw, CONNECTION_MONITOR);
282*4882a593Smuzhiyun 	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
283*4882a593Smuzhiyun 	ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
284*4882a593Smuzhiyun 	ieee80211_hw_set(hw, SIGNAL_DBM);
285*4882a593Smuzhiyun 	ieee80211_hw_set(hw, SUPPORTS_PS);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
288*4882a593Smuzhiyun 					  BIT(NL80211_IFTYPE_ADHOC) |
289*4882a593Smuzhiyun 					  BIT(NL80211_IFTYPE_AP) |
290*4882a593Smuzhiyun 					  BIT(NL80211_IFTYPE_MESH_POINT) |
291*4882a593Smuzhiyun 					  BIT(NL80211_IFTYPE_P2P_CLIENT) |
292*4882a593Smuzhiyun 					  BIT(NL80211_IFTYPE_P2P_GO);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun #ifdef CONFIG_PM
295*4882a593Smuzhiyun 	hw->wiphy->wowlan = &cw1200_wowlan_support;
296*4882a593Smuzhiyun #endif
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	hw->queues = 4;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	priv->rts_threshold = -1;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	hw->max_rates = 8;
305*4882a593Smuzhiyun 	hw->max_rate_tries = 15;
306*4882a593Smuzhiyun 	hw->extra_tx_headroom = WSM_TX_EXTRA_HEADROOM +
307*4882a593Smuzhiyun 		8;  /* TKIP IV */
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	hw->sta_data_size = sizeof(struct cw1200_sta_priv);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	hw->wiphy->bands[NL80211_BAND_2GHZ] = &cw1200_band_2ghz;
312*4882a593Smuzhiyun 	if (have_5ghz)
313*4882a593Smuzhiyun 		hw->wiphy->bands[NL80211_BAND_5GHZ] = &cw1200_band_5ghz;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	/* Channel params have to be cleared before registering wiphy again */
316*4882a593Smuzhiyun 	for (band = 0; band < NUM_NL80211_BANDS; band++) {
317*4882a593Smuzhiyun 		struct ieee80211_supported_band *sband = hw->wiphy->bands[band];
318*4882a593Smuzhiyun 		if (!sband)
319*4882a593Smuzhiyun 			continue;
320*4882a593Smuzhiyun 		for (i = 0; i < sband->n_channels; i++) {
321*4882a593Smuzhiyun 			sband->channels[i].flags = 0;
322*4882a593Smuzhiyun 			sband->channels[i].max_antenna_gain = 0;
323*4882a593Smuzhiyun 			sband->channels[i].max_power = 30;
324*4882a593Smuzhiyun 		}
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	hw->wiphy->max_scan_ssids = 2;
328*4882a593Smuzhiyun 	hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	if (macaddr)
331*4882a593Smuzhiyun 		SET_IEEE80211_PERM_ADDR(hw, (u8 *)macaddr);
332*4882a593Smuzhiyun 	else
333*4882a593Smuzhiyun 		SET_IEEE80211_PERM_ADDR(hw, cw1200_mac_template);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	/* Fix up mac address if necessary */
336*4882a593Smuzhiyun 	if (hw->wiphy->perm_addr[3] == 0 &&
337*4882a593Smuzhiyun 	    hw->wiphy->perm_addr[4] == 0 &&
338*4882a593Smuzhiyun 	    hw->wiphy->perm_addr[5] == 0) {
339*4882a593Smuzhiyun 		get_random_bytes(&hw->wiphy->perm_addr[3], 3);
340*4882a593Smuzhiyun 	}
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	mutex_init(&priv->wsm_cmd_mux);
343*4882a593Smuzhiyun 	mutex_init(&priv->conf_mutex);
344*4882a593Smuzhiyun 	priv->workqueue = create_singlethread_workqueue("cw1200_wq");
345*4882a593Smuzhiyun 	if (!priv->workqueue) {
346*4882a593Smuzhiyun 		ieee80211_free_hw(hw);
347*4882a593Smuzhiyun 		return NULL;
348*4882a593Smuzhiyun 	}
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	sema_init(&priv->scan.lock, 1);
351*4882a593Smuzhiyun 	INIT_WORK(&priv->scan.work, cw1200_scan_work);
352*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->scan.probe_work, cw1200_probe_work);
353*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->scan.timeout, cw1200_scan_timeout);
354*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->clear_recent_scan_work,
355*4882a593Smuzhiyun 			  cw1200_clear_recent_scan_work);
356*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->join_timeout, cw1200_join_timeout);
357*4882a593Smuzhiyun 	INIT_WORK(&priv->unjoin_work, cw1200_unjoin_work);
358*4882a593Smuzhiyun 	INIT_WORK(&priv->join_complete_work, cw1200_join_complete_work);
359*4882a593Smuzhiyun 	INIT_WORK(&priv->wep_key_work, cw1200_wep_key_work);
360*4882a593Smuzhiyun 	INIT_WORK(&priv->tx_policy_upload_work, tx_policy_upload_work);
361*4882a593Smuzhiyun 	spin_lock_init(&priv->event_queue_lock);
362*4882a593Smuzhiyun 	INIT_LIST_HEAD(&priv->event_queue);
363*4882a593Smuzhiyun 	INIT_WORK(&priv->event_handler, cw1200_event_handler);
364*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->bss_loss_work, cw1200_bss_loss_work);
365*4882a593Smuzhiyun 	INIT_WORK(&priv->bss_params_work, cw1200_bss_params_work);
366*4882a593Smuzhiyun 	spin_lock_init(&priv->bss_loss_lock);
367*4882a593Smuzhiyun 	spin_lock_init(&priv->ps_state_lock);
368*4882a593Smuzhiyun 	INIT_WORK(&priv->set_cts_work, cw1200_set_cts_work);
369*4882a593Smuzhiyun 	INIT_WORK(&priv->set_tim_work, cw1200_set_tim_work);
370*4882a593Smuzhiyun 	INIT_WORK(&priv->multicast_start_work, cw1200_multicast_start_work);
371*4882a593Smuzhiyun 	INIT_WORK(&priv->multicast_stop_work, cw1200_multicast_stop_work);
372*4882a593Smuzhiyun 	INIT_WORK(&priv->link_id_work, cw1200_link_id_work);
373*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&priv->link_id_gc_work, cw1200_link_id_gc_work);
374*4882a593Smuzhiyun 	INIT_WORK(&priv->linkid_reset_work, cw1200_link_id_reset);
375*4882a593Smuzhiyun 	INIT_WORK(&priv->update_filtering_work, cw1200_update_filtering_work);
376*4882a593Smuzhiyun 	INIT_WORK(&priv->set_beacon_wakeup_period_work,
377*4882a593Smuzhiyun 		  cw1200_set_beacon_wakeup_period_work);
378*4882a593Smuzhiyun 	timer_setup(&priv->mcast_timeout, cw1200_mcast_timeout, 0);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	if (cw1200_queue_stats_init(&priv->tx_queue_stats,
381*4882a593Smuzhiyun 				    CW1200_LINK_ID_MAX,
382*4882a593Smuzhiyun 				    cw1200_skb_dtor,
383*4882a593Smuzhiyun 				    priv)) {
384*4882a593Smuzhiyun 		destroy_workqueue(priv->workqueue);
385*4882a593Smuzhiyun 		ieee80211_free_hw(hw);
386*4882a593Smuzhiyun 		return NULL;
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	for (i = 0; i < 4; ++i) {
390*4882a593Smuzhiyun 		if (cw1200_queue_init(&priv->tx_queue[i],
391*4882a593Smuzhiyun 				      &priv->tx_queue_stats, i, 16,
392*4882a593Smuzhiyun 				      cw1200_ttl[i])) {
393*4882a593Smuzhiyun 			for (; i > 0; i--)
394*4882a593Smuzhiyun 				cw1200_queue_deinit(&priv->tx_queue[i - 1]);
395*4882a593Smuzhiyun 			cw1200_queue_stats_deinit(&priv->tx_queue_stats);
396*4882a593Smuzhiyun 			destroy_workqueue(priv->workqueue);
397*4882a593Smuzhiyun 			ieee80211_free_hw(hw);
398*4882a593Smuzhiyun 			return NULL;
399*4882a593Smuzhiyun 		}
400*4882a593Smuzhiyun 	}
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	init_waitqueue_head(&priv->channel_switch_done);
403*4882a593Smuzhiyun 	init_waitqueue_head(&priv->wsm_cmd_wq);
404*4882a593Smuzhiyun 	init_waitqueue_head(&priv->wsm_startup_done);
405*4882a593Smuzhiyun 	init_waitqueue_head(&priv->ps_mode_switch_done);
406*4882a593Smuzhiyun 	wsm_buf_init(&priv->wsm_cmd_buf);
407*4882a593Smuzhiyun 	spin_lock_init(&priv->wsm_cmd.lock);
408*4882a593Smuzhiyun 	priv->wsm_cmd.done = 1;
409*4882a593Smuzhiyun 	tx_policy_init(priv);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	return hw;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun 
cw1200_register_common(struct ieee80211_hw * dev)414*4882a593Smuzhiyun static int cw1200_register_common(struct ieee80211_hw *dev)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun 	struct cw1200_common *priv = dev->priv;
417*4882a593Smuzhiyun 	int err;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun #ifdef CONFIG_PM
420*4882a593Smuzhiyun 	err = cw1200_pm_init(&priv->pm_state, priv);
421*4882a593Smuzhiyun 	if (err) {
422*4882a593Smuzhiyun 		pr_err("Cannot init PM. (%d).\n",
423*4882a593Smuzhiyun 		       err);
424*4882a593Smuzhiyun 		return err;
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun #endif
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	err = ieee80211_register_hw(dev);
429*4882a593Smuzhiyun 	if (err) {
430*4882a593Smuzhiyun 		pr_err("Cannot register device (%d).\n",
431*4882a593Smuzhiyun 		       err);
432*4882a593Smuzhiyun #ifdef CONFIG_PM
433*4882a593Smuzhiyun 		cw1200_pm_deinit(&priv->pm_state);
434*4882a593Smuzhiyun #endif
435*4882a593Smuzhiyun 		return err;
436*4882a593Smuzhiyun 	}
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	cw1200_debug_init(priv);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	pr_info("Registered as '%s'\n", wiphy_name(dev->wiphy));
441*4882a593Smuzhiyun 	return 0;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun 
cw1200_free_common(struct ieee80211_hw * dev)444*4882a593Smuzhiyun static void cw1200_free_common(struct ieee80211_hw *dev)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	ieee80211_free_hw(dev);
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun 
cw1200_unregister_common(struct ieee80211_hw * dev)449*4882a593Smuzhiyun static void cw1200_unregister_common(struct ieee80211_hw *dev)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	struct cw1200_common *priv = dev->priv;
452*4882a593Smuzhiyun 	int i;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	ieee80211_unregister_hw(dev);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	del_timer_sync(&priv->mcast_timeout);
457*4882a593Smuzhiyun 	cw1200_unregister_bh(priv);
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	cw1200_debug_release(priv);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	mutex_destroy(&priv->conf_mutex);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	wsm_buf_deinit(&priv->wsm_cmd_buf);
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	destroy_workqueue(priv->workqueue);
466*4882a593Smuzhiyun 	priv->workqueue = NULL;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	if (priv->sdd) {
469*4882a593Smuzhiyun 		release_firmware(priv->sdd);
470*4882a593Smuzhiyun 		priv->sdd = NULL;
471*4882a593Smuzhiyun 	}
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	for (i = 0; i < 4; ++i)
474*4882a593Smuzhiyun 		cw1200_queue_deinit(&priv->tx_queue[i]);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	cw1200_queue_stats_deinit(&priv->tx_queue_stats);
477*4882a593Smuzhiyun #ifdef CONFIG_PM
478*4882a593Smuzhiyun 	cw1200_pm_deinit(&priv->pm_state);
479*4882a593Smuzhiyun #endif
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun /* Clock is in KHz */
cw1200_dpll_from_clk(u16 clk_khz)483*4882a593Smuzhiyun u32 cw1200_dpll_from_clk(u16 clk_khz)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun 	switch (clk_khz) {
486*4882a593Smuzhiyun 	case 0x32C8: /* 13000 KHz */
487*4882a593Smuzhiyun 		return 0x1D89D241;
488*4882a593Smuzhiyun 	case 0x3E80: /* 16000 KHz */
489*4882a593Smuzhiyun 		return 0x000001E1;
490*4882a593Smuzhiyun 	case 0x41A0: /* 16800 KHz */
491*4882a593Smuzhiyun 		return 0x124931C1;
492*4882a593Smuzhiyun 	case 0x4B00: /* 19200 KHz */
493*4882a593Smuzhiyun 		return 0x00000191;
494*4882a593Smuzhiyun 	case 0x5DC0: /* 24000 KHz */
495*4882a593Smuzhiyun 		return 0x00000141;
496*4882a593Smuzhiyun 	case 0x6590: /* 26000 KHz */
497*4882a593Smuzhiyun 		return 0x0EC4F121;
498*4882a593Smuzhiyun 	case 0x8340: /* 33600 KHz */
499*4882a593Smuzhiyun 		return 0x092490E1;
500*4882a593Smuzhiyun 	case 0x9600: /* 38400 KHz */
501*4882a593Smuzhiyun 		return 0x100010C1;
502*4882a593Smuzhiyun 	case 0x9C40: /* 40000 KHz */
503*4882a593Smuzhiyun 		return 0x000000C1;
504*4882a593Smuzhiyun 	case 0xBB80: /* 48000 KHz */
505*4882a593Smuzhiyun 		return 0x000000A1;
506*4882a593Smuzhiyun 	case 0xCB20: /* 52000 KHz */
507*4882a593Smuzhiyun 		return 0x07627091;
508*4882a593Smuzhiyun 	default:
509*4882a593Smuzhiyun 		pr_err("Unknown Refclk freq (0x%04x), using 26000KHz\n",
510*4882a593Smuzhiyun 		       clk_khz);
511*4882a593Smuzhiyun 		return 0x0EC4F121;
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun 
cw1200_core_probe(const struct hwbus_ops * hwbus_ops,struct hwbus_priv * hwbus,struct device * pdev,struct cw1200_common ** core,int ref_clk,const u8 * macaddr,const char * sdd_path,bool have_5ghz)515*4882a593Smuzhiyun int cw1200_core_probe(const struct hwbus_ops *hwbus_ops,
516*4882a593Smuzhiyun 		      struct hwbus_priv *hwbus,
517*4882a593Smuzhiyun 		      struct device *pdev,
518*4882a593Smuzhiyun 		      struct cw1200_common **core,
519*4882a593Smuzhiyun 		      int ref_clk, const u8 *macaddr,
520*4882a593Smuzhiyun 		      const char *sdd_path, bool have_5ghz)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun 	int err = -EINVAL;
523*4882a593Smuzhiyun 	struct ieee80211_hw *dev;
524*4882a593Smuzhiyun 	struct cw1200_common *priv;
525*4882a593Smuzhiyun 	struct wsm_operational_mode mode = {
526*4882a593Smuzhiyun 		.power_mode = cw1200_power_mode,
527*4882a593Smuzhiyun 		.disable_more_flag_usage = true,
528*4882a593Smuzhiyun 	};
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	dev = cw1200_init_common(macaddr, have_5ghz);
531*4882a593Smuzhiyun 	if (!dev)
532*4882a593Smuzhiyun 		goto err;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	priv = dev->priv;
535*4882a593Smuzhiyun 	priv->hw_refclk = ref_clk;
536*4882a593Smuzhiyun 	if (cw1200_refclk)
537*4882a593Smuzhiyun 		priv->hw_refclk = cw1200_refclk;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	priv->sdd_path = (char *)sdd_path;
540*4882a593Smuzhiyun 	if (cw1200_sdd_path)
541*4882a593Smuzhiyun 		priv->sdd_path = cw1200_sdd_path;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	priv->hwbus_ops = hwbus_ops;
544*4882a593Smuzhiyun 	priv->hwbus_priv = hwbus;
545*4882a593Smuzhiyun 	priv->pdev = pdev;
546*4882a593Smuzhiyun 	SET_IEEE80211_DEV(priv->hw, pdev);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	/* Pass struct cw1200_common back up */
549*4882a593Smuzhiyun 	*core = priv;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	err = cw1200_register_bh(priv);
552*4882a593Smuzhiyun 	if (err)
553*4882a593Smuzhiyun 		goto err1;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	err = cw1200_load_firmware(priv);
556*4882a593Smuzhiyun 	if (err)
557*4882a593Smuzhiyun 		goto err2;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	if (wait_event_interruptible_timeout(priv->wsm_startup_done,
560*4882a593Smuzhiyun 					     priv->firmware_ready,
561*4882a593Smuzhiyun 					     3*HZ) <= 0) {
562*4882a593Smuzhiyun 		/* TODO: Need to find how to reset device
563*4882a593Smuzhiyun 		   in QUEUE mode properly.
564*4882a593Smuzhiyun 		*/
565*4882a593Smuzhiyun 		pr_err("Timeout waiting on device startup\n");
566*4882a593Smuzhiyun 		err = -ETIMEDOUT;
567*4882a593Smuzhiyun 		goto err2;
568*4882a593Smuzhiyun 	}
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	/* Set low-power mode. */
571*4882a593Smuzhiyun 	wsm_set_operational_mode(priv, &mode);
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	/* Enable multi-TX confirmation */
574*4882a593Smuzhiyun 	wsm_use_multi_tx_conf(priv, true);
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 	err = cw1200_register_common(dev);
577*4882a593Smuzhiyun 	if (err)
578*4882a593Smuzhiyun 		goto err2;
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	return err;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun err2:
583*4882a593Smuzhiyun 	cw1200_unregister_bh(priv);
584*4882a593Smuzhiyun err1:
585*4882a593Smuzhiyun 	cw1200_free_common(dev);
586*4882a593Smuzhiyun err:
587*4882a593Smuzhiyun 	*core = NULL;
588*4882a593Smuzhiyun 	return err;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cw1200_core_probe);
591*4882a593Smuzhiyun 
cw1200_core_release(struct cw1200_common * self)592*4882a593Smuzhiyun void cw1200_core_release(struct cw1200_common *self)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun 	/* Disable device interrupts */
595*4882a593Smuzhiyun 	self->hwbus_ops->lock(self->hwbus_priv);
596*4882a593Smuzhiyun 	__cw1200_irq_enable(self, 0);
597*4882a593Smuzhiyun 	self->hwbus_ops->unlock(self->hwbus_priv);
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	/* And then clean up */
600*4882a593Smuzhiyun 	cw1200_unregister_common(self->hw);
601*4882a593Smuzhiyun 	cw1200_free_common(self->hw);
602*4882a593Smuzhiyun 	return;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cw1200_core_release);
605