1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * @section LICENSE 3*4882a593Smuzhiyun * Copyright (c) 2014 Redpine Signals Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 6*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 7*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __RSI_SDIO_INTF__ 20*4882a593Smuzhiyun #define __RSI_SDIO_INTF__ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include <linux/mmc/card.h> 23*4882a593Smuzhiyun #include <linux/mmc/mmc.h> 24*4882a593Smuzhiyun #include <linux/mmc/host.h> 25*4882a593Smuzhiyun #include <linux/mmc/sdio_func.h> 26*4882a593Smuzhiyun #include <linux/mmc/sdio.h> 27*4882a593Smuzhiyun #include <linux/mmc/sd.h> 28*4882a593Smuzhiyun #include <linux/mmc/sdio_ids.h> 29*4882a593Smuzhiyun #include "rsi_main.h" 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum sdio_interrupt_type { 32*4882a593Smuzhiyun BUFFER_FULL = 0x0, 33*4882a593Smuzhiyun BUFFER_AVAILABLE = 0x2, 34*4882a593Smuzhiyun FIRMWARE_ASSERT_IND = 0x3, 35*4882a593Smuzhiyun MSDU_PACKET_PENDING = 0x4, 36*4882a593Smuzhiyun UNKNOWN_INT = 0XE 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Buffer status register related info */ 40*4882a593Smuzhiyun #define PKT_BUFF_SEMI_FULL 0 41*4882a593Smuzhiyun #define PKT_BUFF_FULL 1 42*4882a593Smuzhiyun #define PKT_MGMT_BUFF_FULL 2 43*4882a593Smuzhiyun #define MSDU_PKT_PENDING 3 44*4882a593Smuzhiyun #define RECV_NUM_BLOCKS 4 45*4882a593Smuzhiyun /* Interrupt Bit Related Macros */ 46*4882a593Smuzhiyun #define PKT_BUFF_AVAILABLE 1 47*4882a593Smuzhiyun #define FW_ASSERT_IND 2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define RSI_MASTER_REG_BUF_SIZE 12 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3 52*4882a593Smuzhiyun #define RSI_FN1_INT_REGISTER 0xf9 53*4882a593Smuzhiyun #define RSI_INT_ENABLE_REGISTER 0x04 54*4882a593Smuzhiyun #define RSI_INT_ENABLE_MASK 0xfc 55*4882a593Smuzhiyun #define RSI_SD_REQUEST_MASTER 0x10000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* FOR SD CARD ONLY */ 58*4882a593Smuzhiyun #define SDIO_RX_NUM_BLOCKS_REG 0x000F1 59*4882a593Smuzhiyun #define SDIO_FW_STATUS_REG 0x000F2 60*4882a593Smuzhiyun #define SDIO_NXT_RD_DELAY2 0x000F5 61*4882a593Smuzhiyun #define SDIO_MASTER_ACCESS_MSBYTE 0x000FA 62*4882a593Smuzhiyun #define SDIO_MASTER_ACCESS_LSBYTE 0x000FB 63*4882a593Smuzhiyun #define SDIO_READ_START_LVL 0x000FC 64*4882a593Smuzhiyun #define SDIO_READ_FIFO_CTL 0x000FD 65*4882a593Smuzhiyun #define SDIO_WRITE_FIFO_CTL 0x000FE 66*4882a593Smuzhiyun #define SDIO_WAKEUP_REG 0x000FF 67*4882a593Smuzhiyun #define SDIO_FUN1_INTR_CLR_REG 0x0008 68*4882a593Smuzhiyun #define SDIO_REG_HIGH_SPEED 0x0013 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE) \ 71*4882a593Smuzhiyun { \ 72*4882a593Smuzhiyun TYPE = \ 73*4882a593Smuzhiyun (_I & (1 << PKT_BUFF_AVAILABLE)) ? \ 74*4882a593Smuzhiyun BUFFER_AVAILABLE : \ 75*4882a593Smuzhiyun (_I & (1 << MSDU_PKT_PENDING)) ? \ 76*4882a593Smuzhiyun MSDU_PACKET_PENDING : \ 77*4882a593Smuzhiyun (_I & (1 << FW_ASSERT_IND)) ? \ 78*4882a593Smuzhiyun FIRMWARE_ASSERT_IND : UNKNOWN_INT; \ 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* common registers in SDIO function1 */ 82*4882a593Smuzhiyun #define TA_SOFT_RESET_REG 0x0004 83*4882a593Smuzhiyun #define TA_TH0_PC_REG 0x0400 84*4882a593Smuzhiyun #define TA_HOLD_THREAD_REG 0x0844 85*4882a593Smuzhiyun #define TA_RELEASE_THREAD_REG 0x0848 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define TA_SOFT_RST_CLR 0 88*4882a593Smuzhiyun #define TA_SOFT_RST_SET BIT(0) 89*4882a593Smuzhiyun #define TA_PC_ZERO 0 90*4882a593Smuzhiyun #define TA_HOLD_THREAD_VALUE 0xF 91*4882a593Smuzhiyun #define TA_RELEASE_THREAD_VALUE 0xF 92*4882a593Smuzhiyun #define TA_BASE_ADDR 0x2200 93*4882a593Smuzhiyun #define MISC_CFG_BASE_ADDR 0x4105 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct receive_info { 96*4882a593Smuzhiyun bool buffer_full; 97*4882a593Smuzhiyun bool semi_buffer_full; 98*4882a593Smuzhiyun bool mgmt_buffer_full; 99*4882a593Smuzhiyun u32 mgmt_buf_full_counter; 100*4882a593Smuzhiyun u32 buf_semi_full_counter; 101*4882a593Smuzhiyun u8 watch_bufferfull_count; 102*4882a593Smuzhiyun u32 sdio_intr_status_zero; 103*4882a593Smuzhiyun u32 sdio_int_counter; 104*4882a593Smuzhiyun u32 total_sdio_msdu_pending_intr; 105*4882a593Smuzhiyun u32 total_sdio_unknown_intr; 106*4882a593Smuzhiyun u32 buf_full_counter; 107*4882a593Smuzhiyun u32 buf_available_counter; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun struct rsi_91x_sdiodev { 111*4882a593Smuzhiyun struct sdio_func *pfunction; 112*4882a593Smuzhiyun struct task_struct *sdio_irq_task; 113*4882a593Smuzhiyun struct receive_info rx_info; 114*4882a593Smuzhiyun u32 next_read_delay; 115*4882a593Smuzhiyun u32 sdio_high_speed_enable; 116*4882a593Smuzhiyun u8 sdio_clock_speed; 117*4882a593Smuzhiyun u32 cardcapability; 118*4882a593Smuzhiyun u8 prev_desc[16]; 119*4882a593Smuzhiyun u16 tx_blk_size; 120*4882a593Smuzhiyun u8 write_fail; 121*4882a593Smuzhiyun bool buff_status_updated; 122*4882a593Smuzhiyun struct rsi_thread rx_thread; 123*4882a593Smuzhiyun u8 pktbuffer[8192] __aligned(4); 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun int rsi_init_sdio_slave_regs(struct rsi_hw *adapter); 127*4882a593Smuzhiyun int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data); 128*4882a593Smuzhiyun int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length); 129*4882a593Smuzhiyun int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function, 130*4882a593Smuzhiyun u32 addr, u8 *data); 131*4882a593Smuzhiyun int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr, 132*4882a593Smuzhiyun u8 *data, u16 count); 133*4882a593Smuzhiyun int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word); 134*4882a593Smuzhiyun void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit); 135*4882a593Smuzhiyun int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter); 136*4882a593Smuzhiyun int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num); 137*4882a593Smuzhiyun void rsi_sdio_rx_thread(struct rsi_common *common); 138*4882a593Smuzhiyun #endif 139