1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun * Copyright (c) 2014 Redpine Signals Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any
5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above
6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifndef __RSI_MGMT_H__
18*4882a593Smuzhiyun #define __RSI_MGMT_H__
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/sort.h>
21*4882a593Smuzhiyun #include "rsi_boot_params.h"
22*4882a593Smuzhiyun #include "rsi_main.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MAX_MGMT_PKT_SIZE 512
25*4882a593Smuzhiyun #define RSI_NEEDED_HEADROOM 84
26*4882a593Smuzhiyun #define RSI_RCV_BUFFER_LEN 2000
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define RSI_11B_MODE 0
29*4882a593Smuzhiyun #define RSI_11G_MODE BIT(7)
30*4882a593Smuzhiyun #define RETRY_COUNT 8
31*4882a593Smuzhiyun #define RETRY_LONG 4
32*4882a593Smuzhiyun #define RETRY_SHORT 7
33*4882a593Smuzhiyun #define WMM_SHORT_SLOT_TIME 9
34*4882a593Smuzhiyun #define SIFS_DURATION 16
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define EAPOL4_PACKET_LEN 0x85
37*4882a593Smuzhiyun #define KEY_TYPE_CLEAR 0
38*4882a593Smuzhiyun #define RSI_PAIRWISE_KEY 1
39*4882a593Smuzhiyun #define RSI_GROUP_KEY 2
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* EPPROM_READ_ADDRESS */
42*4882a593Smuzhiyun #define WLAN_MAC_EEPROM_ADDR 40
43*4882a593Smuzhiyun #define WLAN_MAC_MAGIC_WORD_LEN 0x01
44*4882a593Smuzhiyun #define WLAN_HOST_MODE_LEN 0x04
45*4882a593Smuzhiyun #define WLAN_FW_VERSION_LEN 0x08
46*4882a593Smuzhiyun #define MAGIC_WORD 0x5A
47*4882a593Smuzhiyun #define WLAN_EEPROM_RFTYPE_ADDR 424
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /*WOWLAN RESUME WAKEUP TYPES*/
50*4882a593Smuzhiyun #define RSI_UNICAST_MAGIC_PKT BIT(0)
51*4882a593Smuzhiyun #define RSI_BROADCAST_MAGICPKT BIT(1)
52*4882a593Smuzhiyun #define RSI_EAPOL_PKT BIT(2)
53*4882a593Smuzhiyun #define RSI_DISCONNECT_PKT BIT(3)
54*4882a593Smuzhiyun #define RSI_HW_BMISS_PKT BIT(4)
55*4882a593Smuzhiyun #define RSI_INSERT_SEQ_IN_FW BIT(2)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define WOW_MAX_FILTERS_PER_LIST 16
58*4882a593Smuzhiyun #define WOW_PATTERN_SIZE 256
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Receive Frame Types */
61*4882a593Smuzhiyun #define RSI_RX_DESC_MSG_TYPE_OFFSET 2
62*4882a593Smuzhiyun #define TA_CONFIRM_TYPE 0x01
63*4882a593Smuzhiyun #define RX_DOT11_MGMT 0x02
64*4882a593Smuzhiyun #define TX_STATUS_IND 0x04
65*4882a593Smuzhiyun #define BEACON_EVENT_IND 0x08
66*4882a593Smuzhiyun #define EAPOL4_CONFIRM 1
67*4882a593Smuzhiyun #define PROBEREQ_CONFIRM 2
68*4882a593Smuzhiyun #define CARD_READY_IND 0x00
69*4882a593Smuzhiyun #define SLEEP_NOTIFY_IND 0x06
70*4882a593Smuzhiyun #define RSI_TX_STATUS_TYPE 15
71*4882a593Smuzhiyun #define RSI_TX_STATUS 12
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define RSI_DELETE_PEER 0x0
74*4882a593Smuzhiyun #define RSI_ADD_PEER 0x1
75*4882a593Smuzhiyun #define START_AMPDU_AGGR 0x1
76*4882a593Smuzhiyun #define STOP_AMPDU_AGGR 0x0
77*4882a593Smuzhiyun #define INTERNAL_MGMT_PKT 0x99
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define PUT_BBP_RESET 0
80*4882a593Smuzhiyun #define BBP_REG_WRITE 0
81*4882a593Smuzhiyun #define RF_RESET_ENABLE BIT(3)
82*4882a593Smuzhiyun #define RATE_INFO_ENABLE BIT(0)
83*4882a593Smuzhiyun #define MORE_DATA_PRESENT BIT(1)
84*4882a593Smuzhiyun #define RSI_BROADCAST_PKT BIT(9)
85*4882a593Smuzhiyun #define RSI_DESC_REQUIRE_CFM_TO_HOST BIT(2)
86*4882a593Smuzhiyun #define RSI_ADD_DELTA_TSF_VAP_ID BIT(3)
87*4882a593Smuzhiyun #define RSI_FETCH_RETRY_CNT_FRM_HST BIT(4)
88*4882a593Smuzhiyun #define RSI_QOS_ENABLE BIT(12)
89*4882a593Smuzhiyun #define RSI_REKEY_PURPOSE BIT(13)
90*4882a593Smuzhiyun #define RSI_ENCRYPT_PKT BIT(15)
91*4882a593Smuzhiyun #define RSI_SET_PS_ENABLE BIT(12)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define RSI_CMDDESC_40MHZ BIT(4)
94*4882a593Smuzhiyun #define RSI_CMDDESC_UPPER_20_ENABLE BIT(5)
95*4882a593Smuzhiyun #define RSI_CMDDESC_LOWER_20_ENABLE BIT(6)
96*4882a593Smuzhiyun #define RSI_CMDDESC_FULL_40_ENABLE (BIT(5) | BIT(6))
97*4882a593Smuzhiyun #define UPPER_20_ENABLE (0x2 << 12)
98*4882a593Smuzhiyun #define LOWER_20_ENABLE (0x4 << 12)
99*4882a593Smuzhiyun #define FULL40M_ENABLE 0x6
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define RSI_LMAC_CLOCK_80MHZ 0x1
102*4882a593Smuzhiyun #define RSI_ENABLE_40MHZ (0x1 << 3)
103*4882a593Smuzhiyun #define ENABLE_SHORTGI_RATE BIT(9)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define RX_BA_INDICATION 1
106*4882a593Smuzhiyun #define RSI_TBL_SZ 40
107*4882a593Smuzhiyun #define MAX_RETRIES 8
108*4882a593Smuzhiyun #define RSI_IFTYPE_STATION 0
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define STD_RATE_MCS7 0x07
111*4882a593Smuzhiyun #define STD_RATE_MCS6 0x06
112*4882a593Smuzhiyun #define STD_RATE_MCS5 0x05
113*4882a593Smuzhiyun #define STD_RATE_MCS4 0x04
114*4882a593Smuzhiyun #define STD_RATE_MCS3 0x03
115*4882a593Smuzhiyun #define STD_RATE_MCS2 0x02
116*4882a593Smuzhiyun #define STD_RATE_MCS1 0x01
117*4882a593Smuzhiyun #define STD_RATE_MCS0 0x00
118*4882a593Smuzhiyun #define STD_RATE_54 0x6c
119*4882a593Smuzhiyun #define STD_RATE_48 0x60
120*4882a593Smuzhiyun #define STD_RATE_36 0x48
121*4882a593Smuzhiyun #define STD_RATE_24 0x30
122*4882a593Smuzhiyun #define STD_RATE_18 0x24
123*4882a593Smuzhiyun #define STD_RATE_12 0x18
124*4882a593Smuzhiyun #define STD_RATE_11 0x16
125*4882a593Smuzhiyun #define STD_RATE_09 0x12
126*4882a593Smuzhiyun #define STD_RATE_06 0x0C
127*4882a593Smuzhiyun #define STD_RATE_5_5 0x0B
128*4882a593Smuzhiyun #define STD_RATE_02 0x04
129*4882a593Smuzhiyun #define STD_RATE_01 0x02
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define RSI_RF_TYPE 1
132*4882a593Smuzhiyun #define RSI_RATE_00 0x00
133*4882a593Smuzhiyun #define RSI_RATE_1 0x0
134*4882a593Smuzhiyun #define RSI_RATE_2 0x2
135*4882a593Smuzhiyun #define RSI_RATE_5_5 0x4
136*4882a593Smuzhiyun #define RSI_RATE_11 0x6
137*4882a593Smuzhiyun #define RSI_RATE_6 0x8b
138*4882a593Smuzhiyun #define RSI_RATE_9 0x8f
139*4882a593Smuzhiyun #define RSI_RATE_12 0x8a
140*4882a593Smuzhiyun #define RSI_RATE_18 0x8e
141*4882a593Smuzhiyun #define RSI_RATE_24 0x89
142*4882a593Smuzhiyun #define RSI_RATE_36 0x8d
143*4882a593Smuzhiyun #define RSI_RATE_48 0x88
144*4882a593Smuzhiyun #define RSI_RATE_54 0x8c
145*4882a593Smuzhiyun #define RSI_RATE_MCS0 0x100
146*4882a593Smuzhiyun #define RSI_RATE_MCS1 0x101
147*4882a593Smuzhiyun #define RSI_RATE_MCS2 0x102
148*4882a593Smuzhiyun #define RSI_RATE_MCS3 0x103
149*4882a593Smuzhiyun #define RSI_RATE_MCS4 0x104
150*4882a593Smuzhiyun #define RSI_RATE_MCS5 0x105
151*4882a593Smuzhiyun #define RSI_RATE_MCS6 0x106
152*4882a593Smuzhiyun #define RSI_RATE_MCS7 0x107
153*4882a593Smuzhiyun #define RSI_RATE_MCS7_SG 0x307
154*4882a593Smuzhiyun #define RSI_RATE_AUTO 0xffff
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun #define BW_20MHZ 0
157*4882a593Smuzhiyun #define BW_40MHZ 1
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun #define EP_2GHZ_20MHZ 0
160*4882a593Smuzhiyun #define EP_2GHZ_40MHZ 1
161*4882a593Smuzhiyun #define EP_5GHZ_20MHZ 2
162*4882a593Smuzhiyun #define EP_5GHZ_40MHZ 3
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun #define SIFS_TX_11N_VALUE 580
165*4882a593Smuzhiyun #define SIFS_TX_11B_VALUE 346
166*4882a593Smuzhiyun #define SHORT_SLOT_VALUE 360
167*4882a593Smuzhiyun #define LONG_SLOT_VALUE 640
168*4882a593Smuzhiyun #define OFDM_ACK_TOUT_VALUE 2720
169*4882a593Smuzhiyun #define CCK_ACK_TOUT_VALUE 9440
170*4882a593Smuzhiyun #define LONG_PREAMBLE 0x0000
171*4882a593Smuzhiyun #define SHORT_PREAMBLE 0x0001
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun #define RSI_SUPP_FILTERS (FIF_ALLMULTI | FIF_PROBE_REQ |\
174*4882a593Smuzhiyun FIF_BCN_PRBRESP_PROMISC)
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define ANTENNA_SEL_INT 0x02 /* RF_OUT_2 / Integerated */
177*4882a593Smuzhiyun #define ANTENNA_SEL_UFL 0x03 /* RF_OUT_1 / U.FL */
178*4882a593Smuzhiyun #define ANTENNA_MASK_VALUE 0x00ff
179*4882a593Smuzhiyun #define ANTENNA_SEL_TYPE 1
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Rx filter word definitions */
182*4882a593Smuzhiyun #define PROMISCOUS_MODE BIT(0)
183*4882a593Smuzhiyun #define ALLOW_DATA_ASSOC_PEER BIT(1)
184*4882a593Smuzhiyun #define ALLOW_MGMT_ASSOC_PEER BIT(2)
185*4882a593Smuzhiyun #define ALLOW_CTRL_ASSOC_PEER BIT(3)
186*4882a593Smuzhiyun #define DISALLOW_BEACONS BIT(4)
187*4882a593Smuzhiyun #define ALLOW_CONN_PEER_MGMT_WHILE_BUF_FULL BIT(5)
188*4882a593Smuzhiyun #define DISALLOW_BROADCAST_DATA BIT(6)
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun #define RSI_MPDU_DENSITY 0x8
191*4882a593Smuzhiyun #define RSI_CHAN_RADAR BIT(7)
192*4882a593Smuzhiyun #define RSI_BEACON_INTERVAL 200
193*4882a593Smuzhiyun #define RSI_DTIM_COUNT 2
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #define RSI_PS_DISABLE_IND BIT(15)
196*4882a593Smuzhiyun #define RSI_PS_ENABLE 1
197*4882a593Smuzhiyun #define RSI_PS_DISABLE 0
198*4882a593Smuzhiyun #define RSI_DEEP_SLEEP 1
199*4882a593Smuzhiyun #define RSI_CONNECTED_SLEEP 2
200*4882a593Smuzhiyun #define RSI_SLEEP_REQUEST 1
201*4882a593Smuzhiyun #define RSI_WAKEUP_REQUEST 2
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun #define RSI_IEEE80211_UAPSD_QUEUES \
204*4882a593Smuzhiyun (IEEE80211_WMM_IE_STA_QOSINFO_AC_VO | \
205*4882a593Smuzhiyun IEEE80211_WMM_IE_STA_QOSINFO_AC_VI | \
206*4882a593Smuzhiyun IEEE80211_WMM_IE_STA_QOSINFO_AC_BE | \
207*4882a593Smuzhiyun IEEE80211_WMM_IE_STA_QOSINFO_AC_BK)
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun #define RSI_DESC_VAP_ID_MASK 0xC000u
210*4882a593Smuzhiyun #define RSI_DESC_VAP_ID_OFST 14
211*4882a593Smuzhiyun #define RSI_DATA_DESC_MAC_BBP_INFO BIT(0)
212*4882a593Smuzhiyun #define RSI_DATA_DESC_NO_ACK_IND BIT(9)
213*4882a593Smuzhiyun #define RSI_DATA_DESC_QOS_EN BIT(12)
214*4882a593Smuzhiyun #define RSI_DATA_DESC_NORMAL_FRAME 0x00
215*4882a593Smuzhiyun #define RSI_DATA_DESC_DTIM_BEACON_GATED_FRAME BIT(10)
216*4882a593Smuzhiyun #define RSI_DATA_DESC_BEACON_FRAME BIT(11)
217*4882a593Smuzhiyun #define RSI_DATA_DESC_DTIM_BEACON (BIT(10) | BIT(11))
218*4882a593Smuzhiyun #define RSI_DATA_DESC_INSERT_TSF BIT(15)
219*4882a593Smuzhiyun #define RSI_DATA_DESC_INSERT_SEQ_NO BIT(2)
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun #ifdef CONFIG_PM
222*4882a593Smuzhiyun #define RSI_WOW_ANY BIT(1)
223*4882a593Smuzhiyun #define RSI_WOW_GTK_REKEY BIT(3)
224*4882a593Smuzhiyun #define RSI_WOW_MAGIC_PKT BIT(4)
225*4882a593Smuzhiyun #define RSI_WOW_DISCONNECT BIT(5)
226*4882a593Smuzhiyun #endif
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun #define RSI_MAX_TX_AGGR_FRMS 8
229*4882a593Smuzhiyun #define RSI_MAX_RX_AGGR_FRMS 8
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun #define RSI_MAX_SCAN_SSIDS 16
232*4882a593Smuzhiyun #define RSI_MAX_SCAN_IE_LEN 256
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun enum opmode {
235*4882a593Smuzhiyun RSI_OPMODE_UNSUPPORTED = -1,
236*4882a593Smuzhiyun RSI_OPMODE_AP = 0,
237*4882a593Smuzhiyun RSI_OPMODE_STA,
238*4882a593Smuzhiyun RSI_OPMODE_P2P_GO,
239*4882a593Smuzhiyun RSI_OPMODE_P2P_CLIENT
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun enum vap_status {
243*4882a593Smuzhiyun VAP_ADD = 1,
244*4882a593Smuzhiyun VAP_DELETE = 2,
245*4882a593Smuzhiyun VAP_UPDATE = 3
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun enum peer_type {
249*4882a593Smuzhiyun PEER_TYPE_AP,
250*4882a593Smuzhiyun PEER_TYPE_STA,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun extern struct ieee80211_rate rsi_rates[12];
253*4882a593Smuzhiyun extern const u16 rsi_mcsrates[8];
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun enum sta_notify_events {
256*4882a593Smuzhiyun STA_CONNECTED = 0,
257*4882a593Smuzhiyun STA_DISCONNECTED,
258*4882a593Smuzhiyun STA_TX_ADDBA_DONE,
259*4882a593Smuzhiyun STA_TX_DELBA,
260*4882a593Smuzhiyun STA_RX_ADDBA_DONE,
261*4882a593Smuzhiyun STA_RX_DELBA
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* Send Frames Types */
265*4882a593Smuzhiyun enum cmd_frame_type {
266*4882a593Smuzhiyun TX_DOT11_MGMT,
267*4882a593Smuzhiyun RESET_MAC_REQ,
268*4882a593Smuzhiyun RADIO_CAPABILITIES,
269*4882a593Smuzhiyun BB_PROG_VALUES_REQUEST,
270*4882a593Smuzhiyun RF_PROG_VALUES_REQUEST,
271*4882a593Smuzhiyun WAKEUP_SLEEP_REQUEST,
272*4882a593Smuzhiyun SCAN_REQUEST,
273*4882a593Smuzhiyun TSF_UPDATE,
274*4882a593Smuzhiyun PEER_NOTIFY,
275*4882a593Smuzhiyun BLOCK_HW_QUEUE,
276*4882a593Smuzhiyun SET_KEY_REQ,
277*4882a593Smuzhiyun AUTO_RATE_IND,
278*4882a593Smuzhiyun BOOTUP_PARAMS_REQUEST,
279*4882a593Smuzhiyun VAP_CAPABILITIES,
280*4882a593Smuzhiyun EEPROM_READ,
281*4882a593Smuzhiyun EEPROM_WRITE,
282*4882a593Smuzhiyun GPIO_PIN_CONFIG ,
283*4882a593Smuzhiyun SET_RX_FILTER,
284*4882a593Smuzhiyun AMPDU_IND,
285*4882a593Smuzhiyun STATS_REQUEST_FRAME,
286*4882a593Smuzhiyun BB_BUF_PROG_VALUES_REQ,
287*4882a593Smuzhiyun BBP_PROG_IN_TA,
288*4882a593Smuzhiyun BG_SCAN_PARAMS,
289*4882a593Smuzhiyun BG_SCAN_PROBE_REQ,
290*4882a593Smuzhiyun CW_MODE_REQ,
291*4882a593Smuzhiyun PER_CMD_PKT,
292*4882a593Smuzhiyun ANT_SEL_FRAME = 0x20,
293*4882a593Smuzhiyun VAP_DYNAMIC_UPDATE = 0x27,
294*4882a593Smuzhiyun COMMON_DEV_CONFIG = 0x28,
295*4882a593Smuzhiyun RADIO_PARAMS_UPDATE = 0x29,
296*4882a593Smuzhiyun WOWLAN_CONFIG_PARAMS = 0x2B,
297*4882a593Smuzhiyun FEATURES_ENABLE = 0x33,
298*4882a593Smuzhiyun WOWLAN_WAKEUP_REASON = 0xc5
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun struct rsi_mac_frame {
302*4882a593Smuzhiyun __le16 desc_word[8];
303*4882a593Smuzhiyun } __packed;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #define PWR_SAVE_WAKEUP_IND BIT(0)
306*4882a593Smuzhiyun #define TCP_CHECK_SUM_OFFLOAD BIT(1)
307*4882a593Smuzhiyun #define CONFIRM_REQUIRED_TO_HOST BIT(2)
308*4882a593Smuzhiyun #define ADD_DELTA_TSF BIT(3)
309*4882a593Smuzhiyun #define FETCH_RETRY_CNT_FROM_HOST_DESC BIT(4)
310*4882a593Smuzhiyun #define EOSP_INDICATION BIT(5)
311*4882a593Smuzhiyun #define REQUIRE_TSF_SYNC_CONFIRM BIT(6)
312*4882a593Smuzhiyun #define ENCAP_MGMT_PKT BIT(7)
313*4882a593Smuzhiyun #define DESC_IMMEDIATE_WAKEUP BIT(15)
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun struct rsi_xtended_desc {
316*4882a593Smuzhiyun u8 confirm_frame_type;
317*4882a593Smuzhiyun u8 retry_cnt;
318*4882a593Smuzhiyun u16 reserved;
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 {
322*4882a593Smuzhiyun __le16 len_qno;
323*4882a593Smuzhiyun u8 frame_type;
324*4882a593Smuzhiyun u8 misc_flags;
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 {
328*4882a593Smuzhiyun u8 xtend_desc_size;
329*4882a593Smuzhiyun u8 reserved1;
330*4882a593Smuzhiyun __le16 reserved2;
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun struct rsi_cmd_desc_dword2 {
334*4882a593Smuzhiyun __le32 pkt_info; /* Packet specific data */
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun struct rsi_cmd_desc_dword3 {
338*4882a593Smuzhiyun __le16 token;
339*4882a593Smuzhiyun u8 qid_tid;
340*4882a593Smuzhiyun u8 sta_id;
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun struct rsi_cmd_desc {
344*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
345*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 desc_dword1;
346*4882a593Smuzhiyun struct rsi_cmd_desc_dword2 desc_dword2;
347*4882a593Smuzhiyun struct rsi_cmd_desc_dword3 desc_dword3;
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun struct rsi_boot_params {
351*4882a593Smuzhiyun __le16 desc_word[8];
352*4882a593Smuzhiyun struct bootup_params bootup_params;
353*4882a593Smuzhiyun } __packed;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun struct rsi_boot_params_9116 {
356*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
357*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 desc_dword1;
358*4882a593Smuzhiyun struct rsi_cmd_desc_dword2 desc_dword2;
359*4882a593Smuzhiyun __le16 reserved;
360*4882a593Smuzhiyun __le16 umac_clk;
361*4882a593Smuzhiyun struct bootup_params_9116 bootup_params;
362*4882a593Smuzhiyun } __packed;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun struct rsi_peer_notify {
365*4882a593Smuzhiyun struct rsi_cmd_desc desc;
366*4882a593Smuzhiyun u8 mac_addr[6];
367*4882a593Smuzhiyun __le16 command;
368*4882a593Smuzhiyun __le16 mpdu_density;
369*4882a593Smuzhiyun __le16 reserved;
370*4882a593Smuzhiyun __le32 sta_flags;
371*4882a593Smuzhiyun } __packed;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun /* Aggregation params flags */
374*4882a593Smuzhiyun #define RSI_AGGR_PARAMS_TID_MASK 0xf
375*4882a593Smuzhiyun #define RSI_AGGR_PARAMS_START BIT(4)
376*4882a593Smuzhiyun #define RSI_AGGR_PARAMS_RX_AGGR BIT(5)
377*4882a593Smuzhiyun struct rsi_aggr_params {
378*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
379*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword1;
380*4882a593Smuzhiyun __le16 seq_start;
381*4882a593Smuzhiyun __le16 baw_size;
382*4882a593Smuzhiyun __le16 token;
383*4882a593Smuzhiyun u8 aggr_params;
384*4882a593Smuzhiyun u8 peer_id;
385*4882a593Smuzhiyun } __packed;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun struct rsi_bb_rf_prog {
388*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
389*4882a593Smuzhiyun __le16 reserved1;
390*4882a593Smuzhiyun u8 rf_power_mode;
391*4882a593Smuzhiyun u8 reserved2;
392*4882a593Smuzhiyun u8 endpoint;
393*4882a593Smuzhiyun u8 reserved3;
394*4882a593Smuzhiyun __le16 reserved4;
395*4882a593Smuzhiyun __le16 reserved5;
396*4882a593Smuzhiyun __le16 flags;
397*4882a593Smuzhiyun } __packed;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun struct rsi_chan_config {
400*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
401*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 desc_dword1;
402*4882a593Smuzhiyun u8 channel_number;
403*4882a593Smuzhiyun u8 antenna_gain_offset_2g;
404*4882a593Smuzhiyun u8 antenna_gain_offset_5g;
405*4882a593Smuzhiyun u8 channel_width;
406*4882a593Smuzhiyun __le16 tx_power;
407*4882a593Smuzhiyun u8 region_rftype;
408*4882a593Smuzhiyun u8 flags;
409*4882a593Smuzhiyun } __packed;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun struct rsi_vap_caps {
412*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
413*4882a593Smuzhiyun u8 reserved1;
414*4882a593Smuzhiyun u8 status;
415*4882a593Smuzhiyun __le16 reserved2;
416*4882a593Smuzhiyun u8 vif_type;
417*4882a593Smuzhiyun u8 channel_bw;
418*4882a593Smuzhiyun __le16 antenna_info;
419*4882a593Smuzhiyun __le16 token;
420*4882a593Smuzhiyun u8 radioid_macid;
421*4882a593Smuzhiyun u8 vap_id;
422*4882a593Smuzhiyun u8 mac_addr[6];
423*4882a593Smuzhiyun __le16 keep_alive_period;
424*4882a593Smuzhiyun u8 bssid[6];
425*4882a593Smuzhiyun __le16 reserved4;
426*4882a593Smuzhiyun __le32 flags;
427*4882a593Smuzhiyun __le16 frag_threshold;
428*4882a593Smuzhiyun __le16 rts_threshold;
429*4882a593Smuzhiyun __le32 default_mgmt_rate;
430*4882a593Smuzhiyun __le16 default_ctrl_rate;
431*4882a593Smuzhiyun __le16 ctrl_rate_flags;
432*4882a593Smuzhiyun __le32 default_data_rate;
433*4882a593Smuzhiyun __le16 beacon_interval;
434*4882a593Smuzhiyun __le16 dtim_period;
435*4882a593Smuzhiyun __le16 beacon_miss_threshold;
436*4882a593Smuzhiyun } __packed;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun struct rsi_ant_sel_frame {
439*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
440*4882a593Smuzhiyun u8 reserved;
441*4882a593Smuzhiyun u8 sub_frame_type;
442*4882a593Smuzhiyun __le16 ant_value;
443*4882a593Smuzhiyun __le32 reserved1;
444*4882a593Smuzhiyun __le32 reserved2;
445*4882a593Smuzhiyun } __packed;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun struct rsi_dynamic_s {
448*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
449*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 desc_dword1;
450*4882a593Smuzhiyun struct rsi_cmd_desc_dword2 desc_dword2;
451*4882a593Smuzhiyun struct rsi_cmd_desc_dword3 desc_dword3;
452*4882a593Smuzhiyun struct framebody {
453*4882a593Smuzhiyun __le16 data_rate;
454*4882a593Smuzhiyun __le16 mgmt_rate;
455*4882a593Smuzhiyun __le16 keep_alive_period;
456*4882a593Smuzhiyun } frame_body;
457*4882a593Smuzhiyun } __packed;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /* Key descriptor flags */
460*4882a593Smuzhiyun #define RSI_KEY_TYPE_BROADCAST BIT(1)
461*4882a593Smuzhiyun #define RSI_WEP_KEY BIT(2)
462*4882a593Smuzhiyun #define RSI_WEP_KEY_104 BIT(3)
463*4882a593Smuzhiyun #define RSI_CIPHER_WPA BIT(4)
464*4882a593Smuzhiyun #define RSI_CIPHER_TKIP BIT(5)
465*4882a593Smuzhiyun #define RSI_KEY_MODE_AP BIT(7)
466*4882a593Smuzhiyun #define RSI_PROTECT_DATA_FRAMES BIT(13)
467*4882a593Smuzhiyun #define RSI_KEY_ID_MASK 0xC0
468*4882a593Smuzhiyun #define RSI_KEY_ID_OFFSET 14
469*4882a593Smuzhiyun struct rsi_set_key {
470*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
471*4882a593Smuzhiyun struct rsi_cmd_desc_dword1 desc_dword1;
472*4882a593Smuzhiyun __le16 key_desc;
473*4882a593Smuzhiyun __le32 bpn;
474*4882a593Smuzhiyun u8 sta_id;
475*4882a593Smuzhiyun u8 vap_id;
476*4882a593Smuzhiyun u8 key[4][32];
477*4882a593Smuzhiyun u8 tx_mic_key[8];
478*4882a593Smuzhiyun u8 rx_mic_key[8];
479*4882a593Smuzhiyun } __packed;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun struct rsi_auto_rate {
482*4882a593Smuzhiyun struct rsi_cmd_desc desc;
483*4882a593Smuzhiyun __le16 failure_limit;
484*4882a593Smuzhiyun __le16 initial_boundary;
485*4882a593Smuzhiyun __le16 max_threshold_limt;
486*4882a593Smuzhiyun __le16 num_supported_rates;
487*4882a593Smuzhiyun __le16 aarf_rssi;
488*4882a593Smuzhiyun __le16 moderate_rate_inx;
489*4882a593Smuzhiyun __le16 collision_tolerance;
490*4882a593Smuzhiyun __le16 supported_rates[40];
491*4882a593Smuzhiyun } __packed;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun #define QUIET_INFO_VALID BIT(0)
494*4882a593Smuzhiyun #define QUIET_ENABLE BIT(1)
495*4882a593Smuzhiyun struct rsi_block_unblock_data {
496*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
497*4882a593Smuzhiyun u8 xtend_desc_size;
498*4882a593Smuzhiyun u8 host_quiet_info;
499*4882a593Smuzhiyun __le16 reserved;
500*4882a593Smuzhiyun __le16 block_q_bitmap;
501*4882a593Smuzhiyun __le16 unblock_q_bitmap;
502*4882a593Smuzhiyun __le16 token;
503*4882a593Smuzhiyun __le16 flush_q_bitmap;
504*4882a593Smuzhiyun } __packed;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun struct qos_params {
507*4882a593Smuzhiyun __le16 cont_win_min_q;
508*4882a593Smuzhiyun __le16 cont_win_max_q;
509*4882a593Smuzhiyun __le16 aifsn_val_q;
510*4882a593Smuzhiyun __le16 txop_q;
511*4882a593Smuzhiyun } __packed;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun struct rsi_radio_caps {
514*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
515*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword1;
516*4882a593Smuzhiyun u8 channel_num;
517*4882a593Smuzhiyun u8 rf_model;
518*4882a593Smuzhiyun __le16 ppe_ack_rate;
519*4882a593Smuzhiyun __le16 mode_11j;
520*4882a593Smuzhiyun u8 radio_cfg_info;
521*4882a593Smuzhiyun u8 radio_info;
522*4882a593Smuzhiyun struct qos_params qos_params[MAX_HW_QUEUES];
523*4882a593Smuzhiyun u8 num_11n_rates;
524*4882a593Smuzhiyun u8 num_11ac_rates;
525*4882a593Smuzhiyun __le16 gcpd_per_rate[20];
526*4882a593Smuzhiyun __le16 sifs_tx_11n;
527*4882a593Smuzhiyun __le16 sifs_tx_11b;
528*4882a593Smuzhiyun __le16 slot_rx_11n;
529*4882a593Smuzhiyun __le16 ofdm_ack_tout;
530*4882a593Smuzhiyun __le16 cck_ack_tout;
531*4882a593Smuzhiyun __le16 preamble_type;
532*4882a593Smuzhiyun } __packed;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* ULP GPIO flags */
535*4882a593Smuzhiyun #define RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP BIT(0)
536*4882a593Smuzhiyun #define RSI_GPIO_SLEEP_IND_FROM_DEVICE BIT(1)
537*4882a593Smuzhiyun #define RSI_GPIO_2_ULP BIT(2)
538*4882a593Smuzhiyun #define RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP BIT(3)
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun /* SOC GPIO flags */
541*4882a593Smuzhiyun #define RSI_GPIO_0_PSPI_CSN_0 BIT(0)
542*4882a593Smuzhiyun #define RSI_GPIO_1_PSPI_CSN_1 BIT(1)
543*4882a593Smuzhiyun #define RSI_GPIO_2_HOST_WAKEUP_INTR BIT(2)
544*4882a593Smuzhiyun #define RSI_GPIO_3_PSPI_DATA_0 BIT(3)
545*4882a593Smuzhiyun #define RSI_GPIO_4_PSPI_DATA_1 BIT(4)
546*4882a593Smuzhiyun #define RSI_GPIO_5_PSPI_DATA_2 BIT(5)
547*4882a593Smuzhiyun #define RSI_GPIO_6_PSPI_DATA_3 BIT(6)
548*4882a593Smuzhiyun #define RSI_GPIO_7_I2C_SCL BIT(7)
549*4882a593Smuzhiyun #define RSI_GPIO_8_I2C_SDA BIT(8)
550*4882a593Smuzhiyun #define RSI_GPIO_9_UART1_RX BIT(9)
551*4882a593Smuzhiyun #define RSI_GPIO_10_UART1_TX BIT(10)
552*4882a593Smuzhiyun #define RSI_GPIO_11_UART1_RTS_I2S_CLK BIT(11)
553*4882a593Smuzhiyun #define RSI_GPIO_12_UART1_CTS_I2S_WS BIT(12)
554*4882a593Smuzhiyun #define RSI_GPIO_13_DBG_UART_RX_I2S_DIN BIT(13)
555*4882a593Smuzhiyun #define RSI_GPIO_14_DBG_UART_RX_I2S_DOUT BIT(14)
556*4882a593Smuzhiyun #define RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS BIT(15)
557*4882a593Smuzhiyun #define RSI_GPIO_16_LED_0 BIT(16)
558*4882a593Smuzhiyun #define RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL BIT(17)
559*4882a593Smuzhiyun #define RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL BIT(18)
560*4882a593Smuzhiyun #define RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF BIT(19)
561*4882a593Smuzhiyun #define RSI_GPIO_20_RF_RESET BIT(20)
562*4882a593Smuzhiyun #define RSI_GPIO_21_SLEEP_IND_FROM_DEVICE BIT(21)
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun #define RSI_UNUSED_SOC_GPIO_BITMAP (RSI_GPIO_9_UART1_RX | \
565*4882a593Smuzhiyun RSI_GPIO_10_UART1_TX | \
566*4882a593Smuzhiyun RSI_GPIO_11_UART1_RTS_I2S_CLK | \
567*4882a593Smuzhiyun RSI_GPIO_12_UART1_CTS_I2S_WS | \
568*4882a593Smuzhiyun RSI_GPIO_13_DBG_UART_RX_I2S_DIN | \
569*4882a593Smuzhiyun RSI_GPIO_14_DBG_UART_RX_I2S_DOUT | \
570*4882a593Smuzhiyun RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS | \
571*4882a593Smuzhiyun RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL | \
572*4882a593Smuzhiyun RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL | \
573*4882a593Smuzhiyun RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF | \
574*4882a593Smuzhiyun RSI_GPIO_21_SLEEP_IND_FROM_DEVICE)
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun #define RSI_UNUSED_ULP_GPIO_BITMAP (RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP | \
577*4882a593Smuzhiyun RSI_GPIO_SLEEP_IND_FROM_DEVICE | \
578*4882a593Smuzhiyun RSI_GPIO_2_ULP | \
579*4882a593Smuzhiyun RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP);
580*4882a593Smuzhiyun struct rsi_config_vals {
581*4882a593Smuzhiyun __le16 len_qno;
582*4882a593Smuzhiyun u8 pkt_type;
583*4882a593Smuzhiyun u8 misc_flags;
584*4882a593Smuzhiyun __le16 reserved1[6];
585*4882a593Smuzhiyun u8 lp_ps_handshake;
586*4882a593Smuzhiyun u8 ulp_ps_handshake;
587*4882a593Smuzhiyun u8 sleep_config_params; /* 0 for no handshake,
588*4882a593Smuzhiyun * 1 for GPIO based handshake,
589*4882a593Smuzhiyun * 2 packet handshake
590*4882a593Smuzhiyun */
591*4882a593Smuzhiyun u8 unused_ulp_gpio;
592*4882a593Smuzhiyun __le32 unused_soc_gpio_bitmap;
593*4882a593Smuzhiyun u8 ext_pa_or_bt_coex_en;
594*4882a593Smuzhiyun u8 opermode;
595*4882a593Smuzhiyun u8 wlan_rf_pwr_mode;
596*4882a593Smuzhiyun u8 bt_rf_pwr_mode;
597*4882a593Smuzhiyun u8 zigbee_rf_pwr_mode;
598*4882a593Smuzhiyun u8 driver_mode;
599*4882a593Smuzhiyun u8 region_code;
600*4882a593Smuzhiyun u8 antenna_sel_val;
601*4882a593Smuzhiyun u8 reserved2[16];
602*4882a593Smuzhiyun } __packed;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun /* Packet info flags */
605*4882a593Smuzhiyun #define RSI_EEPROM_HDR_SIZE_OFFSET 8
606*4882a593Smuzhiyun #define RSI_EEPROM_HDR_SIZE_MASK 0x300
607*4882a593Smuzhiyun #define RSI_EEPROM_LEN_OFFSET 20
608*4882a593Smuzhiyun #define RSI_EEPROM_LEN_MASK 0xFFF00000
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun struct rsi_eeprom_read_frame {
611*4882a593Smuzhiyun __le16 len_qno;
612*4882a593Smuzhiyun u8 pkt_type;
613*4882a593Smuzhiyun u8 misc_flags;
614*4882a593Smuzhiyun __le32 pkt_info;
615*4882a593Smuzhiyun __le32 eeprom_offset;
616*4882a593Smuzhiyun __le16 delay_ms;
617*4882a593Smuzhiyun __le16 reserved3;
618*4882a593Smuzhiyun } __packed;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun struct rsi_request_ps {
621*4882a593Smuzhiyun struct rsi_cmd_desc desc;
622*4882a593Smuzhiyun struct ps_sleep_params ps_sleep;
623*4882a593Smuzhiyun u8 ps_mimic_support;
624*4882a593Smuzhiyun u8 ps_uapsd_acs;
625*4882a593Smuzhiyun u8 ps_uapsd_wakeup_period;
626*4882a593Smuzhiyun u8 reserved;
627*4882a593Smuzhiyun __le32 ps_listen_interval;
628*4882a593Smuzhiyun __le32 ps_dtim_interval_duration;
629*4882a593Smuzhiyun __le16 ps_num_dtim_intervals;
630*4882a593Smuzhiyun } __packed;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun struct rsi_wowlan_req {
633*4882a593Smuzhiyun struct rsi_cmd_desc desc;
634*4882a593Smuzhiyun u8 sourceid[ETH_ALEN];
635*4882a593Smuzhiyun u16 wow_flags;
636*4882a593Smuzhiyun u16 host_sleep_status;
637*4882a593Smuzhiyun } __packed;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun #define RSI_START_BGSCAN 1
640*4882a593Smuzhiyun #define RSI_STOP_BGSCAN 0
641*4882a593Smuzhiyun #define HOST_BG_SCAN_TRIG BIT(4)
642*4882a593Smuzhiyun struct rsi_bgscan_config {
643*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
644*4882a593Smuzhiyun __le64 reserved;
645*4882a593Smuzhiyun __le32 reserved1;
646*4882a593Smuzhiyun __le16 bgscan_threshold;
647*4882a593Smuzhiyun __le16 roam_threshold;
648*4882a593Smuzhiyun __le16 bgscan_periodicity;
649*4882a593Smuzhiyun u8 num_bgscan_channels;
650*4882a593Smuzhiyun u8 two_probe;
651*4882a593Smuzhiyun __le16 active_scan_duration;
652*4882a593Smuzhiyun __le16 passive_scan_duration;
653*4882a593Smuzhiyun __le16 channels2scan[MAX_BGSCAN_CHANNELS_DUAL_BAND];
654*4882a593Smuzhiyun } __packed;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun struct rsi_bgscan_probe {
657*4882a593Smuzhiyun struct rsi_cmd_desc_dword0 desc_dword0;
658*4882a593Smuzhiyun __le64 reserved;
659*4882a593Smuzhiyun __le32 reserved1;
660*4882a593Smuzhiyun __le16 mgmt_rate;
661*4882a593Smuzhiyun __le16 flags;
662*4882a593Smuzhiyun __le16 def_chan;
663*4882a593Smuzhiyun __le16 channel_scan_time;
664*4882a593Smuzhiyun __le16 probe_req_length;
665*4882a593Smuzhiyun } __packed;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun #define RSI_DUTY_CYCLING BIT(0)
668*4882a593Smuzhiyun #define RSI_END_OF_FRAME BIT(1)
669*4882a593Smuzhiyun #define RSI_SIFS_TX_ENABLE BIT(2)
670*4882a593Smuzhiyun #define RSI_DPD BIT(3)
671*4882a593Smuzhiyun struct rsi_wlan_9116_features {
672*4882a593Smuzhiyun struct rsi_cmd_desc desc;
673*4882a593Smuzhiyun u8 pll_mode;
674*4882a593Smuzhiyun u8 rf_type;
675*4882a593Smuzhiyun u8 wireless_mode;
676*4882a593Smuzhiyun u8 enable_ppe;
677*4882a593Smuzhiyun u8 afe_type;
678*4882a593Smuzhiyun u8 reserved1;
679*4882a593Smuzhiyun __le16 reserved2;
680*4882a593Smuzhiyun __le32 feature_enable;
681*4882a593Smuzhiyun };
682*4882a593Smuzhiyun
rsi_get_queueno(u8 * addr,u16 offset)683*4882a593Smuzhiyun static inline u32 rsi_get_queueno(u8 *addr, u16 offset)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun return (le16_to_cpu(*(__le16 *)&addr[offset]) & 0x7000) >> 12;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
rsi_get_length(u8 * addr,u16 offset)688*4882a593Smuzhiyun static inline u32 rsi_get_length(u8 *addr, u16 offset)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun return (le16_to_cpu(*(__le16 *)&addr[offset])) & 0x0fff;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
rsi_get_extended_desc(u8 * addr,u16 offset)693*4882a593Smuzhiyun static inline u8 rsi_get_extended_desc(u8 *addr, u16 offset)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun return le16_to_cpu(*((__le16 *)&addr[offset + 4])) & 0x00ff;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
rsi_get_rssi(u8 * addr)698*4882a593Smuzhiyun static inline u8 rsi_get_rssi(u8 *addr)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun return *(u8 *)(addr + FRAME_DESC_SZ);
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
rsi_get_channel(u8 * addr)703*4882a593Smuzhiyun static inline u8 rsi_get_channel(u8 *addr)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun return *(char *)(addr + 15);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
rsi_set_len_qno(__le16 * addr,u16 len,u8 qno)708*4882a593Smuzhiyun static inline void rsi_set_len_qno(__le16 *addr, u16 len, u8 qno)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun *addr = cpu_to_le16(len | ((qno & 7) << 12));
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun int rsi_handle_card_ready(struct rsi_common *common, u8 *msg);
714*4882a593Smuzhiyun int rsi_mgmt_pkt_recv(struct rsi_common *common, u8 *msg);
715*4882a593Smuzhiyun int rsi_set_vap_capabilities(struct rsi_common *common, enum opmode mode,
716*4882a593Smuzhiyun u8 *mac_addr, u8 vap_id, u8 vap_status);
717*4882a593Smuzhiyun int rsi_send_aggregation_params_frame(struct rsi_common *common, u16 tid,
718*4882a593Smuzhiyun u16 ssn, u8 buf_size, u8 event,
719*4882a593Smuzhiyun u8 sta_id);
720*4882a593Smuzhiyun int rsi_hal_load_key(struct rsi_common *common, u8 *data, u16 key_len,
721*4882a593Smuzhiyun u8 key_type, u8 key_id, u32 cipher, s16 sta_id,
722*4882a593Smuzhiyun struct ieee80211_vif *vif);
723*4882a593Smuzhiyun int rsi_set_channel(struct rsi_common *common,
724*4882a593Smuzhiyun struct ieee80211_channel *channel);
725*4882a593Smuzhiyun int rsi_send_vap_dynamic_update(struct rsi_common *common);
726*4882a593Smuzhiyun int rsi_send_block_unblock_frame(struct rsi_common *common, bool event);
727*4882a593Smuzhiyun int rsi_hal_send_sta_notify_frame(struct rsi_common *common, enum opmode opmode,
728*4882a593Smuzhiyun u8 notify_event, const unsigned char *bssid,
729*4882a593Smuzhiyun u8 qos_enable, u16 aid, u16 sta_id,
730*4882a593Smuzhiyun struct ieee80211_vif *vif);
731*4882a593Smuzhiyun void rsi_inform_bss_status(struct rsi_common *common, enum opmode opmode,
732*4882a593Smuzhiyun u8 status, const u8 *addr, u8 qos_enable, u16 aid,
733*4882a593Smuzhiyun struct ieee80211_sta *sta, u16 sta_id,
734*4882a593Smuzhiyun u16 assoc_cap, struct ieee80211_vif *vif);
735*4882a593Smuzhiyun void rsi_indicate_pkt_to_os(struct rsi_common *common, struct sk_buff *skb);
736*4882a593Smuzhiyun int rsi_mac80211_attach(struct rsi_common *common);
737*4882a593Smuzhiyun void rsi_indicate_tx_status(struct rsi_hw *common, struct sk_buff *skb,
738*4882a593Smuzhiyun int status);
739*4882a593Smuzhiyun bool rsi_is_cipher_wep(struct rsi_common *common);
740*4882a593Smuzhiyun void rsi_core_qos_processor(struct rsi_common *common);
741*4882a593Smuzhiyun void rsi_core_xmit(struct rsi_common *common, struct sk_buff *skb);
742*4882a593Smuzhiyun int rsi_send_mgmt_pkt(struct rsi_common *common, struct sk_buff *skb);
743*4882a593Smuzhiyun int rsi_send_data_pkt(struct rsi_common *common, struct sk_buff *skb);
744*4882a593Smuzhiyun int rsi_band_check(struct rsi_common *common, struct ieee80211_channel *chan);
745*4882a593Smuzhiyun int rsi_send_rx_filter_frame(struct rsi_common *common, u16 rx_filter_word);
746*4882a593Smuzhiyun int rsi_send_radio_params_update(struct rsi_common *common);
747*4882a593Smuzhiyun int rsi_set_antenna(struct rsi_common *common, u8 antenna);
748*4882a593Smuzhiyun #ifdef CONFIG_PM
749*4882a593Smuzhiyun int rsi_send_wowlan_request(struct rsi_common *common, u16 flags,
750*4882a593Smuzhiyun u16 sleep_status);
751*4882a593Smuzhiyun #endif
752*4882a593Smuzhiyun int rsi_send_ps_request(struct rsi_hw *adapter, bool enable,
753*4882a593Smuzhiyun struct ieee80211_vif *vif);
754*4882a593Smuzhiyun void init_bgscan_params(struct rsi_common *common);
755*4882a593Smuzhiyun int rsi_send_bgscan_params(struct rsi_common *common, int enable);
756*4882a593Smuzhiyun int rsi_send_bgscan_probe_req(struct rsi_common *common,
757*4882a593Smuzhiyun struct ieee80211_vif *vif);
758*4882a593Smuzhiyun #endif
759