1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright (c) 2014 Redpine Signals Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __RSI_MAIN_H__ 18*4882a593Smuzhiyun #define __RSI_MAIN_H__ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/string.h> 21*4882a593Smuzhiyun #include <linux/skbuff.h> 22*4882a593Smuzhiyun #include <net/mac80211.h> 23*4882a593Smuzhiyun #include <net/rsi_91x.h> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct rsi_sta { 26*4882a593Smuzhiyun struct ieee80211_sta *sta; 27*4882a593Smuzhiyun s16 sta_id; 28*4882a593Smuzhiyun u16 seq_start[IEEE80211_NUM_TIDS]; 29*4882a593Smuzhiyun bool start_tx_aggr[IEEE80211_NUM_TIDS]; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct rsi_hw; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #include "rsi_ps.h" 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ERR_ZONE BIT(0) /* For Error Msgs */ 37*4882a593Smuzhiyun #define INFO_ZONE BIT(1) /* For General Status Msgs */ 38*4882a593Smuzhiyun #define INIT_ZONE BIT(2) /* For Driver Init Seq Msgs */ 39*4882a593Smuzhiyun #define MGMT_TX_ZONE BIT(3) /* For TX Mgmt Path Msgs */ 40*4882a593Smuzhiyun #define MGMT_RX_ZONE BIT(4) /* For RX Mgmt Path Msgs */ 41*4882a593Smuzhiyun #define DATA_TX_ZONE BIT(5) /* For TX Data Path Msgs */ 42*4882a593Smuzhiyun #define DATA_RX_ZONE BIT(6) /* For RX Data Path Msgs */ 43*4882a593Smuzhiyun #define FSM_ZONE BIT(7) /* For State Machine Msgs */ 44*4882a593Smuzhiyun #define ISR_ZONE BIT(8) /* For Interrupt Msgs */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun enum RSI_FSM_STATES { 47*4882a593Smuzhiyun FSM_FW_NOT_LOADED, 48*4882a593Smuzhiyun FSM_CARD_NOT_READY, 49*4882a593Smuzhiyun FSM_COMMON_DEV_PARAMS_SENT, 50*4882a593Smuzhiyun FSM_BOOT_PARAMS_SENT, 51*4882a593Smuzhiyun FSM_EEPROM_READ_MAC_ADDR, 52*4882a593Smuzhiyun FSM_EEPROM_READ_RF_TYPE, 53*4882a593Smuzhiyun FSM_RESET_MAC_SENT, 54*4882a593Smuzhiyun FSM_RADIO_CAPS_SENT, 55*4882a593Smuzhiyun FSM_BB_RF_PROG_SENT, 56*4882a593Smuzhiyun FSM_MAC_INIT_DONE, 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun NUM_FSM_STATES 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun extern u32 rsi_zone_enabled; 62*4882a593Smuzhiyun extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define RSI_MAX_BANDS 2 65*4882a593Smuzhiyun #define RSI_MAX_VIFS 3 66*4882a593Smuzhiyun #define NUM_EDCA_QUEUES 4 67*4882a593Smuzhiyun #define IEEE80211_ADDR_LEN 6 68*4882a593Smuzhiyun #define FRAME_DESC_SZ 16 69*4882a593Smuzhiyun #define MIN_802_11_HDR_LEN 24 70*4882a593Smuzhiyun #define RSI_DEF_KEEPALIVE 90 71*4882a593Smuzhiyun #define RSI_WOW_KEEPALIVE 5 72*4882a593Smuzhiyun #define RSI_BCN_MISS_THRESHOLD 24 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define DATA_QUEUE_WATER_MARK 400 75*4882a593Smuzhiyun #define MIN_DATA_QUEUE_WATER_MARK 300 76*4882a593Smuzhiyun #define MULTICAST_WATER_MARK 200 77*4882a593Smuzhiyun #define MAC_80211_HDR_FRAME_CONTROL 0 78*4882a593Smuzhiyun #define WME_NUM_AC 4 79*4882a593Smuzhiyun #define NUM_SOFT_QUEUES 6 80*4882a593Smuzhiyun #define MAX_HW_QUEUES 12 81*4882a593Smuzhiyun #define INVALID_QUEUE 0xff 82*4882a593Smuzhiyun #define MAX_CONTINUOUS_VO_PKTS 8 83*4882a593Smuzhiyun #define MAX_CONTINUOUS_VI_PKTS 4 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Hardware queue info */ 86*4882a593Smuzhiyun #define BROADCAST_HW_Q 9 87*4882a593Smuzhiyun #define MGMT_HW_Q 10 88*4882a593Smuzhiyun #define BEACON_HW_Q 11 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define IEEE80211_MGMT_FRAME 0x00 91*4882a593Smuzhiyun #define IEEE80211_CTL_FRAME 0x04 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RSI_MAX_ASSOC_STAS 32 94*4882a593Smuzhiyun #define IEEE80211_QOS_TID 0x0f 95*4882a593Smuzhiyun #define IEEE80211_NONQOS_TID 16 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MAX_DEBUGFS_ENTRIES 4 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define TID_TO_WME_AC(_tid) ( \ 100*4882a593Smuzhiyun ((_tid) == 0 || (_tid) == 3) ? BE_Q : \ 101*4882a593Smuzhiyun ((_tid) < 3) ? BK_Q : \ 102*4882a593Smuzhiyun ((_tid) < 6) ? VI_Q : \ 103*4882a593Smuzhiyun VO_Q) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define WME_AC(_q) ( \ 106*4882a593Smuzhiyun ((_q) == BK_Q) ? IEEE80211_AC_BK : \ 107*4882a593Smuzhiyun ((_q) == BE_Q) ? IEEE80211_AC_BE : \ 108*4882a593Smuzhiyun ((_q) == VI_Q) ? IEEE80211_AC_VI : \ 109*4882a593Smuzhiyun IEEE80211_AC_VO) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* WoWLAN flags */ 112*4882a593Smuzhiyun #define RSI_WOW_ENABLED BIT(0) 113*4882a593Smuzhiyun #define RSI_WOW_NO_CONNECTION BIT(1) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define RSI_MAX_RX_PKTS 64 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun enum rsi_dev_model { 118*4882a593Smuzhiyun RSI_DEV_9113 = 0, 119*4882a593Smuzhiyun RSI_DEV_9116 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun struct version_info { 123*4882a593Smuzhiyun u16 major; 124*4882a593Smuzhiyun u16 minor; 125*4882a593Smuzhiyun u8 release_num; 126*4882a593Smuzhiyun u8 patch_num; 127*4882a593Smuzhiyun union { 128*4882a593Smuzhiyun struct { 129*4882a593Smuzhiyun u8 fw_ver[8]; 130*4882a593Smuzhiyun } info; 131*4882a593Smuzhiyun } ver; 132*4882a593Smuzhiyun } __packed; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct skb_info { 135*4882a593Smuzhiyun s8 rssi; 136*4882a593Smuzhiyun u32 flags; 137*4882a593Smuzhiyun u16 channel; 138*4882a593Smuzhiyun s8 tid; 139*4882a593Smuzhiyun s8 sta_id; 140*4882a593Smuzhiyun u8 internal_hdr_size; 141*4882a593Smuzhiyun struct ieee80211_vif *vif; 142*4882a593Smuzhiyun u8 vap_id; 143*4882a593Smuzhiyun bool have_key; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun enum edca_queue { 147*4882a593Smuzhiyun BK_Q, 148*4882a593Smuzhiyun BE_Q, 149*4882a593Smuzhiyun VI_Q, 150*4882a593Smuzhiyun VO_Q, 151*4882a593Smuzhiyun MGMT_SOFT_Q, 152*4882a593Smuzhiyun MGMT_BEACON_Q 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun struct security_info { 156*4882a593Smuzhiyun u32 ptk_cipher; 157*4882a593Smuzhiyun u32 gtk_cipher; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun struct wmm_qinfo { 161*4882a593Smuzhiyun s32 weight; 162*4882a593Smuzhiyun s32 wme_params; 163*4882a593Smuzhiyun s32 pkt_contended; 164*4882a593Smuzhiyun s32 txop; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun struct transmit_q_stats { 168*4882a593Smuzhiyun u32 total_tx_pkt_send[NUM_EDCA_QUEUES + 2]; 169*4882a593Smuzhiyun u32 total_tx_pkt_freed[NUM_EDCA_QUEUES + 2]; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define MAX_BGSCAN_CHANNELS_DUAL_BAND 38 173*4882a593Smuzhiyun #define MAX_BGSCAN_PROBE_REQ_LEN 0x64 174*4882a593Smuzhiyun #define RSI_DEF_BGSCAN_THRLD 0x0 175*4882a593Smuzhiyun #define RSI_DEF_ROAM_THRLD 0xa 176*4882a593Smuzhiyun #define RSI_BGSCAN_PERIODICITY 0x1e 177*4882a593Smuzhiyun #define RSI_ACTIVE_SCAN_TIME 0x14 178*4882a593Smuzhiyun #define RSI_PASSIVE_SCAN_TIME 0x46 179*4882a593Smuzhiyun #define RSI_CHANNEL_SCAN_TIME 20 180*4882a593Smuzhiyun struct rsi_bgscan_params { 181*4882a593Smuzhiyun u16 bgscan_threshold; 182*4882a593Smuzhiyun u16 roam_threshold; 183*4882a593Smuzhiyun u16 bgscan_periodicity; 184*4882a593Smuzhiyun u8 num_bgscan_channels; 185*4882a593Smuzhiyun u8 two_probe; 186*4882a593Smuzhiyun u16 active_scan_duration; 187*4882a593Smuzhiyun u16 passive_scan_duration; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun struct vif_priv { 191*4882a593Smuzhiyun bool is_ht; 192*4882a593Smuzhiyun bool sgi; 193*4882a593Smuzhiyun u16 seq_start; 194*4882a593Smuzhiyun int vap_id; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun struct rsi_event { 198*4882a593Smuzhiyun atomic_t event_condition; 199*4882a593Smuzhiyun wait_queue_head_t event_queue; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct rsi_thread { 203*4882a593Smuzhiyun void (*thread_function)(void *); 204*4882a593Smuzhiyun struct completion completion; 205*4882a593Smuzhiyun struct task_struct *task; 206*4882a593Smuzhiyun struct rsi_event event; 207*4882a593Smuzhiyun atomic_t thread_done; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun struct cqm_info { 211*4882a593Smuzhiyun s8 last_cqm_event_rssi; 212*4882a593Smuzhiyun int rssi_thold; 213*4882a593Smuzhiyun u32 rssi_hyst; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun enum rsi_dfs_regions { 217*4882a593Smuzhiyun RSI_REGION_FCC = 0, 218*4882a593Smuzhiyun RSI_REGION_ETSI, 219*4882a593Smuzhiyun RSI_REGION_TELEC, 220*4882a593Smuzhiyun RSI_REGION_WORLD 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun struct rsi_9116_features { 224*4882a593Smuzhiyun u8 pll_mode; 225*4882a593Smuzhiyun u8 rf_type; 226*4882a593Smuzhiyun u8 wireless_mode; 227*4882a593Smuzhiyun u8 afe_type; 228*4882a593Smuzhiyun u8 enable_ppe; 229*4882a593Smuzhiyun u8 dpd; 230*4882a593Smuzhiyun u32 sifs_tx_enable; 231*4882a593Smuzhiyun u32 ps_options; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun struct rsi_rate_config { 235*4882a593Smuzhiyun u32 configured_mask; /* configured by mac80211 bits 0-11=legacy 12+ mcs */ 236*4882a593Smuzhiyun u16 fixed_hw_rate; 237*4882a593Smuzhiyun bool fixed_enabled; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun struct rsi_common { 241*4882a593Smuzhiyun struct rsi_hw *priv; 242*4882a593Smuzhiyun struct vif_priv vif_info[RSI_MAX_VIFS]; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun void *coex_cb; 245*4882a593Smuzhiyun bool mgmt_q_block; 246*4882a593Smuzhiyun struct version_info lmac_ver; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun struct rsi_thread tx_thread; 249*4882a593Smuzhiyun struct sk_buff_head tx_queue[NUM_EDCA_QUEUES + 2]; 250*4882a593Smuzhiyun struct completion wlan_init_completion; 251*4882a593Smuzhiyun /* Mutex declaration */ 252*4882a593Smuzhiyun struct mutex mutex; 253*4882a593Smuzhiyun /* Mutex used for tx thread */ 254*4882a593Smuzhiyun struct mutex tx_lock; 255*4882a593Smuzhiyun /* Mutex used for rx thread */ 256*4882a593Smuzhiyun struct mutex rx_lock; 257*4882a593Smuzhiyun u8 endpoint; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* Channel/band related */ 260*4882a593Smuzhiyun u8 band; 261*4882a593Smuzhiyun u8 num_supp_bands; 262*4882a593Smuzhiyun u8 channel_width; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun u16 rts_threshold; 265*4882a593Smuzhiyun u32 bitrate_mask[RSI_MAX_BANDS]; 266*4882a593Smuzhiyun struct rsi_rate_config rate_config[RSI_MAX_BANDS]; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun u8 rf_reset; 269*4882a593Smuzhiyun struct transmit_q_stats tx_stats; 270*4882a593Smuzhiyun struct security_info secinfo; 271*4882a593Smuzhiyun struct wmm_qinfo tx_qinfo[NUM_EDCA_QUEUES]; 272*4882a593Smuzhiyun struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; 273*4882a593Smuzhiyun u8 mac_addr[IEEE80211_ADDR_LEN]; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* state related */ 276*4882a593Smuzhiyun u32 fsm_state; 277*4882a593Smuzhiyun bool init_done; 278*4882a593Smuzhiyun u8 bb_rf_prog_count; 279*4882a593Smuzhiyun bool iface_down; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* Generic */ 282*4882a593Smuzhiyun u8 channel; 283*4882a593Smuzhiyun u8 *rx_data_pkt; 284*4882a593Smuzhiyun u8 mac_id; 285*4882a593Smuzhiyun u8 radio_id; 286*4882a593Smuzhiyun u16 rate_pwr[20]; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* WMM algo related */ 289*4882a593Smuzhiyun u8 selected_qnum; 290*4882a593Smuzhiyun u32 pkt_cnt; 291*4882a593Smuzhiyun u8 min_weight; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /* bgscan related */ 294*4882a593Smuzhiyun struct cqm_info cqm_info; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun bool hw_data_qs_blocked; 297*4882a593Smuzhiyun u8 driver_mode; 298*4882a593Smuzhiyun u8 coex_mode; 299*4882a593Smuzhiyun u16 oper_mode; 300*4882a593Smuzhiyun u8 lp_ps_handshake_mode; 301*4882a593Smuzhiyun u8 ulp_ps_handshake_mode; 302*4882a593Smuzhiyun u8 uapsd_bitmap; 303*4882a593Smuzhiyun u8 rf_power_val; 304*4882a593Smuzhiyun u8 wlan_rf_power_mode; 305*4882a593Smuzhiyun u8 obm_ant_sel_val; 306*4882a593Smuzhiyun int tx_power; 307*4882a593Smuzhiyun u8 ant_in_use; 308*4882a593Smuzhiyun /* Mutex used for writing packet to bus */ 309*4882a593Smuzhiyun struct mutex tx_bus_mutex; 310*4882a593Smuzhiyun bool hibernate_resume; 311*4882a593Smuzhiyun bool reinit_hw; 312*4882a593Smuzhiyun u8 wow_flags; 313*4882a593Smuzhiyun u16 beacon_interval; 314*4882a593Smuzhiyun u8 dtim_cnt; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* AP mode parameters */ 317*4882a593Smuzhiyun u8 beacon_enabled; 318*4882a593Smuzhiyun u16 beacon_cnt; 319*4882a593Smuzhiyun struct rsi_sta stations[RSI_MAX_ASSOC_STAS + 1]; 320*4882a593Smuzhiyun int num_stations; 321*4882a593Smuzhiyun int max_stations; 322*4882a593Smuzhiyun struct ieee80211_key_conf *key; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* Wi-Fi direct mode related */ 325*4882a593Smuzhiyun bool p2p_enabled; 326*4882a593Smuzhiyun struct timer_list roc_timer; 327*4882a593Smuzhiyun struct ieee80211_vif *roc_vif; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun bool eapol4_confirm; 330*4882a593Smuzhiyun bool bt_defer_attach; 331*4882a593Smuzhiyun void *bt_adapter; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun struct cfg80211_scan_request *hwscan; 334*4882a593Smuzhiyun struct rsi_bgscan_params bgscan; 335*4882a593Smuzhiyun struct rsi_9116_features w9116_features; 336*4882a593Smuzhiyun u8 bgscan_en; 337*4882a593Smuzhiyun u8 mac_ops_resumed; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun struct eepromrw_info { 341*4882a593Smuzhiyun u32 offset; 342*4882a593Smuzhiyun u32 length; 343*4882a593Smuzhiyun u8 write; 344*4882a593Smuzhiyun u16 eeprom_erase; 345*4882a593Smuzhiyun u8 data[480]; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun struct eeprom_read { 349*4882a593Smuzhiyun u16 length; 350*4882a593Smuzhiyun u16 off_set; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun struct rsi_hw { 354*4882a593Smuzhiyun struct rsi_common *priv; 355*4882a593Smuzhiyun enum rsi_dev_model device_model; 356*4882a593Smuzhiyun struct ieee80211_hw *hw; 357*4882a593Smuzhiyun struct ieee80211_vif *vifs[RSI_MAX_VIFS]; 358*4882a593Smuzhiyun struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; 359*4882a593Smuzhiyun struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun struct device *device; 362*4882a593Smuzhiyun u8 sc_nvifs; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun enum rsi_host_intf rsi_host_intf; 365*4882a593Smuzhiyun u16 block_size; 366*4882a593Smuzhiyun enum ps_state ps_state; 367*4882a593Smuzhiyun struct rsi_ps_info ps_info; 368*4882a593Smuzhiyun spinlock_t ps_lock; /*To protect power save config*/ 369*4882a593Smuzhiyun u32 usb_buffer_status_reg; 370*4882a593Smuzhiyun #ifdef CONFIG_RSI_DEBUGFS 371*4882a593Smuzhiyun struct rsi_debugfs *dfsentry; 372*4882a593Smuzhiyun u8 num_debugfs_entries; 373*4882a593Smuzhiyun #endif 374*4882a593Smuzhiyun char *fw_file_name; 375*4882a593Smuzhiyun struct timer_list bl_cmd_timer; 376*4882a593Smuzhiyun bool blcmd_timer_expired; 377*4882a593Smuzhiyun u32 flash_capacity; 378*4882a593Smuzhiyun struct eepromrw_info eeprom; 379*4882a593Smuzhiyun u32 interrupt_status; 380*4882a593Smuzhiyun u8 dfs_region; 381*4882a593Smuzhiyun char country[2]; 382*4882a593Smuzhiyun void *rsi_dev; 383*4882a593Smuzhiyun struct rsi_host_intf_ops *host_intf_ops; 384*4882a593Smuzhiyun int (*check_hw_queue_status)(struct rsi_hw *adapter, u8 q_num); 385*4882a593Smuzhiyun int (*determine_event_timeout)(struct rsi_hw *adapter); 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun void rsi_print_version(struct rsi_common *common); 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun struct rsi_host_intf_ops { 391*4882a593Smuzhiyun int (*read_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); 392*4882a593Smuzhiyun int (*write_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); 393*4882a593Smuzhiyun int (*master_access_msword)(struct rsi_hw *adapter, u16 ms_word); 394*4882a593Smuzhiyun int (*read_reg_multiple)(struct rsi_hw *adapter, u32 addr, 395*4882a593Smuzhiyun u8 *data, u16 count); 396*4882a593Smuzhiyun int (*write_reg_multiple)(struct rsi_hw *adapter, u32 addr, 397*4882a593Smuzhiyun u8 *data, u16 count); 398*4882a593Smuzhiyun int (*master_reg_read)(struct rsi_hw *adapter, u32 addr, 399*4882a593Smuzhiyun u32 *read_buf, u16 size); 400*4882a593Smuzhiyun int (*master_reg_write)(struct rsi_hw *adapter, 401*4882a593Smuzhiyun unsigned long addr, unsigned long data, 402*4882a593Smuzhiyun u16 size); 403*4882a593Smuzhiyun int (*load_data_master_write)(struct rsi_hw *adapter, u32 addr, 404*4882a593Smuzhiyun u32 instructions_size, u16 block_size, 405*4882a593Smuzhiyun u8 *fw); 406*4882a593Smuzhiyun int (*reinit_device)(struct rsi_hw *adapter); 407*4882a593Smuzhiyun int (*ta_reset)(struct rsi_hw *adapter); 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun enum rsi_host_intf rsi_get_host_intf(void *priv); 411*4882a593Smuzhiyun void rsi_set_bt_context(void *priv, void *bt_context); 412*4882a593Smuzhiyun void rsi_attach_bt(struct rsi_common *common); 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun #endif 415