1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __HALDMOUTSRC_H__ 27 #define __HALDMOUTSRC_H__ 28 29 /*@============================================================*/ 30 /*@include files*/ 31 /*@============================================================*/ 32 /*PHYDM header*/ 33 #include "phydm_pre_define.h" 34 #include "phydm_features.h" 35 #include "phydm_dig.h" 36 #ifdef CONFIG_PATH_DIVERSITY 37 #include "phydm_pathdiv.h" 38 #endif 39 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 40 #include "phydm_antdiv.h" 41 #endif 42 43 #include "phydm_soml.h" 44 45 #ifdef CONFIG_SMART_ANTENNA 46 #include "phydm_smt_ant.h" 47 #endif 48 #ifdef CONFIG_ANT_DETECTION 49 #include "phydm_antdect.h" 50 #endif 51 #include "phydm_rainfo.h" 52 #ifdef CONFIG_DYNAMIC_TX_TWR 53 #include "phydm_dynamictxpower.h" 54 #endif 55 #include "phydm_cfotracking.h" 56 #include "phydm_adaptivity.h" 57 #include "phydm_dfs.h" 58 #include "phydm_ccx.h" 59 #include "txbf/phydm_hal_txbf_api.h" 60 #if (PHYDM_LA_MODE_SUPPORT) 61 #include "phydm_adc_sampling.h" 62 #endif 63 #ifdef CONFIG_PSD_TOOL 64 #include "phydm_psd.h" 65 #endif 66 #ifdef PHYDM_PRIMARY_CCA 67 #include "phydm_primary_cca.h" 68 #endif 69 #include "phydm_cck_pd.h" 70 #include "phydm_rssi_monitor.h" 71 #ifdef PHYDM_AUTO_DEGBUG 72 #include "phydm_auto_dbg.h" 73 #endif 74 #include "phydm_math_lib.h" 75 #include "phydm_noisemonitor.h" 76 #include "phydm_api.h" 77 #ifdef PHYDM_POWER_TRAINING_SUPPORT 78 #include "phydm_pow_train.h" 79 #endif 80 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 81 #include "phydm_lna_sat.h" 82 #endif 83 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 84 #include "phydm_pmac_tx_setting.h" 85 #endif 86 #ifdef PHYDM_MP_SUPPORT 87 #include "phydm_mp.h" 88 #endif 89 90 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 91 #include "phydm_cck_rx_pathdiv.h" 92 #endif 93 94 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 95 #include "phydm_beamforming.h" 96 #endif 97 98 #ifdef CONFIG_DIRECTIONAL_BF 99 #include "phydm_direct_bf.h" 100 #endif 101 102 #include "phydm_regtable.h" 103 104 /*@HALRF header*/ 105 #include "halrf/halrf_iqk.h" 106 #include "halrf/halrf_dpk.h" 107 #include "halrf/halrf.h" 108 #include "halrf/halrf_powertracking.h" 109 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 110 #include "halrf/halphyrf_ap.h" 111 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 112 #include "halrf/halphyrf_ce.h" 113 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 114 #include "halrf/halphyrf_win.h" 115 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 116 #include "halrf/halphyrf_iot.h" 117 #endif 118 119 extern const u16 phy_rate_table[84]; 120 121 /*@============================================================*/ 122 /*@Definition */ 123 /*@============================================================*/ 124 125 /* Traffic load decision */ 126 #define TRAFFIC_NO_TP 0 127 #define TRAFFIC_ULTRA_LOW 1 128 #define TRAFFIC_LOW 2 129 #define TRAFFIC_MID 3 130 #define TRAFFIC_HIGH 4 131 132 #define NONE 0 133 134 #if defined(DM_ODM_CE_MAC80211) 135 #define MAX_2(x, y) \ 136 __max2(typeof(x), typeof(y), \ 137 x, y) 138 #define __max2(t1, t2, x, y) ({ \ 139 t1 m80211_max1 = (x); \ 140 t2 m80211_max2 = (y); \ 141 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 142 143 #define MIN_2(x, y) \ 144 __min2(typeof(x), typeof(y), \ 145 x, y) 146 #define __min2(t1, t2, x, y) ({ \ 147 t1 m80211_min1 = (x); \ 148 t2 m80211_min2 = (y); \ 149 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 150 151 #define DIFF_2(x, y) \ 152 __diff2(typeof(x), typeof(y), \ 153 x, y) 154 #define __diff2(t1, t2, x, y) ({ \ 155 t1 __d1 = (x); \ 156 t2 __d2 = (y); \ 157 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 158 #else 159 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 160 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 161 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 162 #endif 163 164 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 165 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 166 167 #if defined(DM_ODM_CE_MAC80211) 168 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 169 u32 __b_dup = (B0);\ 170 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 171 }) 172 #else 173 #define BYTE_DUPLICATE_2_DWORD(B0) \ 174 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 175 #endif 176 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 177 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 178 #define BIT_2_BYTE(B3, B2, B1, B0) \ 179 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 180 181 /*@For cmn sta info*/ 182 #if defined(DM_ODM_CE_MAC80211) 183 #define is_sta_active(sta) ({ \ 184 struct cmn_sta_info *__sta = (sta); \ 185 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 186 }) 187 188 #define IS_FUNC_EN(name) ({ \ 189 u8 *__is_func_name = (name); \ 190 (__is_func_name) && (*__is_func_name); \ 191 }) 192 #else 193 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 194 195 #define IS_FUNC_EN(name) ((name) && (*name)) 196 #endif 197 198 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 199 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 200 #else 201 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 202 #endif 203 204 #define PHY_HIST_SIZE 12 205 #define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) 206 207 /*@============================================================*/ 208 /*structure and define*/ 209 /*@============================================================*/ 210 211 #define dm_type_by_fw 0 212 #define dm_type_by_driver 1 213 214 #ifdef BB_RAM_SUPPORT 215 216 struct phydm_bb_ram_per_sta { 217 /* @Reg0x1E84 for RAM I/O*/ 218 boolean hw_igi_en; 219 boolean tx_pwr_offset0_en; 220 boolean tx_pwr_offset1_en; 221 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 222 u8 macid_addr; 223 /* @hw_igi value for paths after packet Tx in a period of time*/ 224 u8 hw_igi; 225 /* @tx_pwr_offset0 offset for Tx power index*/ 226 s8 tx_pwr_offset0; 227 s8 tx_pwr_offset1; 228 229 }; 230 231 struct phydm_bb_ram_ctrl { 232 /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ 233 struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM]; 234 /*------------ For table2 do not set power offset by macid --------*/ 235 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 236 boolean tx_pwr_ofst_reg0_en; 237 u8 tx_pwr_ofst_reg0; 238 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 239 boolean tx_pwr_ofst_reg1_en; 240 u8 tx_pwr_ofst_reg1; 241 }; 242 243 #endif 244 245 struct phydm_phystatus_statistic { 246 /*@[CCK]*/ 247 u32 rssi_cck_sum; 248 u32 rssi_cck_cnt; 249 u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; 250 u32 rssi_beacon_cnt; 251 #ifdef PHYSTS_3RD_TYPE_SUPPORT 252 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 253 u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; 254 #endif 255 #endif 256 /*@[OFDM]*/ 257 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 258 u32 rssi_ofdm_cnt; 259 u32 evm_ofdm_sum; 260 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 261 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 262 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 263 /*@[1SS]*/ 264 u32 rssi_1ss_cnt; 265 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 266 u32 evm_1ss_sum; 267 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 268 u16 evm_1ss_hist[PHY_HIST_SIZE]; 269 u16 snr_1ss_hist[PHY_HIST_SIZE]; 270 /*@[2SS]*/ 271 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 272 u32 rssi_2ss_cnt; 273 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 274 u32 evm_2ss_sum[2]; 275 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 276 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 277 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 278 #endif 279 /*@[3SS]*/ 280 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 281 u32 rssi_3ss_cnt; 282 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 283 u32 evm_3ss_sum[3]; 284 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 285 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 286 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 287 #endif 288 /*@[4SS]*/ 289 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 290 u32 rssi_4ss_cnt; 291 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 292 u32 evm_4ss_sum[4]; 293 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 294 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 295 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 296 #endif 297 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 298 u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ 299 u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ 300 u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; 301 #endif 302 }; 303 304 struct phydm_phystatus_avg { 305 /*@[CCK]*/ 306 u8 rssi_cck_avg; 307 u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; 308 #ifdef PHYSTS_3RD_TYPE_SUPPORT 309 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 310 u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; 311 #endif 312 #endif 313 /*@[OFDM]*/ 314 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 315 u8 evm_ofdm_avg; 316 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 317 /*@[1SS]*/ 318 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 319 u8 evm_1ss_avg; 320 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 321 /*@[2SS]*/ 322 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 323 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 324 u8 evm_2ss_avg[2]; 325 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 326 #endif 327 /*@[3SS]*/ 328 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 329 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 330 u8 evm_3ss_avg[3]; 331 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 332 #endif 333 /*@[4SS]*/ 334 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 335 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 336 u8 evm_4ss_avg[4]; 337 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 338 #endif 339 }; 340 341 struct odm_phy_dbg_info { 342 /*@ODM Write,debug info*/ 343 u32 num_qry_phy_status_cck; 344 u32 num_qry_phy_status_ofdm; 345 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 346 u32 num_qry_mu_pkt; 347 u32 num_qry_bf_pkt; 348 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 349 boolean is_ldpc_pkt; 350 boolean is_stbc_pkt; 351 u8 num_of_ppdu[4]; 352 u8 gid_num[4]; 353 #endif 354 u32 condi_num; /*@condition number U(18,4)*/ 355 u8 condi_num_cdf[CN_CNT_MAX]; 356 u8 num_qry_beacon_pkt; 357 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 358 u8 beacon_phy_rate; 359 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 360 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 361 u16 show_phy_sts_cnt; 362 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 363 u16 num_qry_ht_pkt[HT_RATE_NUM]; 364 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 365 boolean ht_pkt_not_zero; 366 boolean low_bw_20_occur; 367 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 368 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 369 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 370 boolean vht_pkt_not_zero; 371 boolean low_bw_40_occur; 372 #endif 373 u16 snr_hist_th[PHY_HIST_TH_SIZE]; 374 u16 evm_hist_th[PHY_HIST_TH_SIZE]; 375 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 376 u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ 377 #endif 378 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 379 s16 cfo_tail[4]; /* per-path's cfo_tail */ 380 #endif 381 struct phydm_phystatus_statistic physts_statistic_info; 382 struct phydm_phystatus_avg phystatus_statistic_avg; 383 }; 384 385 enum odm_cmninfo { 386 /*@Fixed value*/ 387 /*@-----------HOOK BEFORE REG INIT-----------*/ 388 ODM_CMNINFO_PLATFORM = 0, 389 ODM_CMNINFO_ABILITY, 390 ODM_CMNINFO_INTERFACE, 391 ODM_CMNINFO_MP_TEST_CHIP, 392 ODM_CMNINFO_IC_TYPE, 393 ODM_CMNINFO_CUT_VER, 394 ODM_CMNINFO_FAB_VER, 395 ODM_CMNINFO_FW_VER, 396 ODM_CMNINFO_FW_SUB_VER, 397 ODM_CMNINFO_RF_TYPE, 398 ODM_CMNINFO_RFE_TYPE, 399 ODM_CMNINFO_DPK_EN, 400 ODM_CMNINFO_BOARD_TYPE, 401 ODM_CMNINFO_PACKAGE_TYPE, 402 ODM_CMNINFO_EXT_LNA, 403 ODM_CMNINFO_5G_EXT_LNA, 404 ODM_CMNINFO_EXT_PA, 405 ODM_CMNINFO_5G_EXT_PA, 406 ODM_CMNINFO_GPA, 407 ODM_CMNINFO_APA, 408 ODM_CMNINFO_GLNA, 409 ODM_CMNINFO_ALNA, 410 ODM_CMNINFO_TDMA, 411 ODM_CMNINFO_EXT_TRSW, 412 ODM_CMNINFO_EXT_LNA_GAIN, 413 ODM_CMNINFO_PATCH_ID, 414 ODM_CMNINFO_BINHCT_TEST, 415 ODM_CMNINFO_BWIFI_TEST, 416 ODM_CMNINFO_SMART_CONCURRENT, 417 ODM_CMNINFO_CONFIG_BB_RF, 418 ODM_CMNINFO_IQKPAOFF, 419 ODM_CMNINFO_HUBUSBMODE, 420 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 421 ODM_CMNINFO_TX_TP, 422 ODM_CMNINFO_RX_TP, 423 ODM_CMNINFO_SOUNDING_SEQ, 424 ODM_CMNINFO_REGRFKFREEENABLE, 425 ODM_CMNINFO_RFKFREEENABLE, 426 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 427 ODM_CMNINFO_VALID_PATH_SET, 428 ODM_CMNINFO_EFUSE0X3D8, 429 ODM_CMNINFO_EFUSE0X3D7, 430 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 431 ODM_CMNINFO_X_CAP_SETTING, 432 ODM_CMNINFO_ADVANCE_OTA, 433 ODM_CMNINFO_HP_HWID, 434 ODM_CMNINFO_TSSI_ENABLE, 435 ODM_CMNINFO_DIS_DPD, 436 ODM_CMNINFO_POWER_VOLTAGE, 437 /*@-----------HOOK BEFORE REG INIT-----------*/ 438 439 /*@Dynamic value:*/ 440 441 /*@--------- POINTER REFERENCE-----------*/ 442 ODM_CMNINFO_TX_UNI, 443 ODM_CMNINFO_RX_UNI, 444 ODM_CMNINFO_BAND, 445 ODM_CMNINFO_SEC_CHNL_OFFSET, 446 ODM_CMNINFO_SEC_MODE, 447 ODM_CMNINFO_BW, 448 ODM_CMNINFO_CHNL, 449 ODM_CMNINFO_FORCED_RATE, 450 ODM_CMNINFO_ANT_DIV, 451 ODM_CMNINFO_PATH_DIV, 452 ODM_CMNINFO_ADAPTIVE_SOML, 453 ODM_CMNINFO_ADAPTIVITY, 454 ODM_CMNINFO_SCAN, 455 ODM_CMNINFO_POWER_SAVING, 456 ODM_CMNINFO_ONE_PATH_CCA, 457 ODM_CMNINFO_DRV_STOP, 458 ODM_CMNINFO_PNP_IN, 459 ODM_CMNINFO_INIT_ON, 460 ODM_CMNINFO_ANT_TEST, 461 ODM_CMNINFO_NET_CLOSED, 462 ODM_CMNINFO_P2P_LINK, 463 ODM_CMNINFO_FCS_MODE, 464 ODM_CMNINFO_IS1ANTENNA, 465 ODM_CMNINFO_RFDEFAULTPATH, 466 ODM_CMNINFO_DFS_MASTER_ENABLE, 467 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 468 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 469 ODM_CMNINFO_SOFT_AP_MODE, 470 ODM_CMNINFO_MP_MODE, 471 ODM_CMNINFO_INTERRUPT_MASK, 472 ODM_CMNINFO_BB_OPERATION_MODE, 473 ODM_CMNINFO_BF_ANTDIV_DECISION, 474 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 475 /*@--------- POINTER REFERENCE-----------*/ 476 477 /*@------------CALL BY VALUE-------------*/ 478 ODM_CMNINFO_WIFI_DIRECT, 479 ODM_CMNINFO_WIFI_DISPLAY, 480 ODM_CMNINFO_LINK_IN_PROGRESS, 481 ODM_CMNINFO_LINK, 482 ODM_CMNINFO_CMW500LINK, 483 ODM_CMNINFO_STATION_STATE, 484 ODM_CMNINFO_RSSI_MIN, 485 ODM_CMNINFO_RSSI_MIN_BY_PATH, 486 ODM_CMNINFO_DBG_COMP, 487 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 488 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 489 ODM_CMNINFO_RF_ANTENNA_TYPE, 490 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 491 ODM_CMNINFO_BE_FIX_TX_ANT, 492 ODM_CMNINFO_BT_ENABLED, 493 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 494 ODM_CMNINFO_BT_HS_RSSI, 495 ODM_CMNINFO_BT_OPERATION, 496 ODM_CMNINFO_BT_LIMITED_DIG, 497 ODM_CMNINFO_AP_TOTAL_NUM, 498 ODM_CMNINFO_POWER_TRAINING, 499 ODM_CMNINFO_DFS_REGION_DOMAIN, 500 ODM_CMNINFO_BT_CONTINUOUS_TURN, 501 ODM_CMNINFO_IS_DOWNLOAD_FW, 502 ODM_CMNINFO_PHYDM_PATCH_ID, 503 ODM_CMNINFO_RRSR_VAL, 504 ODM_CMNINFO_LINKED_BF_SUPPORT, 505 /*@------------CALL BY VALUE-------------*/ 506 507 /*@Dynamic ptr array hook itms.*/ 508 ODM_CMNINFO_STA_STATUS, 509 ODM_CMNINFO_MAX, 510 511 }; 512 513 enum phydm_rfe_bb_source_sel { 514 PAPE_2G = 0, 515 PAPE_5G = 1, 516 LNA0N_2G = 2, 517 LNAON_5G = 3, 518 TRSW = 4, 519 TRSW_B = 5, 520 GNT_BT = 6, 521 ZERO = 7, 522 ANTSEL_0 = 8, 523 ANTSEL_1 = 9, 524 ANTSEL_2 = 0xa, 525 ANTSEL_3 = 0xb, 526 ANTSEL_4 = 0xc, 527 ANTSEL_5 = 0xd, 528 ANTSEL_6 = 0xe, 529 ANTSEL_7 = 0xf 530 }; 531 532 enum phydm_info_query { 533 PHYDM_INFO_FA_OFDM, 534 PHYDM_INFO_FA_CCK, 535 PHYDM_INFO_FA_TOTAL, 536 PHYDM_INFO_CCA_OFDM, 537 PHYDM_INFO_CCA_CCK, 538 PHYDM_INFO_CCA_ALL, 539 PHYDM_INFO_CRC32_OK_VHT, 540 PHYDM_INFO_CRC32_OK_HT, 541 PHYDM_INFO_CRC32_OK_LEGACY, 542 PHYDM_INFO_CRC32_OK_CCK, 543 PHYDM_INFO_CRC32_ERROR_VHT, 544 PHYDM_INFO_CRC32_ERROR_HT, 545 PHYDM_INFO_CRC32_ERROR_LEGACY, 546 PHYDM_INFO_CRC32_ERROR_CCK, 547 PHYDM_INFO_EDCCA_FLAG, 548 PHYDM_INFO_OFDM_ENABLE, 549 PHYDM_INFO_CCK_ENABLE, 550 PHYDM_INFO_CRC32_OK_HT_AGG, 551 PHYDM_INFO_CRC32_ERROR_HT_AGG, 552 PHYDM_INFO_DBG_PORT_0, 553 PHYDM_INFO_CURR_IGI, 554 PHYDM_INFO_RSSI_MIN, 555 PHYDM_INFO_RSSI_MAX, 556 PHYDM_INFO_CLM_RATIO, 557 PHYDM_INFO_NHM_RATIO, 558 PHYDM_INFO_NHM_NOISE_PWR, 559 }; 560 561 enum phydm_api { 562 PHYDM_API_NBI = 1, 563 PHYDM_API_CSI_MASK = 2, 564 }; 565 566 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 567 568 F00_DIG = 0, 569 F01_RA_MASK = 1, 570 F02_DYN_TXPWR = 2, 571 F03_FA_CNT = 3, 572 F04_RSSI_MNTR = 4, 573 F05_CCK_PD = 5, 574 F06_ANT_DIV = 6, 575 F07_SMT_ANT = 7, 576 F08_PWR_TRAIN = 8, 577 F09_RA = 9, 578 F10_PATH_DIV = 10, 579 F11_DFS = 11, 580 F12_DYN_ARFR = 12, 581 F13_ADPTVTY = 13, 582 F14_CFO_TRK = 14, 583 F15_ENV_MNTR = 15, 584 F16_PRI_CCA = 16, 585 F17_ADPTV_SOML = 17, 586 F18_LNA_SAT_CHK = 18, 587 }; 588 589 /*@=[PHYDM supportability]==========================================*/ 590 enum odm_ability { 591 ODM_BB_DIG = BIT(F00_DIG), 592 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 593 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 594 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 595 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 596 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 597 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 598 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 599 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 600 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 601 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 602 ODM_BB_DFS = BIT(F11_DFS), 603 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 604 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 605 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 606 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 607 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 608 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 609 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 610 }; 611 612 /*@=[PHYDM Debug Component]=====================================*/ 613 enum phydm_dbg_comp { 614 /*@BB Driver Functions*/ 615 DBG_DIG = BIT(F00_DIG), 616 DBG_RA_MASK = BIT(F01_RA_MASK), 617 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 618 DBG_FA_CNT = BIT(F03_FA_CNT), 619 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 620 DBG_CCKPD = BIT(F05_CCK_PD), 621 DBG_ANT_DIV = BIT(F06_ANT_DIV), 622 DBG_SMT_ANT = BIT(F07_SMT_ANT), 623 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 624 DBG_RA = BIT(F09_RA), 625 DBG_PATH_DIV = BIT(F10_PATH_DIV), 626 DBG_DFS = BIT(F11_DFS), 627 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 628 DBG_ADPTVTY = BIT(F13_ADPTVTY), 629 DBG_CFO_TRK = BIT(F14_CFO_TRK), 630 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 631 DBG_PRI_CCA = BIT(F16_PRI_CCA), 632 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 633 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 634 /*BIT(19)*/ 635 /*Neet to re-arrange*/ 636 DBG_PHY_STATUS = BIT(20), 637 DBG_TMP = BIT(21), 638 DBG_FW_TRACE = BIT(22), 639 DBG_TXBF = BIT(23), 640 DBG_COMMON_FLOW = BIT(24), 641 DBG_COMP_MCC = BIT(25), 642 /*BIT(26)*/ 643 DBG_DM_SUMMARY = BIT(27), 644 ODM_PHY_CONFIG = BIT(28), 645 ODM_COMP_INIT = BIT(29), 646 DBG_CMN = BIT(30),/*@common*/ 647 ODM_COMP_API = BIT(31) 648 }; 649 650 /*@=========================================================*/ 651 652 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 653 enum odm_cca_path { 654 ODM_CCA_2R = 0, 655 ODM_CCA_1R_A = 1, 656 ODM_CCA_1R_B = 2, 657 }; 658 659 enum phy_reg_pg_type { 660 PHY_REG_PG_RELATIVE_VALUE = 0, 661 PHY_REG_PG_EXACT_VALUE = 1 662 }; 663 664 enum phydm_offload_ability { 665 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 666 PHYDM_RF_IQK_OFFLOAD = BIT(1), 667 PHYDM_RF_DPK_OFFLOAD = BIT(2), 668 }; 669 670 struct phydm_pause_lv { 671 s8 lv_dig; 672 s8 lv_cckpd; 673 s8 lv_antdiv; 674 s8 lv_adapt; 675 s8 lv_adsl; 676 }; 677 678 struct phydm_func_poiner { 679 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 680 }; 681 682 struct pkt_process_info { 683 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 684 /*@send phystatus in each sampling time*/ 685 boolean physts_auto_swch_en; 686 u8 mac_ppdu_cnt; 687 u8 phy_ppdu_cnt; /*change with phy cca cnt*/ 688 u8 page_bitmap_target; 689 u8 page_bitmap_record; 690 #endif 691 u8 lna_idx; 692 u8 vga_idx; 693 }; 694 695 #ifdef ODM_CONFIG_BT_COEXIST 696 struct phydm_bt_info { 697 boolean is_bt_enabled; /*@BT is enabled*/ 698 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 699 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 700 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 701 boolean is_bt_limited_dig; /*@BT is busy.*/ 702 }; 703 #endif 704 705 struct phydm_iot_center { 706 boolean is_linked_cmw500; 707 u8 win_patch_id; /*@Customer ID*/ 708 u32 phydm_patch_id; 709 710 }; 711 712 #if (RTL8822B_SUPPORT) 713 struct drp_rtl8822b_struct { 714 enum bb_path path_judge; 715 u16 path_a_cck_fa; 716 u16 path_b_cck_fa; 717 }; 718 #endif 719 720 #ifdef CONFIG_MCC_DM 721 #define MCC_DM_REG_NUM 32 722 struct _phydm_mcc_dm_ { 723 u8 mcc_pre_status; 724 u8 mcc_reg_id[MCC_DM_REG_NUM]; 725 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 726 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 727 /*mcc DIG*/ 728 u8 mcc_rssi[2]; 729 /*u8 mcc_igi[2];*/ 730 731 /* need to be config by driver*/ 732 u8 mcc_status; 733 u8 sta_macid[2][NUM_STA]; 734 u16 mcc_rf_ch[2]; 735 736 }; 737 #endif 738 739 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 740 struct phydm_physts { 741 u8 cck_gi_u_bnd; 742 u8 cck_gi_l_bnd; 743 }; 744 #endif 745 746 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 747 #if (RT_PLATFORM != PLATFORM_LINUX) 748 typedef 749 #endif 750 751 struct dm_struct { 752 #else/*for AP, CE Team*/ 753 struct dm_struct { 754 #endif 755 /*@Add for different team use temporarily*/ 756 void *adapter; /*@For CE/NIC team*/ 757 struct rtl8192cd_priv *priv; /*@For AP team*/ 758 boolean odm_ready; 759 enum phy_reg_pg_type phy_reg_pg_value_type; 760 u8 phy_reg_pg_version; 761 u64 support_ability; /*@PHYDM function Supportability*/ 762 u64 pause_ability; /*@PHYDM function pause Supportability*/ 763 u64 debug_components; 764 u8 cmn_dbg_msg_period; 765 u8 cmn_dbg_msg_cnt; 766 u32 fw_debug_components; 767 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 768 u32 last_num_qry_phy_status_all; 769 u32 rx_pwdb_ave; 770 boolean is_init_hw_info_by_rfe; 771 772 //TSSI 773 u8 en_tssi_mode; 774 775 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 776 boolean is_cck_high_power; 777 u8 rf_path_rx_enable; 778 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 779 780 /* @COMMON INFORMATION */ 781 782 /*@Init value*/ 783 /*@-----------HOOK BEFORE REG INIT-----------*/ 784 785 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 786 u8 normal_rx_path; 787 u8 valid_path_set; /*@use for single rx path only*/ 788 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 789 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 790 u32 support_ic_type; /*@PHYDM supported IC*/ 791 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 792 u8 ic_ip_series; /*N/AC/JGR3*/ 793 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 794 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 795 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 796 u8 fw_version; 797 u8 fw_sub_version; 798 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 799 u8 rfe_type; 800 u8 board_type; 801 u8 package_type; 802 u16 type_glna; 803 u16 type_gpa; 804 u16 type_alna; 805 u16 type_apa; 806 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 807 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 808 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 809 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 810 u8 efuse0x3d7; /*@with Efuse number*/ 811 u8 efuse0x3d8; 812 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 813 u8 ext_lna_gain; /*@gain of external lna*/ 814 boolean is_in_hct_test; 815 u8 wifi_test; 816 boolean is_dual_mac_smart_concurrent; 817 u32 bk_support_ability; /*SD4 only*/ 818 u8 with_extenal_ant_switch; 819 /*@cck agc relative*/ 820 boolean cck_new_agc; 821 s8 cck_lna_gain_table[8]; 822 u8 cck_sat_cnt_th_init; 823 /*@-------------------------------------*/ 824 u32 phydm_sys_up_time; 825 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 826 u32 soft_ap_special_setting; 827 boolean boolean_dummy; 828 s8 s8_dummy; 829 u8 u8_dummy; 830 u16 u16_dummy; 831 u32 u32_dummy; 832 u8 rfe_hwsetting_band; 833 u8 p_advance_ota; 834 boolean hp_hw_id; 835 boolean BOOLEAN_temp; 836 boolean is_dfs_band; 837 u8 is_rx_blocking_en; 838 u16 fw_offload_ability; 839 boolean is_download_fw; 840 boolean en_dis_dpd; 841 u16 dis_dpd_rate; 842 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT) 843 u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; 844 u32 bp_0x9b0; 845 #endif 846 /*@-----------HOOK BEFORE REG INIT-----------*/ 847 /*@===========================================================*/ 848 /*@====[ CALL BY Reference ]=========================================*/ 849 /*@===========================================================*/ 850 851 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 852 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 853 u8 *band_type; /*@2.4G/5G = 0/1*/ 854 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 855 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 856 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 857 u8 *channel; /*@central CH number*/ 858 boolean *is_scan_in_process; 859 boolean *is_power_saving; 860 boolean *is_tdma; 861 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 862 u8 *antenna_test; 863 boolean *is_net_closed; 864 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 865 /*@--------- For 8723B IQK-------------------------------------*/ 866 boolean *is_1_antenna; 867 u8 *rf_default_path; /* @0:S1, 1:S0 */ 868 /*@-----------------------------------------------------------*/ 869 870 u16 *forced_data_rate; 871 u8 *enable_antdiv; 872 u8 *enable_pathdiv; 873 u8 *en_adap_soml; 874 u8 *edcca_mode; 875 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 876 boolean *is_fw_dw_rsvd_page_in_progress; 877 u32 *current_tx_tp; 878 u32 *current_rx_tp; 879 u8 *sounding_seq; 880 u32 *soft_ap_mode; 881 u8 *mp_mode; 882 u32 *interrupt_mask; 883 u8 *bb_op_mode; 884 u32 *manual_supportability; 885 /*@===========================================================*/ 886 /*@====[ CALL BY VALUE ]===========================================*/ 887 /*@===========================================================*/ 888 889 u8 disable_phydm_watchdog; 890 boolean is_link_in_process; 891 boolean is_wifi_direct; 892 boolean is_wifi_display; 893 boolean is_linked; 894 boolean pre_is_linked; 895 boolean first_connect; 896 boolean first_disconnect; 897 boolean bsta_state; 898 u8 rssi_min; 899 u8 rssi_min_macid; 900 u8 pre_rssi_min; 901 u8 rssi_max; 902 u8 rssi_max_macid; 903 u8 rssi_min_by_path; 904 boolean is_mp_chip; 905 boolean is_one_entry_only; 906 u32 one_entry_macid; 907 u32 one_entry_tp; 908 u32 pre_one_entry_tp; 909 u8 pre_number_linked_client; 910 u8 number_linked_client; 911 u8 pre_number_active_client; 912 u8 number_active_client; 913 boolean is_disable_phy_api; 914 u8 rssi_a; 915 u8 rssi_b; 916 u8 rssi_c; 917 u8 rssi_d; 918 s8 rxsc_80; 919 s8 rxsc_40; 920 s8 rxsc_20; 921 s8 rxsc_l; 922 u64 rssi_trsw; 923 u64 rssi_trsw_h; 924 u64 rssi_trsw_l; 925 u64 rssi_trsw_iso; 926 u8 tx_ant_status; /*TX path enable*/ 927 u8 rx_ant_status; /*RX path enable*/ 928 #ifdef PHYDM_COMPILE_ABOVE_4SS 929 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 930 #endif 931 #ifdef PHYDM_COMPILE_ABOVE_3SS 932 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 933 #endif 934 #ifdef PHYDM_COMPILE_ABOVE_2SS 935 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 936 #endif 937 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 938 u8 cck_lna_idx; 939 u8 cck_vga_idx; 940 u8 curr_station_id; 941 u8 ofdm_agc_idx[4]; 942 u8 rx_rate; 943 u8 rate_ss; 944 u8 tx_rate; 945 u8 linked_interval; 946 u8 pre_channel; 947 u32 txagc_offset_value_a; 948 boolean is_txagc_offset_positive_a; 949 u32 txagc_offset_value_b; 950 boolean is_txagc_offset_positive_b; 951 u8 ap_total_num; 952 /*@[traffic]*/ 953 u8 traffic_load; 954 u8 pre_traffic_load; 955 u32 tx_tp; /*@Mbps*/ 956 u32 rx_tp; /*@Mbps*/ 957 u32 total_tp; /*@Mbps*/ 958 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 959 u64 cur_tx_ok_cnt; 960 u64 cur_rx_ok_cnt; 961 u64 last_tx_ok_cnt; 962 u64 last_rx_ok_cnt; 963 u16 consecutive_idlel_time; /*@unit: second*/ 964 /*@---------------------------*/ 965 boolean is_bb_swing_offset_positive_a; 966 boolean is_bb_swing_offset_positive_b; 967 968 /*@[DIG]*/ 969 boolean MPDIG_2G; /*off MPDIG*/ 970 u8 times_2g; /*@for MP DIG*/ 971 u8 force_igi; /*@for debug*/ 972 973 /*@[TDMA-DIG]*/ 974 u16 tdma_dig_timer_ms; 975 u8 tdma_dig_state_number; 976 u8 tdma_dig_low_upper_bond; 977 u8 force_tdma_low_igi; 978 u8 force_tdma_high_igi; 979 u8 fix_expire_to_zero; 980 boolean original_dig_restore; 981 /*@---------------------------*/ 982 983 /*@[AntDiv]*/ 984 u8 ant_div_type; 985 u8 antdiv_rssi; 986 u8 fat_comb_a; 987 u8 fat_comb_b; 988 u8 antdiv_intvl; 989 u8 antdiv_delay; 990 u8 ant_type; 991 u8 ant_type2; 992 u8 pre_ant_type; 993 u8 pre_ant_type2; 994 u8 antdiv_period; 995 u8 evm_antdiv_period; 996 u8 antdiv_select; 997 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 998 u8 stop_antdiv_rssi_th; 999 u16 stop_antdiv_tp_diff_th; 1000 u16 stop_antdiv_tp_th; 1001 u8 antdiv_tp_period; 1002 u16 tp_active_th; 1003 u8 tp_active_occur; 1004 u8 path_select; 1005 u8 antdiv_evm_en; 1006 u8 bdc_holdstate; 1007 u8 antdiv_counter; 1008 /*@---------------------------*/ 1009 1010 u8 ndpa_period; 1011 boolean h2c_rarpt_connect; 1012 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 1013 u8 print_agc; 1014 u8 la_mode; 1015 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 1016 u8 current_rf_set_8821c; 1017 u8 default_rf_set_8821c; 1018 u8 current_ant_num_8821c; 1019 u8 default_ant_num_8821c; 1020 u8 rfe_type_expand; 1021 /*@-----------------------------------------------------------*/ 1022 /*@---For Adaptivtiy---------------------------------------------*/ 1023 s8 TH_L2H_default; 1024 s8 th_edcca_hl_diff_default; 1025 s8 th_l2h_ini; 1026 s8 th_edcca_hl_diff; 1027 boolean carrier_sense_enable; 1028 /*@-----------------------------------------------------------*/ 1029 u8 pre_dbg_priority; 1030 u8 nbi_set_result; 1031 u8 c2h_cmd_start; 1032 u8 fw_debug_trace[60]; 1033 u8 pre_c2h_seq; 1034 boolean fw_buff_is_enpty; 1035 u32 data_frame_num; 1036 /*@--- for spur detection ---------------------------------------*/ 1037 boolean en_reg_mntr_bb; 1038 boolean en_reg_mntr_rf; 1039 boolean en_reg_mntr_mac; 1040 boolean en_reg_mntr_byte; 1041 /*@--------------------------------------------------------------*/ 1042 #if (RTL8814B_SUPPORT) 1043 /*@--- for spur detection ---------------------------------------*/ 1044 u8 dsde_sel; 1045 u8 nbi_path_sel; 1046 u8 csi_wgt; 1047 /*@------------------------------------------*/ 1048 #endif 1049 /*@--- for noise detection ---------------------------------------*/ 1050 boolean is_noisy_state; 1051 boolean noisy_decision; /*@b_noisy*/ 1052 boolean pre_b_noisy; 1053 u32 noisy_decision_smooth; 1054 /*@-----------------------------------------------------------*/ 1055 1056 /*@--- for MCC ant weighting ------------------------------------*/ 1057 boolean is_stop_dym_ant_weighting; 1058 /*@-----------------------------------------------------------*/ 1059 1060 boolean is_disable_dym_ecs; 1061 boolean is_disable_dym_ant_weighting; 1062 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1063 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1064 1065 #if (RATE_ADAPTIVE_SUPPORT) 1066 u16 currmin_rpt_time; 1067 struct _phydm_txstatistic_ hw_stats; 1068 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1069 /*Use mac_id as array index. STA mac_id=0*/ 1070 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1071 #endif 1072 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1073 /*We need to colelct all support abilit to a proper area.*/ 1074 boolean ra_support88e; 1075 boolean *is_driver_stopped; 1076 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1077 boolean *pinit_adpt_in_progress; 1078 boolean is_user_assign_level; 1079 u8 RSSI_BT; /*@come from BT*/ 1080 1081 /*@---PSD Relative ---------------------------------------------*/ 1082 boolean is_psd_in_process; 1083 boolean is_psd_active; 1084 /*@-----------------------------------------------------------*/ 1085 1086 boolean bsomlenabled; /* @D-SoML control */ 1087 u8 linked_bf_support; 1088 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1089 u32 n_iqk_cnt; 1090 u32 n_iqk_ok_cnt; 1091 u32 n_iqk_fail_cnt; 1092 1093 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1094 boolean config_bbrf; 1095 #endif 1096 boolean is_disable_power_training; 1097 boolean is_bt_continuous_turn; 1098 u8 enhance_pwr_th[3]; 1099 u8 set_pwr_th[3]; 1100 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1101 #ifdef BB_RAM_SUPPORT 1102 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1103 #endif 1104 u8 dynamic_tx_high_power_lvl; 1105 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1106 u8 last_dtp_lvl; 1107 u8 min_power_index; 1108 u32 tx_agc_ofdm_18_6; 1109 /*-------------------------------------------------------------*/ 1110 u8 rx_pkt_type; 1111 1112 #ifdef CONFIG_PHYDM_DFS_MASTER 1113 u8 dfs_region_domain; 1114 u8 *dfs_master_enabled; 1115 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1116 u8 radar_detect_dbg_parm_en; 1117 u32 radar_detect_reg_918; 1118 u32 radar_detect_reg_91c; 1119 u32 radar_detect_reg_920; 1120 u32 radar_detect_reg_924; 1121 1122 u32 radar_detect_reg_a40; 1123 u32 radar_detect_reg_a44; 1124 u32 radar_detect_reg_a48; 1125 u32 radar_detect_reg_a4c; 1126 u32 radar_detect_reg_a50; 1127 u32 radar_detect_reg_a54; 1128 1129 u32 radar_detect_reg_f54; 1130 u32 radar_detect_reg_f58; 1131 u32 radar_detect_reg_f5c; 1132 u32 radar_detect_reg_f70; 1133 u32 radar_detect_reg_f74; 1134 /*@---For zero-wait DFS---------------------------------------*/ 1135 boolean seg1_dfs_flag; 1136 /*@-----------------------------------------------------------*/ 1137 /*@-----------------------------------------------------------*/ 1138 #endif 1139 1140 /*@=== RTL8721D ===*/ 1141 #if (RTL8721D_SUPPORT) 1142 boolean cbw20_adc80; 1143 boolean invalid_mode; 1144 u8 power_voltage; 1145 u8 cca_cbw20_lev; 1146 u8 cca_cbw40_lev; 1147 #endif 1148 1149 /*@=== PHYDM Timer ========================================== (start)*/ 1150 1151 struct phydm_timer_list mpt_dig_timer; 1152 struct phydm_timer_list fast_ant_training_timer; 1153 #ifdef ODM_EVM_ENHANCE_ANTDIV 1154 struct phydm_timer_list evm_fast_ant_training_timer; 1155 #endif 1156 #ifdef PHYDM_TDMA_DIG_SUPPORT 1157 struct phydm_timer_list tdma_dig_timer; 1158 #endif 1159 struct phydm_timer_list sbdcnt_timer; 1160 1161 /*@=== PHYDM Workitem ======================================= (start)*/ 1162 1163 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1164 #if USE_WORKITEM 1165 RT_WORK_ITEM fast_ant_training_workitem; 1166 RT_WORK_ITEM ra_rpt_workitem; 1167 RT_WORK_ITEM sbdcnt_workitem; 1168 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1169 #ifdef PHYDM_TDMA_DIG_SUPPORT 1170 RT_WORK_ITEM phydm_tdma_dig_workitem; 1171 #endif 1172 #endif 1173 #endif 1174 1175 /*@=== PHYDM Structure ======================================== (start)*/ 1176 struct phydm_func_poiner phydm_func_handler; 1177 struct phydm_iot_center iot_table; 1178 1179 #ifdef ODM_CONFIG_BT_COEXIST 1180 struct phydm_bt_info bt_info_table; 1181 #endif 1182 1183 struct pkt_process_info pkt_proc_struct; 1184 struct phydm_adaptivity_struct adaptivity; 1185 struct _DFS_STATISTICS dfs; 1186 struct odm_noise_monitor noise_level; 1187 struct odm_phy_dbg_info phy_dbg_info; 1188 1189 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1190 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1191 #endif 1192 1193 #ifdef CONFIG_ADAPTIVE_SOML 1194 struct adaptive_soml dm_soml_table; 1195 #endif 1196 1197 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1198 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1199 struct _BF_DIV_COEX_ dm_bdc_table; 1200 #endif 1201 1202 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1203 struct smt_ant_honbo dm_sat_table; 1204 #endif 1205 #endif 1206 1207 #if (defined(CONFIG_SMART_ANTENNA)) 1208 struct smt_ant smtant_table; 1209 #endif 1210 1211 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1212 struct dm_rf_calibration_struct rf_calibrate_info; 1213 struct dm_iqk_info IQK_info; 1214 struct dm_dpk_info dpk_info; 1215 struct dm_dack_info dack_info; 1216 1217 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1218 struct phydm_fat_struct dm_fat_table; 1219 struct sw_antenna_switch dm_swat_table; 1220 #endif 1221 struct phydm_dig_struct dm_dig_table; 1222 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1223 struct phydm_lna_sat_t dm_lna_sat_info; 1224 #endif 1225 1226 #ifdef CONFIG_MCC_DM 1227 struct _phydm_mcc_dm_ mcc_dm; 1228 #endif 1229 1230 #ifdef PHYDM_SUPPORT_CCKPD 1231 struct phydm_cckpd_struct dm_cckpd_table; 1232 #endif 1233 1234 #ifdef PHYDM_PRIMARY_CCA 1235 struct phydm_pricca_struct dm_pri_cca; 1236 #endif 1237 1238 struct ra_table dm_ra_table; 1239 struct phydm_fa_struct false_alm_cnt; 1240 #ifdef PHYDM_TDMA_DIG_SUPPORT 1241 struct phydm_fa_acc_struct false_alm_cnt_acc; 1242 #ifdef IS_USE_NEW_TDMA 1243 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1244 #endif 1245 #endif 1246 struct phydm_cfo_track_struct dm_cfo_track; 1247 struct ccx_info dm_ccx_info; 1248 1249 struct odm_power_trim_data power_trim_data; 1250 #if (RTL8822B_SUPPORT) 1251 struct drp_rtl8822b_struct phydm_rtl8822b; 1252 #endif 1253 1254 #ifdef CONFIG_PSD_TOOL 1255 struct psd_info dm_psd_table; 1256 #endif 1257 1258 #if (PHYDM_LA_MODE_SUPPORT) 1259 struct rt_adcsmp adcsmp; 1260 #endif 1261 1262 #if (defined(CONFIG_PATH_DIVERSITY)) 1263 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1264 #endif 1265 1266 #if (defined(CONFIG_ANT_DETECTION)) 1267 struct _ANT_DETECTED_INFO ant_detected_info; 1268 #endif 1269 1270 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1271 #ifdef PHYDM_BEAMFORMING_SUPPORT 1272 struct _RT_BEAMFORMING_INFO beamforming_info; 1273 #endif 1274 #endif 1275 #ifdef PHYDM_AUTO_DEGBUG 1276 struct phydm_auto_dbg_struct auto_dbg_table; 1277 #endif 1278 1279 struct phydm_pause_lv pause_lv_table; 1280 struct phydm_api_stuc api_table; 1281 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1282 struct phydm_pow_train_stuc pow_train_table; 1283 #endif 1284 1285 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1286 struct phydm_pmac_tx dm_pmac_tx_table; 1287 #endif 1288 1289 #ifdef PHYDM_MP_SUPPORT 1290 struct phydm_mp dm_mp_table; 1291 #endif 1292 1293 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 1294 struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; 1295 #endif 1296 /*@==========================================================*/ 1297 1298 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 1299 /*@-------------------phydm_phystatus report --------------------*/ 1300 struct phydm_physts dm_physts_table; 1301 #endif 1302 1303 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1304 1305 #if (RT_PLATFORM != PLATFORM_LINUX) 1306 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1307 #else 1308 }; 1309 #endif 1310 1311 #else /*@for AP,CE Team*/ 1312 }; 1313 #endif 1314 1315 enum phydm_adv_ota { 1316 PHYDM_PATHB_1RCCA = BIT(0), 1317 PHYDM_HP_OTA_SETTING_A = BIT(1), 1318 PHYDM_HP_OTA_SETTING_B = BIT(2), 1319 PHYDM_ASUS_OTA_SETTING = BIT(3), 1320 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1321 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1322 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1323 1324 }; 1325 1326 enum phydm_bb_op_mode { 1327 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1328 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1329 }; 1330 1331 enum phydm_structure_type { 1332 PHYDM_FALSEALMCNT, 1333 PHYDM_CFOTRACK, 1334 PHYDM_ADAPTIVITY, 1335 PHYDM_DFS, 1336 PHYDM_ROMINFO, 1337 1338 }; 1339 1340 enum odm_bb_config_type { 1341 CONFIG_BB_PHY_REG, 1342 CONFIG_BB_AGC_TAB, 1343 CONFIG_BB_AGC_TAB_2G, 1344 CONFIG_BB_AGC_TAB_5G, 1345 CONFIG_BB_PHY_REG_PG, 1346 CONFIG_BB_PHY_REG_MP, 1347 CONFIG_BB_AGC_TAB_DIFF, 1348 CONFIG_BB_RF_CAL_INIT, 1349 }; 1350 1351 enum odm_rf_config_type { 1352 CONFIG_RF_RADIO, 1353 CONFIG_RF_TXPWR_LMT, 1354 CONFIG_RF_SYN_RADIO, 1355 }; 1356 1357 enum odm_fw_config_type { 1358 CONFIG_FW_NIC, 1359 CONFIG_FW_NIC_2, 1360 CONFIG_FW_AP, 1361 CONFIG_FW_AP_2, 1362 CONFIG_FW_MP, 1363 CONFIG_FW_WOWLAN, 1364 CONFIG_FW_WOWLAN_2, 1365 CONFIG_FW_AP_WOWLAN, 1366 CONFIG_FW_BT, 1367 }; 1368 1369 /*status code*/ 1370 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1371 enum rt_status { 1372 RT_STATUS_SUCCESS, 1373 RT_STATUS_FAILURE, 1374 RT_STATUS_PENDING, 1375 RT_STATUS_RESOURCE, 1376 RT_STATUS_INVALID_CONTEXT, 1377 RT_STATUS_INVALID_PARAMETER, 1378 RT_STATUS_NOT_SUPPORT, 1379 RT_STATUS_OS_API_FAILED, 1380 }; 1381 #endif /*@end of enum rt_status definition*/ 1382 1383 void 1384 phydm_watchdog_lps(struct dm_struct *dm); 1385 1386 void 1387 phydm_watchdog_lps_32k(struct dm_struct *dm); 1388 1389 void 1390 phydm_txcurrentcalibration(struct dm_struct *dm); 1391 1392 void 1393 phydm_dm_early_init(struct dm_struct *dm); 1394 1395 void 1396 odm_dm_init(struct dm_struct *dm); 1397 1398 void 1399 odm_dm_reset(struct dm_struct *dm); 1400 1401 void 1402 phydm_fwoffload_ability_init(struct dm_struct *dm, 1403 enum phydm_offload_ability offload_ability); 1404 1405 void 1406 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1407 enum phydm_offload_ability offload_ability); 1408 1409 void 1410 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1411 char *output, u32 *_out_len); 1412 1413 void 1414 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1415 1416 void 1417 phydm_watchdog(struct dm_struct *dm); 1418 1419 void 1420 phydm_watchdog_mp(struct dm_struct *dm); 1421 1422 u8 1423 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1424 enum phydm_pause_type pause_type, 1425 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1426 1427 void 1428 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1429 char *output, u32 *_out_len); 1430 1431 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, 1432 enum phydm_pause_type pause_type, u8 rssi); 1433 1434 void 1435 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1436 1437 void 1438 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1439 1440 void 1441 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1442 1443 u32 1444 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1445 1446 void 1447 odm_init_all_timers(struct dm_struct *dm); 1448 1449 void 1450 odm_cancel_all_timers(struct dm_struct *dm); 1451 1452 void 1453 odm_release_all_timers(struct dm_struct *dm); 1454 1455 void * 1456 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1457 1458 void 1459 phydm_dc_cancellation(struct dm_struct *dm); 1460 1461 void 1462 phydm_receiver_blocking(void *dm_void); 1463 1464 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1465 void 1466 odm_init_all_work_items( 1467 struct dm_struct *dm 1468 ); 1469 void 1470 odm_free_all_work_items( 1471 struct dm_struct *dm 1472 ); 1473 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1474 1475 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1476 void 1477 odm_dtc(struct dm_struct *dm); 1478 #endif 1479 1480 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1481 void 1482 odm_init_all_threads( 1483 struct dm_struct *dm 1484 ); 1485 1486 void 1487 odm_stop_all_threads( 1488 struct dm_struct *dm 1489 ); 1490 #endif 1491 1492 #endif 1493