1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /***************************************************************************** 3 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. 4 * 5 * Module: __INC_HAL8192SPHYREG_H 6 * 7 * 8 * Note: 1. Define PMAC/BB register map 9 * 2. Define RF register map 10 * 3. PMAC/BB register bit mask. 11 * 4. RF reg bit mask. 12 * 5. Other BB/RF relative definition. 13 * 14 * 15 * Export: Constants, macro, functions(API), global variables(None). 16 * 17 * Abbrev: 18 * 19 * History: 20 * Data Who Remark 21 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 22 * 2. Reorganize code architecture. 23 * 09/25/2008 MH 1. Add RL6052 register definition 24 * 25 *****************************************************************************/ 26 #ifndef __INC_HAL8192EPHYREG_H 27 #define __INC_HAL8192EPHYREG_H 28 29 30 /*--------------------------Define Parameters-------------------------------*/ 31 32 /* ************************************************************ 33 * 8192S Regsiter offset definition 34 * ************************************************************ */ 35 36 /* 37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 38 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 40 * 3. RF register 0x00-2E 41 * 4. Bit Mask for BB/RF register 42 * 5. Other defintion for BB/RF R/W 43 * */ 44 45 46 /* 47 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 48 * 1. Page1(0x100) 49 * */ 50 #define rPMAC_Reset 0x100 51 #define rPMAC_TxStart 0x104 52 #define rPMAC_TxLegacySIG 0x108 53 #define rPMAC_TxHTSIG1 0x10c 54 #define rPMAC_TxHTSIG2 0x110 55 #define rPMAC_PHYDebug 0x114 56 #define rPMAC_TxPacketNum 0x118 57 #define rPMAC_TxIdle 0x11c 58 #define rPMAC_TxMACHeader0 0x120 59 #define rPMAC_TxMACHeader1 0x124 60 #define rPMAC_TxMACHeader2 0x128 61 #define rPMAC_TxMACHeader3 0x12c 62 #define rPMAC_TxMACHeader4 0x130 63 #define rPMAC_TxMACHeader5 0x134 64 #define rPMAC_TxDataType 0x138 65 #define rPMAC_TxRandomSeed 0x13c 66 #define rPMAC_CCKPLCPPreamble 0x140 67 #define rPMAC_CCKPLCPHeader 0x144 68 #define rPMAC_CCKCRC16 0x148 69 #define rPMAC_OFDMRxCRC32OK 0x170 70 #define rPMAC_OFDMRxCRC32Er 0x174 71 #define rPMAC_OFDMRxParityEr 0x178 72 #define rPMAC_OFDMRxCRC8Er 0x17c 73 #define rPMAC_CCKCRxRC16Er 0x180 74 #define rPMAC_CCKCRxRC32Er 0x184 75 #define rPMAC_CCKCRxRC32OK 0x188 76 #define rPMAC_TxStatus 0x18c 77 78 79 /* 80 * 3. Page8(0x800) 81 * */ 82 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 83 84 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 85 #define rFPGA0_PSDFunction 0x808 86 87 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 88 89 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 90 #define rFPGA0_RFTiming2 0x814 91 92 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 93 #define rFPGA0_XA_HSSIParameter2 0x824 94 #define rFPGA0_XB_HSSIParameter1 0x828 95 #define rFPGA0_XB_HSSIParameter2 0x82c 96 97 #define rFPGA0_XA_LSSIParameter 0x840 98 #define rFPGA0_XB_LSSIParameter 0x844 99 100 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 101 #define rFPGA0_RFSleepUpParameter 0x854 102 103 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 104 #define rFPGA0_XCD_SwitchControl 0x85c 105 106 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 107 #define rFPGA0_XB_RFInterfaceOE 0x864 108 109 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 110 #define rFPGA0_XCD_RFInterfaceSW 0x874 111 112 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 113 #define rFPGA0_XCD_RFParameter 0x87c 114 115 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 116 #define rFPGA0_AnalogParameter2 0x884 117 #define rFPGA0_AnalogParameter3 0x888 118 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 119 #define rFPGA0_AnalogParameter4 0x88c 120 121 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 122 #define rFPGA0_XB_LSSIReadBack 0x8a4 123 #define rFPGA0_XC_LSSIReadBack 0x8a8 124 #define rFPGA0_XD_LSSIReadBack 0x8ac 125 126 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 127 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 128 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 129 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 130 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 131 132 /* 133 * 4. Page9(0x900) 134 * */ 135 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 136 137 #define rFPGA1_TxBlock 0x904 /* Useless now */ 138 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 139 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 140 141 /* 142 * 5. PageA(0xA00) 143 * 144 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 145 #define rCCK0_System 0xa00 146 147 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 148 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 149 150 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 151 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 152 153 #define rCCK0_RxHP 0xa14 154 155 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 156 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 157 158 #define rCCK0_TxFilter1 0xa20 159 #define rCCK0_TxFilter2 0xa24 160 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 161 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 162 #define rCCK0_TRSSIReport 0xa50 163 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 164 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 165 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 166 167 /* 168 * PageB(0xB00) 169 * */ 170 #define rPdp_AntA 0xb00 171 #define rPdp_AntA_4 0xb04 172 #define rConfig_Pmpd_AntA 0xb28 173 #define rConfig_ram64x16 0xb2c 174 175 #define rConfig_AntA 0xb68 176 #define rConfig_AntB 0xb6c 177 #define rPdp_AntB 0xb70 178 #define rPdp_AntB_4 0xb74 179 #define rConfig_Pmpd_AntB 0xb98 180 #define rAPK 0xbd8 181 182 183 184 /* 185 * 6. PageC(0xC00) 186 * */ 187 #define rOFDM0_LSTF 0xc00 188 189 #define rOFDM0_TRxPathEnable 0xc04 190 #define rOFDM0_TRMuxPar 0xc08 191 #define rOFDM0_TRSWIsolation 0xc0c 192 193 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 194 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 195 #define rOFDM0_XBRxAFE 0xc18 196 #define rOFDM0_XBRxIQImbalance 0xc1c 197 #define rOFDM0_XCRxAFE 0xc20 198 #define rOFDM0_XCRxIQImbalance 0xc24 199 #define rOFDM0_XDRxAFE 0xc28 200 #define rOFDM0_XDRxIQImbalance 0xc2c 201 202 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 203 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 204 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 205 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 206 207 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 208 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 209 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 210 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 211 212 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 213 #define rOFDM0_XAAGCCore2 0xc54 214 #define rOFDM0_XBAGCCore1 0xc58 215 #define rOFDM0_XBAGCCore2 0xc5c 216 #define rOFDM0_XCAGCCore1 0xc60 217 #define rOFDM0_XCAGCCore2 0xc64 218 #define rOFDM0_XDAGCCore1 0xc68 219 #define rOFDM0_XDAGCCore2 0xc6c 220 221 #define rOFDM0_AGCParameter1 0xc70 222 #define rOFDM0_AGCParameter2 0xc74 223 #define rOFDM0_AGCRSSITable 0xc78 224 #define rOFDM0_HTSTFAGC 0xc7c 225 226 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 227 #define rOFDM0_XATxAFE 0xc84 228 #define rOFDM0_XBTxIQImbalance 0xc88 229 #define rOFDM0_XBTxAFE 0xc8c 230 #define rOFDM0_XCTxIQImbalance 0xc90 231 #define rOFDM0_XCTxAFE 0xc94 232 #define rOFDM0_XDTxIQImbalance 0xc98 233 #define rOFDM0_XDTxAFE 0xc9c 234 235 #define rOFDM0_RxIQExtAnta 0xca0 236 #define rOFDM0_TxCoeff1 0xca4 237 #define rOFDM0_TxCoeff2 0xca8 238 #define rOFDM0_TxCoeff3 0xcac 239 #define rOFDM0_TxCoeff4 0xcb0 240 #define rOFDM0_TxCoeff5 0xcb4 241 #define rOFDM0_RxHPParameter 0xce0 242 #define rOFDM0_TxPseudoNoiseWgt 0xce4 243 #define rOFDM0_FrameSync 0xcf0 244 #define rOFDM0_DFSReport 0xcf4 245 246 247 /* 248 * 7. PageD(0xD00) 249 * */ 250 #define rOFDM1_LSTF 0xd00 251 #define rOFDM1_TRxPathEnable 0xd04 252 253 #define rOFDM1_CFO 0xd08 /* No setting now */ 254 #define rOFDM1_CSI1 0xd10 255 #define rOFDM1_SBD 0xd14 256 #define rOFDM1_CSI2 0xd18 257 #define rOFDM1_CFOTracking 0xd2c 258 #define rOFDM1_TRxMesaure1 0xd34 259 #define rOFDM1_IntfDet 0xd3c 260 #define rOFDM1_PseudoNoiseStateAB 0xd50 261 #define rOFDM1_PseudoNoiseStateCD 0xd54 262 #define rOFDM1_RxPseudoNoiseWgt 0xd58 263 264 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 265 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 266 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 267 268 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 269 #define rOFDM_ShortCFOCD 0xdb0 270 #define rOFDM_LongCFOAB 0xdb4 271 #define rOFDM_LongCFOCD 0xdb8 272 #define rOFDM_TailCFOAB 0xdbc 273 #define rOFDM_TailCFOCD 0xdc0 274 #define rOFDM_PWMeasure1 0xdc4 275 #define rOFDM_PWMeasure2 0xdc8 276 #define rOFDM_BWReport 0xdcc 277 #define rOFDM_AGCReport 0xdd0 278 #define rOFDM_RxSNR 0xdd4 279 #define rOFDM_RxEVMCSI 0xdd8 280 #define rOFDM_SIGReport 0xddc 281 282 283 /* 284 * 8. PageE(0xE00) 285 * */ 286 #define rTxAGC_A_Rate18_06 0xe00 287 #define rTxAGC_A_Rate54_24 0xe04 288 #define rTxAGC_A_CCK1_Mcs32 0xe08 289 #define rTxAGC_A_Mcs03_Mcs00 0xe10 290 #define rTxAGC_A_Mcs07_Mcs04 0xe14 291 #define rTxAGC_A_Mcs11_Mcs08 0xe18 292 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 293 294 #define rTxAGC_B_Rate18_06 0x830 295 #define rTxAGC_B_Rate54_24 0x834 296 #define rTxAGC_B_CCK1_55_Mcs32 0x838 297 #define rTxAGC_B_Mcs03_Mcs00 0x83c 298 #define rTxAGC_B_Mcs07_Mcs04 0x848 299 #define rTxAGC_B_Mcs11_Mcs08 0x84c 300 #define rTxAGC_B_Mcs15_Mcs12 0x868 301 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 302 303 #define rFPGA0_IQK 0xe28 304 #define rTx_IQK_Tone_A 0xe30 305 #define rRx_IQK_Tone_A 0xe34 306 #define rTx_IQK_PI_A 0xe38 307 #define rRx_IQK_PI_A 0xe3c 308 309 #define rTx_IQK 0xe40 310 #define rRx_IQK 0xe44 311 #define rIQK_AGC_Pts 0xe48 312 #define rIQK_AGC_Rsp 0xe4c 313 #define rTx_IQK_Tone_B 0xe50 314 #define rRx_IQK_Tone_B 0xe54 315 #define rTx_IQK_PI_B 0xe58 316 #define rRx_IQK_PI_B 0xe5c 317 #define rIQK_AGC_Cont 0xe60 318 319 #define rBlue_Tooth 0xe6c 320 #define rRx_Wait_CCA 0xe70 321 #define rTx_CCK_RFON 0xe74 322 #define rTx_CCK_BBON 0xe78 323 #define rTx_OFDM_RFON 0xe7c 324 #define rTx_OFDM_BBON 0xe80 325 #define rTx_To_Rx 0xe84 326 #define rTx_To_Tx 0xe88 327 #define rRx_CCK 0xe8c 328 329 #define rTx_Power_Before_IQK_A 0xe94 330 #define rTx_Power_After_IQK_A 0xe9c 331 332 #define rRx_Power_Before_IQK_A 0xea0 333 #define rRx_Power_Before_IQK_A_2 0xea4 334 #define rRx_Power_After_IQK_A 0xea8 335 #define rRx_Power_After_IQK_A_2 0xeac 336 337 #define rTx_Power_Before_IQK_B 0xeb4 338 #define rTx_Power_After_IQK_B 0xebc 339 340 #define rRx_Power_Before_IQK_B 0xec0 341 #define rRx_Power_Before_IQK_B_2 0xec4 342 #define rRx_Power_After_IQK_B 0xec8 343 #define rRx_Power_After_IQK_B_2 0xecc 344 345 #define rRx_OFDM 0xed0 346 #define rRx_Wait_RIFS 0xed4 347 #define rRx_TO_Rx 0xed8 348 #define rStandby 0xedc 349 #define rSleep 0xee0 350 #define rPMPD_ANAEN 0xeec 351 352 /* 353 * 7. RF Register 0x00-0x2E (RF 8256) 354 * RF-0222D 0x00-3F 355 * 356 * Zebra1 */ 357 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 358 #define rZebra1_TRxEnable1 0x1 359 #define rZebra1_TRxEnable2 0x2 360 #define rZebra1_AGC 0x4 361 #define rZebra1_ChargePump 0x5 362 #define rZebra1_Channel 0x7 /* RF channel switch */ 363 364 /* #endif */ 365 #define rZebra1_TxGain 0x8 /* Useless now */ 366 #define rZebra1_TxLPF 0x9 367 #define rZebra1_RxLPF 0xb 368 #define rZebra1_RxHPFCorner 0xc 369 370 /* Zebra4 */ 371 #define rGlobalCtrl 0 /* Useless now */ 372 #define rRTL8256_TxLPF 19 373 #define rRTL8256_RxLPF 11 374 375 /* RTL8258 */ 376 #define rRTL8258_TxLPF 0x11 /* Useless now */ 377 #define rRTL8258_RxLPF 0x13 378 #define rRTL8258_RSSILPF 0xa 379 380 /* 381 * RL6052 Register definition 382 * */ 383 #define RF_AC 0x00 /* */ 384 385 #define RF_IQADJ_G1 0x01 /* */ 386 #define RF_IQADJ_G2 0x02 /* */ 387 388 #define RF_POW_TRSW 0x05 /* */ 389 390 #define RF_GAIN_RX 0x06 /* */ 391 #define RF_GAIN_TX 0x07 /* */ 392 393 #define RF_TXM_IDAC 0x08 /* */ 394 #define RF_IPA_G 0x09 /* */ 395 #define RF_TXBIAS_G 0x0A 396 #define RF_TXPA_AG 0x0B 397 #define RF_IPA_A 0x0C /* */ 398 #define RF_TXBIAS_A 0x0D 399 #define RF_BS_PA_APSET_G9_G11 0x0E 400 #define RF_BS_IQGEN 0x0F /* */ 401 402 #define RF_MODE1 0x10 /* */ 403 #define RF_MODE2 0x11 /* */ 404 405 #define RF_RX_AGC_HP 0x12 /* */ 406 #define RF_TX_AGC 0x13 /* */ 407 #define RF_BIAS 0x14 /* */ 408 #define RF_IPA 0x15 /* */ 409 #define RF_TXBIAS 0x16 410 #define RF_POW_ABILITY 0x17 /* */ 411 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 412 #define RF_TOP 0x19 /* */ 413 414 #define RF_RX_G1 0x1A /* */ 415 #define RF_RX_G2 0x1B /* */ 416 417 #define RF_RX_BB2 0x1C /* */ 418 #define RF_RX_BB1 0x1D /* */ 419 420 #define RF_RCK1 0x1E /* */ 421 #define RF_RCK2 0x1F /* */ 422 423 #define RF_TX_G1 0x20 /* */ 424 #define RF_TX_G2 0x21 /* */ 425 #define RF_TX_G3 0x22 /* */ 426 427 #define RF_TX_BB1 0x23 /* */ 428 429 #define RF_T_METER_8192E 0x42 /* */ 430 #define RF_T_METER_88E 0x42 431 #define RF_T_METER 0x24 /* */ 432 433 /* #endif */ 434 435 #define RF_SYN_G1 0x25 /* RF TX Power control */ 436 #define RF_SYN_G2 0x26 /* RF TX Power control */ 437 #define RF_SYN_G3 0x27 /* RF TX Power control */ 438 #define RF_SYN_G4 0x28 /* RF TX Power control */ 439 #define RF_SYN_G5 0x29 /* RF TX Power control */ 440 #define RF_SYN_G6 0x2A /* RF TX Power control */ 441 #define RF_SYN_G7 0x2B /* RF TX Power control */ 442 #define RF_SYN_G8 0x2C /* RF TX Power control */ 443 444 #define RF_RCK_OS 0x30 /* RF TX PA control */ 445 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 446 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 447 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 448 #define RF_TX_BIAS_A 0x35 449 #define RF_TX_BIAS_D 0x36 450 #define RF_LOBF_9 0x38 451 #define RF_RXRF_A3 0x3C /* */ 452 #define RF_TRSW 0x3F 453 454 #define RF_TXRF_A2 0x41 455 #define RF_TXPA_G4 0x46 456 #define RF_TXPA_A4 0x4B 457 #define RF_0x52 0x52 458 #define RF_LDO 0xB1 459 #define RF_WE_LUT 0xEF 460 461 462 /* 463 * Bit Mask 464 * 465 * 1. Page1(0x100) */ 466 #define bBBResetB 0x100 /* Useless now? */ 467 #define bGlobalResetB 0x200 468 #define bOFDMTxStart 0x4 469 #define bCCKTxStart 0x8 470 #define bCRC32Debug 0x100 471 #define bPMACLoopback 0x10 472 #define bTxLSIG 0xffffff 473 #define bOFDMTxRate 0xf 474 #define bOFDMTxReserved 0x10 475 #define bOFDMTxLength 0x1ffe0 476 #define bOFDMTxParity 0x20000 477 #define bTxHTSIG1 0xffffff 478 #define bTxHTMCSRate 0x7f 479 #define bTxHTBW 0x80 480 #define bTxHTLength 0xffff00 481 #define bTxHTSIG2 0xffffff 482 #define bTxHTSmoothing 0x1 483 #define bTxHTSounding 0x2 484 #define bTxHTReserved 0x4 485 #define bTxHTAggreation 0x8 486 #define bTxHTSTBC 0x30 487 #define bTxHTAdvanceCoding 0x40 488 #define bTxHTShortGI 0x80 489 #define bTxHTNumberHT_LTF 0x300 490 #define bTxHTCRC8 0x3fc00 491 #define bCounterReset 0x10000 492 #define bNumOfOFDMTx 0xffff 493 #define bNumOfCCKTx 0xffff0000 494 #define bTxIdleInterval 0xffff 495 #define bOFDMService 0xffff0000 496 #define bTxMACHeader 0xffffffff 497 #define bTxDataInit 0xff 498 #define bTxHTMode 0x100 499 #define bTxDataType 0x30000 500 #define bTxRandomSeed 0xffffffff 501 #define bCCKTxPreamble 0x1 502 #define bCCKTxSFD 0xffff0000 503 #define bCCKTxSIG 0xff 504 #define bCCKTxService 0xff00 505 #define bCCKLengthExt 0x8000 506 #define bCCKTxLength 0xffff0000 507 #define bCCKTxCRC16 0xffff 508 #define bCCKTxStatus 0x1 509 #define bOFDMTxStatus 0x2 510 511 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 512 #define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 513 514 515 /* 2. Page8(0x800) */ 516 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 517 #define bJapanMode 0x2 518 #define bCCKTxSC 0x30 519 #define bCCKEn 0x1000000 520 #define bOFDMEn 0x2000000 521 522 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 523 #define bOFDMTxDACPhase 0x40000 524 #define bXATxAGC 0x3f 525 526 #define bAntennaSelect 0x0300 527 528 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 529 #define bXCTxAGC 0xf000 530 #define bXDTxAGC 0xf0000 531 532 #define bPAStart 0xf0000000 /* Useless now */ 533 #define bTRStart 0x00f00000 534 #define bRFStart 0x0000f000 535 #define bBBStart 0x000000f0 536 #define bBBCCKStart 0x0000000f 537 #define bPAEnd 0xf /* Reg0x814 */ 538 #define bTREnd 0x0f000000 539 #define bRFEnd 0x000f0000 540 #define bCCAMask 0x000000f0 /* T2R */ 541 #define bR2RCCAMask 0x00000f00 542 #define bHSSI_R2TDelay 0xf8000000 543 #define bHSSI_T2RDelay 0xf80000 544 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 545 #define bIGFromCCK 0x200 546 #define bAGCAddress 0x3f 547 #define bRxHPTx 0x7000 548 #define bRxHPT2R 0x38000 549 #define bRxHPCCKIni 0xc0000 550 #define bAGCTxCode 0xc00000 551 #define bAGCRxCode 0x300000 552 553 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 554 #define b3WireAddressLength 0x400 555 556 #define b3WireRFPowerDown 0x1 /* Useless now 557 * #define bHWSISelect 0x8 */ 558 #define b5GPAPEPolarity 0x40000000 559 #define b2GPAPEPolarity 0x80000000 560 #define bRFSW_TxDefaultAnt 0x3 561 #define bRFSW_TxOptionAnt 0x30 562 #define bRFSW_RxDefaultAnt 0x300 563 #define bRFSW_RxOptionAnt 0x3000 564 #define bRFSI_3WireData 0x1 565 #define bRFSI_3WireClock 0x2 566 #define bRFSI_3WireLoad 0x4 567 #define bRFSI_3WireRW 0x8 568 #define bRFSI_3Wire 0xf 569 570 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 571 572 #define bRFSI_TRSW 0x20 /* Useless now */ 573 #define bRFSI_TRSWB 0x40 574 #define bRFSI_ANTSW 0x100 575 #define bRFSI_ANTSWB 0x200 576 #define bRFSI_PAPE 0x400 577 #define bRFSI_PAPE5G 0x800 578 #define bBandSelect 0x1 579 #define bHTSIG2_GI 0x80 580 #define bHTSIG2_Smoothing 0x01 581 #define bHTSIG2_Sounding 0x02 582 #define bHTSIG2_Aggreaton 0x08 583 #define bHTSIG2_STBC 0x30 584 #define bHTSIG2_AdvCoding 0x40 585 #define bHTSIG2_NumOfHTLTF 0x300 586 #define bHTSIG2_CRC8 0x3fc 587 #define bHTSIG1_MCS 0x7f 588 #define bHTSIG1_BandWidth 0x80 589 #define bHTSIG1_HTLength 0xffff 590 #define bLSIG_Rate 0xf 591 #define bLSIG_Reserved 0x10 592 #define bLSIG_Length 0x1fffe 593 #define bLSIG_Parity 0x20 594 #define bCCKRxPhase 0x4 595 596 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 597 598 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 599 600 #define bLSSIReadBackData 0xfffff /* T65 RF */ 601 602 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 603 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 604 #define bRegulator0Standby 0x1 605 #define bRegulatorPLLStandby 0x2 606 #define bRegulator1Standby 0x4 607 #define bPLLPowerUp 0x8 608 #define bDPLLPowerUp 0x10 609 #define bDA10PowerUp 0x20 610 #define bAD7PowerUp 0x200 611 #define bDA6PowerUp 0x2000 612 #define bXtalPowerUp 0x4000 613 #define b40MDClkPowerUP 0x8000 614 #define bDA6DebugMode 0x20000 615 #define bDA6Swing 0x380000 616 617 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 618 619 #define b80MClkDelay 0x18000000 /* Useless */ 620 #define bAFEWatchDogEnable 0x20000000 621 622 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 623 #define bXtalCap23 0x3 624 #define bXtalCap92x 0x0f000000 625 #define bXtalCap 0x0f000000 626 627 #define bIntDifClkEnable 0x400 /* Useless */ 628 #define bExtSigClkEnable 0x800 629 #define bBandgapMbiasPowerUp 0x10000 630 #define bAD11SHGain 0xc0000 631 #define bAD11InputRange 0x700000 632 #define bAD11OPCurrent 0x3800000 633 #define bIPathLoopback 0x4000000 634 #define bQPathLoopback 0x8000000 635 #define bAFELoopback 0x10000000 636 #define bDA10Swing 0x7e0 637 #define bDA10Reverse 0x800 638 #define bDAClkSource 0x1000 639 #define bAD7InputRange 0x6000 640 #define bAD7Gain 0x38000 641 #define bAD7OutputCMMode 0x40000 642 #define bAD7InputCMMode 0x380000 643 #define bAD7Current 0xc00000 644 #define bRegulatorAdjust 0x7000000 645 #define bAD11PowerUpAtTx 0x1 646 #define bDA10PSAtTx 0x10 647 #define bAD11PowerUpAtRx 0x100 648 #define bDA10PSAtRx 0x1000 649 #define bCCKRxAGCFormat 0x200 650 #define bPSDFFTSamplepPoint 0xc000 651 #define bPSDAverageNum 0x3000 652 #define bIQPathControl 0xc00 653 #define bPSDFreq 0x3ff 654 #define bPSDAntennaPath 0x30 655 #define bPSDIQSwitch 0x40 656 #define bPSDRxTrigger 0x400000 657 #define bPSDTxTrigger 0x80000000 658 #define bPSDSineToneScale 0x7f000000 659 #define bPSDReport 0xffff 660 661 /* 3. Page9(0x900) */ 662 #define bOFDMTxSC 0x30000000 /* Useless */ 663 #define bCCKTxOn 0x1 664 #define bOFDMTxOn 0x2 665 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 666 #define bDebugItem 0xff /* reset debug page and LWord */ 667 #define bAntL 0x10 668 #define bAntNonHT 0x100 669 #define bAntHT1 0x1000 670 #define bAntHT2 0x10000 671 #define bAntHT1S1 0x100000 672 #define bAntNonHTS1 0x1000000 673 674 /* 4. PageA(0xA00) */ 675 #define bCCKBBMode 0x3 /* Useless */ 676 #define bCCKTxPowerSaving 0x80 677 #define bCCKRxPowerSaving 0x40 678 679 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 680 681 #define bCCKScramble 0x8 /* Useless */ 682 #define bCCKAntDiversity 0x8000 683 #define bCCKCarrierRecovery 0x4000 684 #define bCCKTxRate 0x3000 685 #define bCCKDCCancel 0x0800 686 #define bCCKISICancel 0x0400 687 #define bCCKMatchFilter 0x0200 688 #define bCCKEqualizer 0x0100 689 #define bCCKPreambleDetect 0x800000 690 #define bCCKFastFalseCCA 0x400000 691 #define bCCKChEstStart 0x300000 692 #define bCCKCCACount 0x080000 693 #define bCCKcs_lim 0x070000 694 #define bCCKBistMode 0x80000000 695 #define bCCKCCAMask 0x40000000 696 #define bCCKTxDACPhase 0x4 697 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 698 #define bCCKr_cp_mode0 0x0100 699 #define bCCKTxDCOffset 0xf0 700 #define bCCKRxDCOffset 0xf 701 #define bCCKCCAMode 0xc000 702 #define bCCKFalseCS_lim 0x3f00 703 #define bCCKCS_ratio 0xc00000 704 #define bCCKCorgBit_sel 0x300000 705 #define bCCKPD_lim 0x0f0000 706 #define bCCKNewCCA 0x80000000 707 #define bCCKRxHPofIG 0x8000 708 #define bCCKRxIG 0x7f00 709 #define bCCKLNAPolarity 0x800000 710 #define bCCKRx1stGain 0x7f0000 711 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 712 #define bCCKRxAGCSatLevel 0x1f000000 713 #define bCCKRxAGCSatCount 0xe0 714 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 715 #define bCCKFixedRxAGC 0x8000 716 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 717 #define bCCKAntennaPolarity 0x2000 718 #define bCCKTxFilterType 0x0c00 719 #define bCCKRxAGCReportType 0x0300 720 #define bCCKRxDAGCEn 0x80000000 721 #define bCCKRxDAGCPeriod 0x20000000 722 #define bCCKRxDAGCSatLevel 0x1f000000 723 #define bCCKTimingRecovery 0x800000 724 #define bCCKTxC0 0x3f0000 725 #define bCCKTxC1 0x3f000000 726 #define bCCKTxC2 0x3f 727 #define bCCKTxC3 0x3f00 728 #define bCCKTxC4 0x3f0000 729 #define bCCKTxC5 0x3f000000 730 #define bCCKTxC6 0x3f 731 #define bCCKTxC7 0x3f00 732 #define bCCKDebugPort 0xff0000 733 #define bCCKDACDebug 0x0f000000 734 #define bCCKFalseAlarmEnable 0x8000 735 #define bCCKFalseAlarmRead 0x4000 736 #define bCCKTRSSI 0x7f 737 #define bCCKRxAGCReport 0xfe 738 #define bCCKRxReport_AntSel 0x80000000 739 #define bCCKRxReport_MFOff 0x40000000 740 #define bCCKRxRxReport_SQLoss 0x20000000 741 #define bCCKRxReport_Pktloss 0x10000000 742 #define bCCKRxReport_Lockedbit 0x08000000 743 #define bCCKRxReport_RateError 0x04000000 744 #define bCCKRxReport_RxRate 0x03000000 745 #define bCCKRxFACounterLower 0xff 746 #define bCCKRxFACounterUpper 0xff000000 747 #define bCCKRxHPAGCStart 0xe000 748 #define bCCKRxHPAGCFinal 0x1c00 749 #define bCCKRxFalseAlarmEnable 0x8000 750 #define bCCKFACounterFreeze 0x4000 751 #define bCCKTxPathSel 0x10000000 752 #define bCCKDefaultRxPath 0xc000000 753 #define bCCKOptionRxPath 0x3000000 754 755 /* 5. PageC(0xC00) */ 756 #define bNumOfSTF 0x3 /* Useless */ 757 #define bShift_L 0xc0 758 #define bGI_TH 0xc 759 #define bRxPathA 0x1 760 #define bRxPathB 0x2 761 #define bRxPathC 0x4 762 #define bRxPathD 0x8 763 #define bTxPathA 0x1 764 #define bTxPathB 0x2 765 #define bTxPathC 0x4 766 #define bTxPathD 0x8 767 #define bTRSSIFreq 0x200 768 #define bADCBackoff 0x3000 769 #define bDFIRBackoff 0xc000 770 #define bTRSSILatchPhase 0x10000 771 #define bRxIDCOffset 0xff 772 #define bRxQDCOffset 0xff00 773 #define bRxDFIRMode 0x1800000 774 #define bRxDCNFType 0xe000000 775 #define bRXIQImb_A 0x3ff 776 #define bRXIQImb_B 0xfc00 777 #define bRXIQImb_C 0x3f0000 778 #define bRXIQImb_D 0xffc00000 779 #define bDC_dc_Notch 0x60000 780 #define bRxNBINotch 0x1f000000 781 #define bPD_TH 0xf 782 #define bPD_TH_Opt2 0xc000 783 #define bPWED_TH 0x700 784 #define bIfMF_Win_L 0x800 785 #define bPD_Option 0x1000 786 #define bMF_Win_L 0xe000 787 #define bBW_Search_L 0x30000 788 #define bwin_enh_L 0xc0000 789 #define bBW_TH 0x700000 790 #define bED_TH2 0x3800000 791 #define bBW_option 0x4000000 792 #define bRatio_TH 0x18000000 793 #define bWindow_L 0xe0000000 794 #define bSBD_Option 0x1 795 #define bFrame_TH 0x1c 796 #define bFS_Option 0x60 797 #define bDC_Slope_check 0x80 798 #define bFGuard_Counter_DC_L 0xe00 799 #define bFrame_Weight_Short 0x7000 800 #define bSub_Tune 0xe00000 801 #define bFrame_DC_Length 0xe000000 802 #define bSBD_start_offset 0x30000000 803 #define bFrame_TH_2 0x7 804 #define bFrame_GI2_TH 0x38 805 #define bGI2_Sync_en 0x40 806 #define bSarch_Short_Early 0x300 807 #define bSarch_Short_Late 0xc00 808 #define bSarch_GI2_Late 0x70000 809 #define bCFOAntSum 0x1 810 #define bCFOAcc 0x2 811 #define bCFOStartOffset 0xc 812 #define bCFOLookBack 0x70 813 #define bCFOSumWeight 0x80 814 #define bDAGCEnable 0x10000 815 #define bTXIQImb_A 0x3ff 816 #define bTXIQImb_B 0xfc00 817 #define bTXIQImb_C 0x3f0000 818 #define bTXIQImb_D 0xffc00000 819 #define bTxIDCOffset 0xff 820 #define bTxQDCOffset 0xff00 821 #define bTxDFIRMode 0x10000 822 #define bTxPesudoNoiseOn 0x4000000 823 #define bTxPesudoNoise_A 0xff 824 #define bTxPesudoNoise_B 0xff00 825 #define bTxPesudoNoise_C 0xff0000 826 #define bTxPesudoNoise_D 0xff000000 827 #define bCCADropOption 0x20000 828 #define bCCADropThres 0xfff00000 829 #define bEDCCA_H 0xf 830 #define bEDCCA_L 0xf0 831 #define bLambda_ED 0x300 832 #define bRxInitialGain 0x7f 833 #define bRxAntDivEn 0x80 834 #define bRxAGCAddressForLNA 0x7f00 835 #define bRxHighPowerFlow 0x8000 836 #define bRxAGCFreezeThres 0xc0000 837 #define bRxFreezeStep_AGC1 0x300000 838 #define bRxFreezeStep_AGC2 0xc00000 839 #define bRxFreezeStep_AGC3 0x3000000 840 #define bRxFreezeStep_AGC0 0xc000000 841 #define bRxRssi_Cmp_En 0x10000000 842 #define bRxQuickAGCEn 0x20000000 843 #define bRxAGCFreezeThresMode 0x40000000 844 #define bRxOverFlowCheckType 0x80000000 845 #define bRxAGCShift 0x7f 846 #define bTRSW_Tri_Only 0x80 847 #define bPowerThres 0x300 848 #define bRxAGCEn 0x1 849 #define bRxAGCTogetherEn 0x2 850 #define bRxAGCMin 0x4 851 #define bRxHP_Ini 0x7 852 #define bRxHP_TRLNA 0x70 853 #define bRxHP_RSSI 0x700 854 #define bRxHP_BBP1 0x7000 855 #define bRxHP_BBP2 0x70000 856 #define bRxHP_BBP3 0x700000 857 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 858 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 859 #define bRxSettle_TRSW 0x7 860 #define bRxSettle_LNA 0x38 861 #define bRxSettle_RSSI 0x1c0 862 #define bRxSettle_BBP 0xe00 863 #define bRxSettle_RxHP 0x7000 864 #define bRxSettle_AntSW_RSSI 0x38000 865 #define bRxSettle_AntSW 0xc0000 866 #define bRxProcessTime_DAGC 0x300000 867 #define bRxSettle_HSSI 0x400000 868 #define bRxProcessTime_BBPPW 0x800000 869 #define bRxAntennaPowerShift 0x3000000 870 #define bRSSITableSelect 0xc000000 871 #define bRxHP_Final 0x7000000 872 #define bRxHTSettle_BBP 0x7 873 #define bRxHTSettle_HSSI 0x8 874 #define bRxHTSettle_RxHP 0x70 875 #define bRxHTSettle_BBPPW 0x80 876 #define bRxHTSettle_Idle 0x300 877 #define bRxHTSettle_Reserved 0x1c00 878 #define bRxHTRxHPEn 0x8000 879 #define bRxHTAGCFreezeThres 0x30000 880 #define bRxHTAGCTogetherEn 0x40000 881 #define bRxHTAGCMin 0x80000 882 #define bRxHTAGCEn 0x100000 883 #define bRxHTDAGCEn 0x200000 884 #define bRxHTRxHP_BBP 0x1c00000 885 #define bRxHTRxHP_Final 0xe0000000 886 #define bRxPWRatioTH 0x3 887 #define bRxPWRatioEn 0x4 888 #define bRxMFHold 0x3800 889 #define bRxPD_Delay_TH1 0x38 890 #define bRxPD_Delay_TH2 0x1c0 891 #define bRxPD_DC_COUNT_MAX 0x600 892 /* #define bRxMF_Hold 0x3800 */ 893 #define bRxPD_Delay_TH 0x8000 894 #define bRxProcess_Delay 0xf0000 895 #define bRxSearchrange_GI2_Early 0x700000 896 #define bRxFrame_Guard_Counter_L 0x3800000 897 #define bRxSGI_Guard_L 0xc000000 898 #define bRxSGI_Search_L 0x30000000 899 #define bRxSGI_TH 0xc0000000 900 #define bDFSCnt0 0xff 901 #define bDFSCnt1 0xff00 902 #define bDFSFlag 0xf0000 903 #define bMFWeightSum 0x300000 904 #define bMinIdxTH 0x7f000000 905 #define bDAFormat 0x40000 906 #define bTxChEmuEnable 0x01000000 907 #define bTRSWIsolation_A 0x7f 908 #define bTRSWIsolation_B 0x7f00 909 #define bTRSWIsolation_C 0x7f0000 910 #define bTRSWIsolation_D 0x7f000000 911 #define bExtLNAGain 0x7c00 912 913 /* 6. PageE(0xE00) */ 914 #define bSTBCEn 0x4 /* Useless */ 915 #define bAntennaMapping 0x10 916 #define bNss 0x20 917 #define bCFOAntSumD 0x200 918 #define bPHYCounterReset 0x8000000 919 #define bCFOReportGet 0x4000000 920 #define bOFDMContinueTx 0x10000000 921 #define bOFDMSingleCarrier 0x20000000 922 #define bOFDMSingleTone 0x40000000 923 /* #define bRxPath1 0x01 */ 924 /* #define bRxPath2 0x02 */ 925 /* #define bRxPath3 0x04 */ 926 /* #define bRxPath4 0x08 */ 927 /* #define bTxPath1 0x10 */ 928 /* #define bTxPath2 0x20 */ 929 #define bHTDetect 0x100 930 #define bCFOEn 0x10000 931 #define bCFOValue 0xfff00000 932 #define bSigTone_Re 0x3f 933 #define bSigTone_Im 0x7f00 934 #define bCounter_CCA 0xffff 935 #define bCounter_ParityFail 0xffff0000 936 #define bCounter_RateIllegal 0xffff 937 #define bCounter_CRC8Fail 0xffff0000 938 #define bCounter_MCSNoSupport 0xffff 939 #define bCounter_FastSync 0xffff 940 #define bShortCFO 0xfff 941 #define bShortCFOTLength 12 /* total */ 942 #define bShortCFOFLength 11 /* fraction */ 943 #define bLongCFO 0x7ff 944 #define bLongCFOTLength 11 945 #define bLongCFOFLength 11 946 #define bTailCFO 0x1fff 947 #define bTailCFOTLength 13 948 #define bTailCFOFLength 12 949 #define bmax_en_pwdB 0xffff 950 #define bCC_power_dB 0xffff0000 951 #define bnoise_pwdB 0xffff 952 #define bPowerMeasTLength 10 953 #define bPowerMeasFLength 3 954 #define bRx_HT_BW 0x1 955 #define bRxSC 0x6 956 #define bRx_HT 0x8 957 #define bNB_intf_det_on 0x1 958 #define bIntf_win_len_cfg 0x30 959 #define bNB_Intf_TH_cfg 0x1c0 960 #define bRFGain 0x3f 961 #define bTableSel 0x40 962 #define bTRSW 0x80 963 #define bRxSNR_A 0xff 964 #define bRxSNR_B 0xff00 965 #define bRxSNR_C 0xff0000 966 #define bRxSNR_D 0xff000000 967 #define bSNREVMTLength 8 968 #define bSNREVMFLength 1 969 #define bCSI1st 0xff 970 #define bCSI2nd 0xff00 971 #define bRxEVM1st 0xff0000 972 #define bRxEVM2nd 0xff000000 973 #define bSIGEVM 0xff 974 #define bPWDB 0xff00 975 #define bSGIEN 0x10000 976 977 #define bSFactorQAM1 0xf /* Useless */ 978 #define bSFactorQAM2 0xf0 979 #define bSFactorQAM3 0xf00 980 #define bSFactorQAM4 0xf000 981 #define bSFactorQAM5 0xf0000 982 #define bSFactorQAM6 0xf0000 983 #define bSFactorQAM7 0xf00000 984 #define bSFactorQAM8 0xf000000 985 #define bSFactorQAM9 0xf0000000 986 #define bCSIScheme 0x100000 987 988 #define bNoiseLvlTopSet 0x3 /* Useless */ 989 #define bChSmooth 0x4 990 #define bChSmoothCfg1 0x38 991 #define bChSmoothCfg2 0x1c0 992 #define bChSmoothCfg3 0xe00 993 #define bChSmoothCfg4 0x7000 994 #define bMRCMode 0x800000 995 #define bTHEVMCfg 0x7000000 996 997 #define bLoopFitType 0x1 /* Useless */ 998 #define bUpdCFO 0x40 999 #define bUpdCFOOffData 0x80 1000 #define bAdvUpdCFO 0x100 1001 #define bAdvTimeCtrl 0x800 1002 #define bUpdClko 0x1000 1003 #define bFC 0x6000 1004 #define bTrackingMode 0x8000 1005 #define bPhCmpEnable 0x10000 1006 #define bUpdClkoLTF 0x20000 1007 #define bComChCFO 0x40000 1008 #define bCSIEstiMode 0x80000 1009 #define bAdvUpdEqz 0x100000 1010 #define bUChCfg 0x7000000 1011 #define bUpdEqz 0x8000000 1012 1013 /* Rx Pseduo noise */ 1014 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1015 #define bRxPesudoNoise_A 0xff 1016 #define bRxPesudoNoise_B 0xff00 1017 #define bRxPesudoNoise_C 0xff0000 1018 #define bRxPesudoNoise_D 0xff000000 1019 #define bPesudoNoiseState_A 0xffff 1020 #define bPesudoNoiseState_B 0xffff0000 1021 #define bPesudoNoiseState_C 0xffff 1022 #define bPesudoNoiseState_D 0xffff0000 1023 1024 /* 7. RF Register 1025 * Zebra1 */ 1026 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1027 #define bZebra1_TRxControl 0xc00 1028 #define bZebra1_TRxGainSetting 0x07f 1029 #define bZebra1_RxCorner 0xc00 1030 #define bZebra1_TxChargePump 0x38 1031 #define bZebra1_RxChargePump 0x7 1032 #define bZebra1_ChannelNum 0xf80 1033 #define bZebra1_TxLPFBW 0x400 1034 #define bZebra1_RxLPFBW 0x600 1035 1036 /* Zebra4 */ 1037 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1038 #define bRTL8256RegModeCtrl0 0x40 1039 #define bRTL8256_TxLPFBW 0x18 1040 #define bRTL8256_RxLPFBW 0x600 1041 1042 /* RTL8258 */ 1043 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1044 #define bRTL8258_RxLPFBW 0xc00 1045 #define bRTL8258_RSSILPFBW 0xc0 1046 1047 1048 /* 1049 * Other Definition 1050 * */ 1051 1052 /* byte endable for sb_write */ 1053 #define bByte0 0x1 /* Useless */ 1054 #define bByte1 0x2 1055 #define bByte2 0x4 1056 #define bByte3 0x8 1057 #define bWord0 0x3 1058 #define bWord1 0xc 1059 #define bDWord 0xf 1060 1061 /* for PutRegsetting & GetRegSetting BitMask */ 1062 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1063 #define bMaskByte1 0xff00 1064 #define bMaskByte2 0xff0000 1065 #define bMaskByte3 0xff000000 1066 #define bMaskHWord 0xffff0000 1067 #define bMaskLWord 0x0000ffff 1068 #define bMaskDWord 0xffffffff 1069 #define bMaskH3Bytes 0xffffff00 1070 #define bMask12Bits 0xfff 1071 #define bMaskH4Bits 0xf0000000 1072 #define bMaskOFDM_D 0xffc00000 1073 #define bMaskCCK 0x3f3f3f3f 1074 1075 /* for PutRFRegsetting & GetRFRegSetting BitMask 1076 * #define bMask12Bits 0xfffff */ /* RF Reg mask bits 1077 * #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ 1078 #define bRFRegOffsetMask 0xfffff 1079 1080 #define bEnable 0x1 /* Useless */ 1081 #define bDisable 0x0 1082 1083 #define LeftAntenna 0x0 /* Useless */ 1084 #define RightAntenna 0x1 1085 1086 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1087 #define tUpdateRxCounter 100 /* 100ms */ 1088 1089 #define rateCCK 0 /* Useless */ 1090 #define rateOFDM 1 1091 #define rateHT 2 1092 1093 /* define Register-End */ 1094 #define bPMAC_End 0x1ff /* Useless */ 1095 #define bFPGAPHY0_End 0x8ff 1096 #define bFPGAPHY1_End 0x9ff 1097 #define bCCKPHY0_End 0xaff 1098 #define bOFDMPHY0_End 0xcff 1099 #define bOFDMPHY1_End 0xdff 1100 1101 /* define max debug item in each debug page 1102 * #define bMaxItem_FPGA_PHY0 0x9 1103 * #define bMaxItem_FPGA_PHY1 0x3 1104 * #define bMaxItem_PHY_11B 0x16 1105 * #define bMaxItem_OFDM_PHY0 0x29 1106 * #define bMaxItem_OFDM_PHY1 0x0 */ 1107 1108 #define bPMACControl 0x0 /* Useless */ 1109 #define bWMACControl 0x1 1110 #define bWNICControl 0x2 1111 1112 #define PathA 0x0 /* Useless */ 1113 #define PathB 0x1 1114 #define PathC 0x2 1115 #define PathD 0x3 1116 1117 1118 /* RSSI Dump Message */ 1119 #define rA_RSSIDump_92E 0xcb0 1120 #define rB_RSSIDump_92E 0xcb1 1121 #define rS1_RXevmDump_92E 0xcb2 1122 #define rS2_RXevmDump_92E 0xcb3 1123 #define rA_RXsnrDump_92E 0xcb4 1124 #define rB_RXsnrDump_92E 0xcb5 1125 #define rA_CfoShortDump_92E 0xcb6 1126 #define rB_CfoShortDump_92E 0xcb8 1127 #define rA_CfoLongDump_92E 0xcba 1128 #define rB_CfoLongDump_92E 0xcbc 1129 1130 /*--------------------------Define Parameters-------------------------------*/ 1131 1132 1133 #endif /* __INC_HAL8188EPHYREG_H */ 1134