1 /* SPDX-License-Identifier: GPL-2.0 */
2 //============================================================
3 // Description:
4 //
5 // This file is for 92D BT 2 Antenna Co-exist mechanism
6 //
7 // By cosa 02/11/2011
8 //
9 //============================================================
10
11 //============================================================
12 // include files
13 //============================================================
14 #include "Mp_Precomp.h"
15
16 #if WPP_SOFTWARE_TRACE
17 #include "HalBtc8192d2Ant.tmh"
18 #endif
19
20 #if(BT_30_SUPPORT == 1)
21 //============================================================
22 // Global variables, these are static variables
23 //============================================================
24 static COEX_DM_8192D_2ANT GLCoexDm8192d2Ant;
25 static PCOEX_DM_8192D_2ANT pCoexDm=&GLCoexDm8192d2Ant;
26 static COEX_STA_8192D_2ANT GLCoexSta8192d2Ant;
27 static PCOEX_STA_8192D_2ANT pCoexSta=&GLCoexSta8192d2Ant;
28
29 //============================================================
30 // local function start with btdm_
31 //============================================================
32 u1Byte
halbtc8192d2ant_WifiRssiState(IN PBTC_COEXIST pBtCoexist,IN u1Byte index,IN u1Byte levelNum,IN u1Byte rssiThresh,IN u1Byte rssiThresh1)33 halbtc8192d2ant_WifiRssiState(
34 IN PBTC_COEXIST pBtCoexist,
35 IN u1Byte index,
36 IN u1Byte levelNum,
37 IN u1Byte rssiThresh,
38 IN u1Byte rssiThresh1
39 )
40 {
41 s4Byte wifiRssi=0;
42 u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
43
44 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
45
46 if(levelNum == 2)
47 {
48 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
49 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
50 {
51 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
52 {
53 wifiRssiState = BTC_RSSI_STATE_HIGH;
54 }
55 else
56 {
57 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
58 }
59 }
60 else
61 {
62 if(wifiRssi < rssiThresh)
63 {
64 wifiRssiState = BTC_RSSI_STATE_LOW;
65 }
66 else
67 {
68 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
69 }
70 }
71 }
72 else if(levelNum == 3)
73 {
74 if(rssiThresh > rssiThresh1)
75 {
76 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n"));
77 return pCoexSta->preWifiRssiState[index];
78 }
79
80 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
81 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
82 {
83 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
84 {
85 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
86 }
87 else
88 {
89 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
90 }
91 }
92 else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
93 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
94 {
95 if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
96 {
97 wifiRssiState = BTC_RSSI_STATE_HIGH;
98 }
99 else if(wifiRssi < rssiThresh)
100 {
101 wifiRssiState = BTC_RSSI_STATE_LOW;
102 }
103 else
104 {
105 wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
106 }
107 }
108 else
109 {
110 if(wifiRssi < rssiThresh1)
111 {
112 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
113 }
114 else
115 {
116 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
117 }
118 }
119 }
120
121 pCoexSta->preWifiRssiState[index] = wifiRssiState;
122
123 return wifiRssiState;
124 }
125
126 u1Byte
halbtc8192d2ant_ActionAlgorithm(IN PBTC_COEXIST pBtCoexist)127 halbtc8192d2ant_ActionAlgorithm(
128 IN PBTC_COEXIST pBtCoexist
129 )
130 {
131 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
132 BOOLEAN bBtHsOn=FALSE;
133 u1Byte algorithm=BT_8192D_2ANT_COEX_ALGO_UNDEFINED;
134 u1Byte numOfDiffProfile=0;
135
136 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
137
138 if(!pStackInfo->bBtLinkExist)
139 {
140 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n"));
141 return algorithm;
142 }
143
144 if(pStackInfo->bScoExist)
145 numOfDiffProfile++;
146 if(pStackInfo->bHidExist)
147 numOfDiffProfile++;
148 if(pStackInfo->bPanExist)
149 numOfDiffProfile++;
150 if(pStackInfo->bA2dpExist)
151 numOfDiffProfile++;
152
153 if(pStackInfo->bScoExist)
154 {
155 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n"));
156 algorithm = BT_8192D_2ANT_COEX_ALGO_SCO;
157 }
158 else
159 {
160 if(numOfDiffProfile == 1)
161 {
162 if(pStackInfo->bHidExist)
163 {
164 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n"));
165 algorithm = BT_8192D_2ANT_COEX_ALGO_HID;
166 }
167 else if(pStackInfo->bA2dpExist)
168 {
169 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n"));
170 algorithm = BT_8192D_2ANT_COEX_ALGO_A2DP;
171 }
172 else if(pStackInfo->bPanExist)
173 {
174 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n"));
175 algorithm = BT_8192D_2ANT_COEX_ALGO_PAN;
176 }
177 }
178 else
179 {
180 if( pStackInfo->bHidExist &&
181 pStackInfo->bA2dpExist )
182 {
183 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n"));
184 algorithm = BT_8192D_2ANT_COEX_ALGO_HID_A2DP;
185 }
186 else if( pStackInfo->bHidExist &&
187 pStackInfo->bPanExist )
188 {
189 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n"));
190 algorithm = BT_8192D_2ANT_COEX_ALGO_HID_PAN;
191 }
192 else if( pStackInfo->bPanExist &&
193 pStackInfo->bA2dpExist )
194 {
195 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n"));
196 algorithm = BT_8192D_2ANT_COEX_ALGO_PAN_A2DP;
197 }
198 }
199 }
200 return algorithm;
201 }
202
203 VOID
halbtc8192d2ant_SetFwBalance(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bBalanceOn,IN u1Byte ms0,IN u1Byte ms1)204 halbtc8192d2ant_SetFwBalance(
205 IN PBTC_COEXIST pBtCoexist,
206 IN BOOLEAN bBalanceOn,
207 IN u1Byte ms0,
208 IN u1Byte ms1
209 )
210 {
211 u1Byte H2C_Parameter[3] ={0};
212
213 if(bBalanceOn)
214 {
215 H2C_Parameter[2] = 1;
216 H2C_Parameter[1] = ms1;
217 H2C_Parameter[0] = ms0;
218 }
219 else
220 {
221 H2C_Parameter[2] = 0;
222 H2C_Parameter[1] = 0;
223 H2C_Parameter[0] = 0;
224 }
225
226 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
227 bBalanceOn?"ON":"OFF", ms0, ms1,
228 H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
229
230 pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter);
231 }
232
233 VOID
halbtc8192d2ant_Balance(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bBalanceOn,IN u1Byte ms0,IN u1Byte ms1)234 halbtc8192d2ant_Balance(
235 IN PBTC_COEXIST pBtCoexist,
236 IN BOOLEAN bForceExec,
237 IN BOOLEAN bBalanceOn,
238 IN u1Byte ms0,
239 IN u1Byte ms1
240 )
241 {
242 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n",
243 (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF")));
244 pCoexDm->bCurBalanceOn = bBalanceOn;
245
246 if(!bForceExec)
247 {
248 if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn)
249 return;
250 }
251 halbtc8192d2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1);
252
253 pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn;
254 }
255
256 VOID
halbtc8192d2ant_SetFwDiminishWifi(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bDacOn,IN BOOLEAN bInterruptOn,IN u1Byte fwDacSwingLvl,IN BOOLEAN bNavOn)257 halbtc8192d2ant_SetFwDiminishWifi(
258 IN PBTC_COEXIST pBtCoexist,
259 IN BOOLEAN bDacOn,
260 IN BOOLEAN bInterruptOn,
261 IN u1Byte fwDacSwingLvl,
262 IN BOOLEAN bNavOn
263 )
264 {
265 u1Byte H2C_Parameter[3] ={0};
266
267 if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20))
268 {
269 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n"));
270 fwDacSwingLvl = 0x18;
271 }
272
273 H2C_Parameter[2] = 0;
274 H2C_Parameter[1] = fwDacSwingLvl;
275 H2C_Parameter[0] = 0;
276 if(bDacOn)
277 {
278 H2C_Parameter[2] |= 0x01; //BIT0
279 if(bInterruptOn)
280 {
281 H2C_Parameter[2] |= 0x02; //BIT1
282 }
283 }
284 if(bNavOn)
285 {
286 H2C_Parameter[2] |= 0x08; //BIT3
287 }
288
289 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0x12=0x%x\n",
290 (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"),
291 (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])));
292 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x12, 3, H2C_Parameter);
293 }
294
295
296 VOID
halbtc8192d2ant_DiminishWifi(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bDacOn,IN BOOLEAN bInterruptOn,IN u1Byte fwDacSwingLvl,IN BOOLEAN bNavOn)297 halbtc8192d2ant_DiminishWifi(
298 IN PBTC_COEXIST pBtCoexist,
299 IN BOOLEAN bForceExec,
300 IN BOOLEAN bDacOn,
301 IN BOOLEAN bInterruptOn,
302 IN u1Byte fwDacSwingLvl,
303 IN BOOLEAN bNavOn
304 )
305 {
306 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n",
307 (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF")));
308
309 pCoexDm->bCurDacOn = bDacOn;
310 pCoexDm->bCurInterruptOn = bInterruptOn;
311 pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
312 pCoexDm->bCurNavOn = bNavOn;
313
314 if(!bForceExec)
315 {
316 if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) &&
317 (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) &&
318 (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) &&
319 (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) )
320 return;
321 }
322 halbtc8192d2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn);
323
324 pCoexDm->bPreDacOn = pCoexDm->bCurDacOn;
325 pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn;
326 pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
327 pCoexDm->bPreNavOn = pCoexDm->bCurNavOn;
328 }
329
330 VOID
halbtc8192d2ant_SetSwRfRxLpfCorner(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bRxRfShrinkOn)331 halbtc8192d2ant_SetSwRfRxLpfCorner(
332 IN PBTC_COEXIST pBtCoexist,
333 IN BOOLEAN bRxRfShrinkOn
334 )
335 {
336 if(bRxRfShrinkOn)
337 {
338 //Shrink RF Rx LPF corner
339 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
340 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf2ff7);
341 }
342 else
343 {
344 //Resume RF Rx LPF corner
345 // After initialized, we can use pCoexDm->btRf0x1eBackup
346 if(pBtCoexist->bInitilized)
347 {
348 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
349 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
350 }
351 }
352 }
353
354
355 VOID
halbtc8192d2ant_RfShrink(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bRxRfShrinkOn)356 halbtc8192d2ant_RfShrink(
357 IN PBTC_COEXIST pBtCoexist,
358 IN BOOLEAN bForceExec,
359 IN BOOLEAN bRxRfShrinkOn
360 )
361 {
362 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
363 (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
364 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
365
366 if(!bForceExec)
367 {
368 if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
369 return;
370 }
371 halbtc8192d2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
372
373 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
374 }
375
376 VOID
halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bLowPenaltyRa)377 halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(
378 IN PBTC_COEXIST pBtCoexist,
379 IN BOOLEAN bLowPenaltyRa
380 )
381 {
382 u1Byte tmpU1;
383
384 tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd);
385 if(bLowPenaltyRa)
386 {
387 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
388 tmpU1 &= ~BIT2;
389 }
390 else
391 {
392 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
393 tmpU1 |= BIT2;
394 }
395 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1);
396 }
397
398 VOID
halbtc8192d2ant_LowPenaltyRa(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bLowPenaltyRa)399 halbtc8192d2ant_LowPenaltyRa(
400 IN PBTC_COEXIST pBtCoexist,
401 IN BOOLEAN bForceExec,
402 IN BOOLEAN bLowPenaltyRa
403 )
404 {
405 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
406 (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
407 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
408
409 if(!bForceExec)
410 {
411 if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
412 return;
413 }
414 halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
415
416 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
417 }
418
419 VOID
halbtc8192d2ant_SetSwFullTimeDacSwing(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bSwDacSwingOn,IN u4Byte swDacSwingLvl)420 halbtc8192d2ant_SetSwFullTimeDacSwing(
421 IN PBTC_COEXIST pBtCoexist,
422 IN BOOLEAN bSwDacSwingOn,
423 IN u4Byte swDacSwingLvl
424 )
425 {
426 u4Byte dacSwingLvl;
427
428 if(bSwDacSwingOn)
429 {
430 if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20))
431 {
432 dacSwingLvl = 0x18;
433 }
434 else
435 {
436 dacSwingLvl = swDacSwingLvl;
437 }
438 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl);
439 }
440 else
441 {
442 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30);
443 }
444 }
445
446 VOID
halbtc8192d2ant_DacSwing(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bDacSwingOn,IN u4Byte dacSwingLvl)447 halbtc8192d2ant_DacSwing(
448 IN PBTC_COEXIST pBtCoexist,
449 IN BOOLEAN bForceExec,
450 IN BOOLEAN bDacSwingOn,
451 IN u4Byte dacSwingLvl
452 )
453 {
454 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
455 (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
456 pCoexDm->bCurDacSwingOn = bDacSwingOn;
457 pCoexDm->curDacSwingLvl = dacSwingLvl;
458
459 if(!bForceExec)
460 {
461 if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
462 (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
463 return;
464 }
465 delay_ms(30);
466 halbtc8192d2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
467
468 pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
469 pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
470 }
471
472 VOID
halbtc8192d2ant_SetAdcBackOff(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bAdcBackOff)473 halbtc8192d2ant_SetAdcBackOff(
474 IN PBTC_COEXIST pBtCoexist,
475 IN BOOLEAN bAdcBackOff
476 )
477 {
478 if(bAdcBackOff)
479 {
480 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n"));
481 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611);
482 }
483 else
484 {
485 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n"));
486 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611);
487 }
488 }
489
490 VOID
halbtc8192d2ant_AdcBackOff(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bAdcBackOff)491 halbtc8192d2ant_AdcBackOff(
492 IN PBTC_COEXIST pBtCoexist,
493 IN BOOLEAN bForceExec,
494 IN BOOLEAN bAdcBackOff
495 )
496 {
497 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n",
498 (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
499 pCoexDm->bCurAdcBackOff = bAdcBackOff;
500
501 if(!bForceExec)
502 {
503 if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
504 return;
505 }
506 halbtc8192d2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
507
508 pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
509 }
510
511 VOID
halbtc8192d2ant_SetAgcTable(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bAgcTableEn)512 halbtc8192d2ant_SetAgcTable(
513 IN PBTC_COEXIST pBtCoexist,
514 IN BOOLEAN bAgcTableEn
515 )
516 {
517 u1Byte rssiAdjustVal=0;
518
519 if(bAgcTableEn)
520 {
521 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n"));
522 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0xa99);
523 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xd4000);
524
525 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b000001);
526 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b010001);
527 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b020001);
528 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b030001);
529 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b040001);
530 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b050001);
531 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b060001);
532 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b070001);
533 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b080001);
534 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b090001);
535 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0A0001);
536 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0B0001);
537 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7a0C0001);
538 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x790D0001);
539 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x780E0001);
540 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770F0001);
541 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x76100001);
542 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x75110001);
543 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x74120001);
544 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x73130001);
545 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x72140001);
546 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71150001);
547 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70160001);
548 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6f170001);
549 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e180001);
550 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d190001);
551 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1A0001);
552 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1B0001);
553 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1C0001);
554 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691D0001);
555 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4f1E0001);
556 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4e1F0001);
557 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4d200001);
558 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4c210001);
559 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4b220001);
560 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4a230001);
561 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49240001);
562 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48250001);
563 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47260001);
564 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46270001);
565 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45280001);
566 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44290001);
567 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x432A0001);
568 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x422B0001);
569
570 rssiAdjustVal = 12;
571 }
572 else
573 {
574 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n"));
575 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30a99);
576 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000);
577
578 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B000001);
579 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B010001);
580 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B020001);
581 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B030001);
582 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B040001);
583 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B050001);
584 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B060001);
585 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7A070001);
586 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x79080001);
587 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x78090001);
588 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770A0001);
589 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x760B0001);
590 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x750C0001);
591 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x740D0001);
592 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x730E0001);
593 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x720F0001);
594 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71100001);
595 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70110001);
596 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6F120001);
597 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6E130001);
598 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6D140001);
599 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6C150001);
600 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6B160001);
601 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6A170001);
602 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x69180001);
603 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68190001);
604 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x671A0001);
605 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x661B0001);
606 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x651C0001);
607 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x641D0001);
608 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x631E0001);
609 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x621F0001);
610 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x61200001);
611 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x60210001);
612 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49220001);
613 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48230001);
614 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47240001);
615 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46250001);
616 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45260001);
617 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44270001);
618 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x43280001);
619 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x42290001);
620 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x412A0001);
621 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x402B0001);
622 }
623
624 // set rssiAdjustVal for wifi module.
625 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
626 }
627
628
629
630 VOID
halbtc8192d2ant_AgcTable(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN BOOLEAN bAgcTableEn)631 halbtc8192d2ant_AgcTable(
632 IN PBTC_COEXIST pBtCoexist,
633 IN BOOLEAN bForceExec,
634 IN BOOLEAN bAgcTableEn
635 )
636 {
637 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n",
638 (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
639 pCoexDm->bCurAgcTableEn = bAgcTableEn;
640
641 if(!bForceExec)
642 {
643 if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
644 return;
645 }
646 halbtc8192d2ant_SetAgcTable(pBtCoexist, bAgcTableEn);
647
648 pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
649 }
650
651 VOID
halbtc8192d2ant_SetCoexTable(IN PBTC_COEXIST pBtCoexist,IN u4Byte val0x6c4,IN u4Byte val0x6c8,IN u4Byte val0x6cc)652 halbtc8192d2ant_SetCoexTable(
653 IN PBTC_COEXIST pBtCoexist,
654 IN u4Byte val0x6c4,
655 IN u4Byte val0x6c8,
656 IN u4Byte val0x6cc
657 )
658 {
659 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4));
660 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4);
661
662 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
663 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8);
664
665 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
666 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc);
667 }
668
669 VOID
halbtc8192d2ant_CoexTable(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bForceExec,IN u4Byte val0x6c4,IN u4Byte val0x6c8,IN u4Byte val0x6cc)670 halbtc8192d2ant_CoexTable(
671 IN PBTC_COEXIST pBtCoexist,
672 IN BOOLEAN bForceExec,
673 IN u4Byte val0x6c4,
674 IN u4Byte val0x6c8,
675 IN u4Byte val0x6cc
676 )
677 {
678 RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
679 (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc));
680 pCoexDm->curVal0x6c4 = val0x6c4;
681 pCoexDm->curVal0x6c8 = val0x6c8;
682 pCoexDm->curVal0x6cc = val0x6cc;
683
684 if(!bForceExec)
685 {
686 if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) &&
687 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
688 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
689 return;
690 }
691 halbtc8192d2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc);
692
693 pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4;
694 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
695 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
696 }
697
698 VOID
halbtc8192d2ant_CoexAllOff(IN PBTC_COEXIST pBtCoexist)699 halbtc8192d2ant_CoexAllOff(
700 IN PBTC_COEXIST pBtCoexist
701 )
702 {
703 // fw mechanism
704 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
705 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
706
707 // sw mechanism
708 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
709 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
710 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
711 }
712 VOID
halbtc8192d2ant_InitCoexDm(IN PBTC_COEXIST pBtCoexist)713 halbtc8192d2ant_InitCoexDm(
714 IN PBTC_COEXIST pBtCoexist
715 )
716 {
717 }
718
719 VOID
halbtc8192d2ant_MonitorBtEnableDisable(IN PBTC_COEXIST pBtCoexist,IN u4Byte btActive)720 halbtc8192d2ant_MonitorBtEnableDisable(
721 IN PBTC_COEXIST pBtCoexist,
722 IN u4Byte btActive
723 )
724 {
725 static BOOLEAN bPreBtDisabled=FALSE;
726 static u4Byte btDisableCnt=0;
727 BOOLEAN bBtDisabled=FALSE, bForceToRoam=FALSE;
728 u4Byte u4Tmp=0;
729
730 // This function check if bt is disabled
731 if(btActive)
732 {
733 btDisableCnt = 0;
734 bBtDisabled = FALSE;
735 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
736 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n"));
737 }
738 else
739 {
740 btDisableCnt++;
741 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n",
742 btDisableCnt));
743 if(btDisableCnt >= 2)
744 {
745 bBtDisabled = TRUE;
746 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
747 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n"));
748 }
749 }
750 if(bPreBtDisabled != bBtDisabled)
751 {
752 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n",
753 (bPreBtDisabled ? "disabled":"enabled"),
754 (bBtDisabled ? "disabled":"enabled")));
755
756 bForceToRoam = TRUE;
757 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_FORCE_TO_ROAM, &bForceToRoam);
758
759 bPreBtDisabled = bBtDisabled;
760 }
761 }
762
763 VOID
halbtc8192d2ant_MonitorBtState(IN PBTC_COEXIST pBtCoexist)764 halbtc8192d2ant_MonitorBtState(
765 IN PBTC_COEXIST pBtCoexist
766 )
767 {
768 BOOLEAN stateChange=FALSE;
769 u4Byte BT_Polling, Ratio_Act, Ratio_STA;
770 u4Byte BT_Active, BT_State;
771 u4Byte regBTActive=0, regBTState=0, regBTPolling=0;
772 u4Byte btBusyThresh=0;
773 u4Byte fwVer=0;
774 static BOOLEAN bBtBusyTraffic=FALSE;
775 BOOLEAN bRejApAggPkt=FALSE;
776
777 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer);
778
779 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer));
780
781 regBTActive = 0x444;
782 regBTState = 0x448;
783 regBTPolling = 0x44c;
784
785 btBusyThresh = 40;
786
787 BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive);
788 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active));
789 BT_Active = BT_Active & 0x00ffffff;
790
791 BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState);
792 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State));
793 BT_State = BT_State & 0x00ffffff;
794
795 BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling);
796 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling));
797
798 if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff )
799 return;
800
801 // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running
802 // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f
803 // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to
804 // HW divide trap.
805 if (BT_Polling==0)
806 return;
807
808 halbtc8192d2ant_MonitorBtEnableDisable(pBtCoexist, BT_Active);
809
810 Ratio_Act = BT_Active*1000/BT_Polling;
811 Ratio_STA = BT_State*1000/BT_Polling;
812
813 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act));
814 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA));
815
816 if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
817 {
818 if(Ratio_STA < 60) // BT PAN idle
819 {
820 }
821 else
822 {
823 // Check if BT PAN (under BT 2.1) is uplink or downlink
824 if((Ratio_Act/Ratio_STA) < 2)
825 { // BT PAN Uplink
826 pCoexSta->bBtUplink = TRUE;
827 }
828 else
829 { // BT PAN downlink
830 pCoexSta->bBtUplink = FALSE;
831 }
832 }
833 }
834
835 // Check BT is idle or not
836 if(!pBtCoexist->stackInfo.bBtLinkExist)
837 {
838 pCoexSta->bBtBusy = FALSE;
839 }
840 else
841 {
842 if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
843 {
844 if(Ratio_Act<20)
845 {
846 pCoexSta->bBtBusy = FALSE;
847 }
848 else
849 {
850 pCoexSta->bBtBusy = TRUE;
851 }
852 }
853 else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
854 {
855 if(Ratio_STA < btBusyThresh)
856 {
857 pCoexSta->bBtBusy = FALSE;
858 }
859 else
860 {
861 pCoexSta->bBtBusy = TRUE;
862 }
863
864 if( (Ratio_STA < btBusyThresh) ||
865 (Ratio_Act<180 && Ratio_STA<130) )
866 {
867 pCoexSta->bA2dpBusy = FALSE;
868 }
869 else
870 {
871 pCoexSta->bA2dpBusy = TRUE;
872 }
873 }
874 }
875
876 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy);
877 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy);
878
879 if(bBtBusyTraffic != pCoexSta->bBtBusy)
880 { // BT idle or BT non-idle
881 bBtBusyTraffic = pCoexSta->bBtBusy;
882 stateChange = TRUE;
883 }
884
885 if(stateChange)
886 {
887 if(!pCoexSta->bBtBusy)
888 {
889 halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
890 halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
891 halbtc8192d2ant_CoexAllOff(pBtCoexist);
892 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
893 }
894 else
895 {
896 halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
897 halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
898 }
899 }
900
901 if(stateChange)
902 {
903 bRejApAggPkt = pCoexSta->bBtBusy;
904 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt);
905 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
906 }
907 }
908
909 VOID
halbtc8192d2ant_ActionA2dp(IN PBTC_COEXIST pBtCoexist)910 halbtc8192d2ant_ActionA2dp(
911 IN PBTC_COEXIST pBtCoexist
912 )
913 {
914 u1Byte wifiRssiState, wifiRssiState1=BTC_RSSI_STATE_HIGH;
915 u4Byte wifiBw, wifiTrafficDir;
916 BOOLEAN bWifiBusy=FALSE;
917
918 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
919 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
920 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
921
922 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
923 if(pCoexSta->bA2dpBusy && bWifiBusy)
924 {
925 if(BTC_WIFI_BW_HT40 == wifiBw)
926 {
927 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
928 }
929 else
930 {
931 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
932 {
933 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0);
934 }
935 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
936 {
937 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0);
938 }
939 }
940
941 // fw mechanism first
942 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
943 {
944 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18);
945 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
946 }
947 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
948 {
949 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18);
950 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
951 }
952
953 // sw mechanism
954 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
955 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
956 {
957 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
958 }
959 else
960 {
961 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
962 }
963
964 if(BTC_WIFI_BW_HT40 == wifiBw)
965 {
966 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
967 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
968 }
969 else
970 {
971 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
972 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
973 {
974 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
975 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
976 }
977 else
978 {
979 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
980 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
981 }
982 }
983 }
984 else if(pCoexSta->bA2dpBusy)
985 {
986 // fw mechanism first
987 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
988 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE);
989
990 // sw mechanism
991 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
992 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
993 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
994 }
995 else
996 {
997 halbtc8192d2ant_CoexAllOff(pBtCoexist);
998 }
999 }
1000
1001 VOID
halbtc8192d2ant_ActionPan(IN PBTC_COEXIST pBtCoexist)1002 halbtc8192d2ant_ActionPan(
1003 IN PBTC_COEXIST pBtCoexist
1004 )
1005 {
1006 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1007 u1Byte wifiRssiState, wifiRssiState1;
1008 u4Byte wifiBw, wifiTrafficDir;
1009 s4Byte wifiRssi;
1010
1011 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1012 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1013 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1014 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
1015 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
1016
1017 if(bBtHsOn)
1018 {
1019 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1020 }
1021 else
1022 {
1023 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50);
1024 if(BTC_WIFI_BW_HT40 == wifiBw)
1025 {
1026 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
1027 }
1028 else
1029 {
1030 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0);
1031 }
1032
1033 if(pCoexSta->bBtBusy && bWifiBusy)
1034 {
1035 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1036 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1037 {
1038 // fw mechanism first
1039 if(pCoexSta->bBtUplink)
1040 {
1041 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
1042 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1043 }
1044 else
1045 {
1046 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1047 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1048 }
1049 // sw mechanism
1050 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
1051 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
1052 {
1053 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1054 }
1055 else
1056 {
1057 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1058 }
1059 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1060 if(pCoexSta->bBtUplink)
1061 {
1062 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1063 }
1064 else
1065 {
1066 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
1067 }
1068 }
1069 else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) ||
1070 (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) )
1071 {
1072 // fw mechanism first
1073 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
1074
1075 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1076 {
1077 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1078 }
1079 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1080 {
1081 if(BTC_WIFI_BW_HT40 == wifiBw)
1082 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
1083 else
1084 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1085 }
1086 // sw mechanism
1087 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
1088 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
1089 {
1090 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1091 }
1092 else
1093 {
1094 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1095 }
1096 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1097 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1098 }
1099 else
1100 {
1101 // fw mechanism first
1102 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
1103
1104 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1105 {
1106 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1107 }
1108 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1109 {
1110 if(pCoexSta->bBtUplink)
1111 {
1112 if(BTC_WIFI_BW_HT40 == wifiBw)
1113 {
1114 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
1115 }
1116 else
1117 {
1118 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1119 }
1120 }
1121 else
1122 {
1123 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1124 }
1125 }
1126 // sw mechanism
1127 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
1128 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
1129 {
1130 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1131 }
1132 else
1133 {
1134 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1135 }
1136 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1137 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1138 }
1139 }
1140 else if(pCoexSta->bBtBusy &&
1141 !bWifiBusy &&
1142 (wifiRssi < 30))
1143 {
1144 // fw mechanism first
1145 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20);
1146 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1147 // sw mechanism
1148 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1149 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1150 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1151 }
1152 else
1153 {
1154 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1155 }
1156 }
1157 }
1158
1159
1160 VOID
halbtc8192d2ant_ActionHid(IN PBTC_COEXIST pBtCoexist)1161 halbtc8192d2ant_ActionHid(
1162 IN PBTC_COEXIST pBtCoexist
1163 )
1164 {
1165 u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH;
1166 u4Byte wifiTrafficDir;
1167 BOOLEAN bWifiBusy=FALSE;
1168
1169 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1170 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
1171 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1172 {
1173 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 45, 0);
1174 }
1175 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1176 {
1177 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 20, 0);
1178 }
1179
1180 if(pCoexSta->bBtBusy && bWifiBusy)
1181 {
1182 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1183 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1184 {
1185 // fw mechanism first
1186 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1187 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1188
1189 // sw mechanism
1190 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1191 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1192 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
1193 }
1194 else
1195 {
1196 // fw mechanism first
1197 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1198 {
1199 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1200 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE);
1201 }
1202 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1203 {
1204 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x15);
1205 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x30, FALSE);
1206 }
1207 // sw mechanism
1208 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1209 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1210 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1211 }
1212 }
1213 else
1214 {
1215 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1216 }
1217 }
1218
1219
1220
1221 VOID
halbtc8192d2ant_ActionSco(IN PBTC_COEXIST pBtCoexist)1222 halbtc8192d2ant_ActionSco(
1223 IN PBTC_COEXIST pBtCoexist
1224 )
1225 {
1226 u1Byte wifiRssiState;
1227 u4Byte wifiBw;
1228
1229 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1230 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
1231
1232 if(BTC_WIFI_BW_HT40 == wifiBw)
1233 {
1234 // fw mechanism first
1235 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1236 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1237
1238 // sw mechanism
1239 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1240 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1241 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1242 }
1243 else
1244 {
1245 // fw mechanism first
1246 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1247 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1248
1249 // sw mechanism
1250 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1251 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1252 {
1253 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1254 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1255 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1256 }
1257 else
1258 {
1259 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1260 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1261 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1262 }
1263 }
1264 }
1265
1266 VOID
halbtc8192d2ant_ActionHidA2dp(IN PBTC_COEXIST pBtCoexist)1267 halbtc8192d2ant_ActionHidA2dp(
1268 IN PBTC_COEXIST pBtCoexist
1269 )
1270 {
1271 u1Byte wifiRssiState, wifiRssiState1;
1272 u4Byte wifiBw;
1273
1274 if(pCoexSta->bBtBusy)
1275 {
1276 wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 35, 0);
1277 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1278 if(BTC_WIFI_BW_HT40 == wifiBw)
1279 {
1280 // fw mechanism first
1281 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1282 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1283
1284
1285 // sw mechanism
1286 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
1287 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
1288 {
1289 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1290 }
1291 else
1292 {
1293 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1294 }
1295 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1296 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
1297 }
1298 else
1299 {
1300 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
1301 // fw mechanism
1302 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1303 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1304
1305 // sw mechanism
1306 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
1307 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
1308 {
1309 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1310 }
1311 else
1312 {
1313 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1314 }
1315 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1316 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1317 {
1318 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1319 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
1320 }
1321 else
1322 {
1323 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1324 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
1325 }
1326 }
1327 }
1328 else
1329 {
1330 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1331 }
1332 }
1333
1334
1335 VOID
halbtc8192d2ant_ActionHidPanBc4(IN PBTC_COEXIST pBtCoexist)1336 halbtc8192d2ant_ActionHidPanBc4(
1337 IN PBTC_COEXIST pBtCoexist
1338 )
1339 {
1340 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1341 u4Byte wifiBw, wifiTrafficDir;
1342
1343 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1344
1345 if(bBtHsOn)
1346 {
1347 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1348 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1349
1350 halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
1351 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
1352 }
1353 else
1354 {
1355 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1356 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1357 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
1358 if(BTC_WIFI_BW_LEGACY == wifiBw)
1359 {
1360 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1361 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1362
1363 halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
1364 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
1365 }
1366 else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1367 {
1368 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1369 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1370
1371 halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
1372 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
1373 }
1374 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1375 {
1376 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
1377 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
1378 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1379 }
1380 else if(!bWifiBusy)
1381 {
1382 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
1383 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1384 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1385 }
1386 }
1387 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1388 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1389 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1390 }
1391 VOID
halbtc8192d2ant_ActionHidPanBc8(IN PBTC_COEXIST pBtCoexist)1392 halbtc8192d2ant_ActionHidPanBc8(
1393 IN PBTC_COEXIST pBtCoexist
1394 )
1395 {
1396 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1397 u1Byte wifiRssiState;
1398 u4Byte wifiBw, wifiTrafficDir;
1399
1400 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1401
1402 if(!bBtHsOn)
1403 {
1404 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1405 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
1406 if((pCoexSta->bBtBusy && bWifiBusy))
1407 {
1408 // fw mechanism first
1409 if(pCoexSta->bBtUplink)
1410 {
1411 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
1412 }
1413 else
1414 {
1415 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
1416 }
1417 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1418
1419 // sw mechanism
1420 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1421 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1422 {
1423 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1424 if(BTC_WIFI_BW_HT40 == wifiBw)
1425 {
1426 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1427 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1428 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1429 }
1430 else
1431 {
1432 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1433 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1434 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1435 }
1436 }
1437 else
1438 {
1439 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1440 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1441 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1442 }
1443 }
1444 else
1445 {
1446 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1447 }
1448 }
1449 else
1450 {
1451 if(BTC_INTF_USB == pBtCoexist->chipInterface)
1452 {
1453 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
1454 if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
1455 {
1456 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1457 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1458
1459 halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
1460 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
1461 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
1462 }
1463 else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
1464 {
1465 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
1466 }
1467 }
1468 else
1469 {
1470 if(pCoexSta->bBtBusy)
1471 {
1472 // fw mechanism
1473 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1474 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1475
1476 // sw mechanism
1477 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1478 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1479 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
1480 }
1481 else
1482 {
1483 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1484 }
1485 }
1486 }
1487 }
1488
1489 VOID
halbtc8192d2ant_ActionHidPan(IN PBTC_COEXIST pBtCoexist)1490 halbtc8192d2ant_ActionHidPan(
1491 IN PBTC_COEXIST pBtCoexist
1492 )
1493 {
1494 if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
1495 {
1496 halbtc8192d2ant_ActionHidPanBc4(pBtCoexist);
1497 }
1498 else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
1499 {
1500 halbtc8192d2ant_ActionHidPanBc8(pBtCoexist);
1501 }
1502 }
1503
1504 VOID
halbtc8192d2ant_ActionPanA2dpBc4(IN PBTC_COEXIST pBtCoexist)1505 halbtc8192d2ant_ActionPanA2dpBc4(
1506 IN PBTC_COEXIST pBtCoexist
1507 )
1508 {
1509 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1510 u1Byte wifiRssiState;
1511
1512 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1513
1514 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
1515 if(bBtHsOn)
1516 {
1517 if(pCoexSta->bBtBusy)
1518 {
1519 // fw mechanism
1520 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1521 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1522
1523 // sw mechanism
1524 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1525 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1526 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
1527 }
1528 else
1529 {
1530 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1531 }
1532 }
1533 else
1534 {
1535 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1536 if(pCoexSta->bBtBusy && bWifiBusy)
1537 {
1538 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
1539 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1540 }
1541 else
1542 {
1543 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1544 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
1545 }
1546 // sw mechanism
1547 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1548 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1549 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1550 }
1551 }
1552 VOID
halbtc8192d2ant_ActionPanA2dpBc8(IN PBTC_COEXIST pBtCoexist)1553 halbtc8192d2ant_ActionPanA2dpBc8(
1554 IN PBTC_COEXIST pBtCoexist
1555 )
1556 {
1557 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1558 u1Byte wifiRssiState;
1559 u4Byte wifiBw;
1560
1561 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1562
1563 if(!bBtHsOn)
1564 {
1565 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1566 wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
1567 if((pCoexSta->bBtBusy && bWifiBusy))
1568 {
1569 // fw mechanism first
1570 if(pCoexSta->bBtUplink)
1571 {
1572 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
1573 }
1574 else
1575 {
1576 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
1577 }
1578 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
1579
1580 // sw mechanism
1581 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
1582 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
1583 {
1584 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1585 if(BTC_WIFI_BW_HT40 == wifiBw)
1586 {
1587 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1588 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1589 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1590 }
1591 else
1592 {
1593 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
1594 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
1595 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1596 }
1597 }
1598 else
1599 {
1600 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1601 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1602 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1603 }
1604 }
1605 else
1606 {
1607 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1608 }
1609 }
1610 else
1611 {
1612 if(pCoexSta->bBtBusy)
1613 {
1614 // fw mechanism
1615 halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
1616 halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
1617
1618 // sw mechanism
1619 halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1620 halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1621 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
1622 }
1623 else
1624 {
1625 halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
1626 }
1627 }
1628 }
1629
1630 VOID
halbtc8192d2ant_ActionPanA2dp(IN PBTC_COEXIST pBtCoexist)1631 halbtc8192d2ant_ActionPanA2dp(
1632 IN PBTC_COEXIST pBtCoexist
1633 )
1634 {
1635 if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
1636 {
1637 halbtc8192d2ant_ActionPanA2dpBc4(pBtCoexist);
1638 }
1639 else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
1640 {
1641 halbtc8192d2ant_ActionPanA2dpBc8(pBtCoexist);
1642 }
1643 }
1644
1645 BOOLEAN
halbtc8192d2ant_IsBtCoexistEnter(IN PBTC_COEXIST pBtCoexist)1646 halbtc8192d2ant_IsBtCoexistEnter(
1647 IN PBTC_COEXIST pBtCoexist
1648 )
1649 {
1650 u1Byte macPhyMode;
1651 BOOLEAN bRet=TRUE;
1652 BOOLEAN bWifiUnder5G=FALSE;
1653
1654 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_MAC_PHY_MODE, &macPhyMode);
1655 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G);
1656
1657 if(BTC_SMSP != macPhyMode)
1658 {
1659 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Only support single mac single phy!!\n"));
1660 bRet = FALSE;
1661 }
1662
1663 if(bWifiUnder5G)
1664 {
1665 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under 5G or A band\n"));
1666 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1667 bRet = FALSE;
1668 }
1669
1670 return bRet;
1671 }
1672
1673 //============================================================
1674 // extern function start with EXhalbtc8192d2ant_
1675 //============================================================
1676 VOID
EXhalbtc8192d2ant_PowerOnSetting(IN PBTC_COEXIST pBtCoexist)1677 EXhalbtc8192d2ant_PowerOnSetting(
1678 IN PBTC_COEXIST pBtCoexist
1679 )
1680 {
1681 }
1682
1683 VOID
EXhalbtc8192d2ant_InitHwConfig(IN PBTC_COEXIST pBtCoexist,IN BOOLEAN bWifiOnly)1684 EXhalbtc8192d2ant_InitHwConfig(
1685 IN PBTC_COEXIST pBtCoexist,
1686 IN BOOLEAN bWifiOnly
1687 )
1688 {
1689 u1Byte u1Tmp=0;
1690
1691 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n"));
1692
1693 // backup rf 0x1e value
1694 pCoexDm->btRf0x1eBackup =
1695 pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
1696
1697 if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) ||
1698 (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) )
1699 {
1700 u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0;
1701 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp);
1702
1703 halbtc8192d2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010);
1704
1705 // switch control, here we set pathA to control
1706 // 0x878[13] = 1, 0:pathB, 1:pathA(default)
1707 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x878, BIT13, 0x1);
1708
1709 // antsel control, here we use phy0 and enable antsel.
1710 // 0x87c[16:15] = b'11, enable antsel, antsel output pin
1711 // 0x87c[30] = 0, 0: phy0, 1:phy 1
1712 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x87c, bMaskDWord, 0x1fff8);
1713
1714 // antsel to Bt or Wifi, it depends Bt on/off.
1715 // 0x860[9:8] = 'b10, b10:Bt On, WL2G off(default), b01:Bt off, WL2G on.
1716 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x860, BIT9|BIT8, 0x2);
1717
1718 // sw/hw control switch, here we set sw control
1719 // 0x870[9:8] = 'b11 sw control, 'b00 hw control
1720 pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x870, BIT9|BIT8, 0x3);
1721 }
1722 }
1723
1724 VOID
EXhalbtc8192d2ant_InitCoexDm(IN PBTC_COEXIST pBtCoexist)1725 EXhalbtc8192d2ant_InitCoexDm(
1726 IN PBTC_COEXIST pBtCoexist
1727 )
1728 {
1729 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n"));
1730
1731 halbtc8192d2ant_InitCoexDm(pBtCoexist);
1732 }
1733
1734 VOID
EXhalbtc8192d2ant_DisplayCoexInfo(IN PBTC_COEXIST pBtCoexist)1735 EXhalbtc8192d2ant_DisplayCoexInfo(
1736 IN PBTC_COEXIST pBtCoexist
1737 )
1738 {
1739 PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo;
1740 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
1741 pu1Byte cliBuf=pBtCoexist->cliBuf;
1742 u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
1743 u4Byte u4Tmp[4];
1744
1745 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
1746 CL_PRINTF(cliBuf);
1747
1748 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
1749 pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum);
1750 CL_PRINTF(cliBuf);
1751
1752 if(pBtCoexist->bManualControl)
1753 {
1754 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
1755 CL_PRINTF(cliBuf);
1756 }
1757
1758 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
1759 ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
1760 CL_PRINTF(cliBuf);
1761
1762 // wifi status
1763 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============");
1764 CL_PRINTF(cliBuf);
1765 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS);
1766
1767 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============");
1768 CL_PRINTF(cliBuf);
1769
1770 if(pStackInfo->bProfileNotified)
1771 {
1772 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
1773 pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
1774 CL_PRINTF(cliBuf);
1775
1776 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
1777 }
1778
1779 // Sw mechanism
1780 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
1781 CL_PRINTF(cliBuf);
1782 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
1783 pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
1784 CL_PRINTF(cliBuf);
1785
1786 // Fw mechanism
1787 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
1788 CL_PRINTF(cliBuf);
1789
1790 // Hw setting
1791 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
1792 CL_PRINTF(cliBuf);
1793
1794 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
1795 pCoexDm->btRf0x1eBackup);
1796 CL_PRINTF(cliBuf);
1797
1798 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40);
1799 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
1800 u1Tmp[0]);
1801 CL_PRINTF(cliBuf);
1802
1803 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50);
1804 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
1805 u4Tmp[0]);
1806 CL_PRINTF(cliBuf);
1807
1808 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4);
1809 u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8);
1810 u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc);
1811 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \
1812 u4Tmp[0], u4Tmp[1], u4Tmp[2]);
1813 CL_PRINTF(cliBuf);
1814
1815 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
1816 }
1817
1818
1819 VOID
EXhalbtc8192d2ant_IpsNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1820 EXhalbtc8192d2ant_IpsNotify(
1821 IN PBTC_COEXIST pBtCoexist,
1822 IN u1Byte type
1823 )
1824 {
1825 if(BTC_IPS_ENTER == type)
1826 {
1827 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n"));
1828 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1829 }
1830 else if(BTC_IPS_LEAVE == type)
1831 {
1832 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n"));
1833 //halbtc8192d2ant_InitCoexDm(pBtCoexist);
1834 }
1835 }
1836
1837 VOID
EXhalbtc8192d2ant_LpsNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1838 EXhalbtc8192d2ant_LpsNotify(
1839 IN PBTC_COEXIST pBtCoexist,
1840 IN u1Byte type
1841 )
1842 {
1843 if(BTC_LPS_ENABLE == type)
1844 {
1845 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n"));
1846 halbtc8192d2ant_CoexAllOff(pBtCoexist);
1847 }
1848 else if(BTC_LPS_DISABLE == type)
1849 {
1850 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n"));
1851 halbtc8192d2ant_InitCoexDm(pBtCoexist);
1852 }
1853 }
1854
1855 VOID
EXhalbtc8192d2ant_ScanNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1856 EXhalbtc8192d2ant_ScanNotify(
1857 IN PBTC_COEXIST pBtCoexist,
1858 IN u1Byte type
1859 )
1860 {
1861 if(BTC_SCAN_START == type)
1862 {
1863 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n"));
1864 }
1865 else if(BTC_SCAN_FINISH == type)
1866 {
1867 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n"));
1868 }
1869 }
1870
1871 VOID
EXhalbtc8192d2ant_ConnectNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1872 EXhalbtc8192d2ant_ConnectNotify(
1873 IN PBTC_COEXIST pBtCoexist,
1874 IN u1Byte type
1875 )
1876 {
1877 if(BTC_ASSOCIATE_START == type)
1878 {
1879 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n"));
1880 }
1881 else if(BTC_ASSOCIATE_FINISH == type)
1882 {
1883 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n"));
1884 }
1885 }
1886
1887 VOID
EXhalbtc8192d2ant_MediaStatusNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1888 EXhalbtc8192d2ant_MediaStatusNotify(
1889 IN PBTC_COEXIST pBtCoexist,
1890 IN u1Byte type
1891 )
1892 {
1893 if(BTC_MEDIA_CONNECT == type)
1894 {
1895 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n"));
1896 }
1897 else
1898 {
1899 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n"));
1900 }
1901 }
1902
1903 VOID
EXhalbtc8192d2ant_SpecialPacketNotify(IN PBTC_COEXIST pBtCoexist,IN u1Byte type)1904 EXhalbtc8192d2ant_SpecialPacketNotify(
1905 IN PBTC_COEXIST pBtCoexist,
1906 IN u1Byte type
1907 )
1908 {
1909 if(type == BTC_PACKET_DHCP)
1910 {
1911 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n"));
1912 }
1913 }
1914
1915 VOID
EXhalbtc8192d2ant_BtInfoNotify(IN PBTC_COEXIST pBtCoexist,IN pu1Byte tmpBuf,IN u1Byte length)1916 EXhalbtc8192d2ant_BtInfoNotify(
1917 IN PBTC_COEXIST pBtCoexist,
1918 IN pu1Byte tmpBuf,
1919 IN u1Byte length
1920 )
1921 {
1922 }
1923
1924 VOID
EXhalbtc8192d2ant_HaltNotify(IN PBTC_COEXIST pBtCoexist)1925 EXhalbtc8192d2ant_HaltNotify(
1926 IN PBTC_COEXIST pBtCoexist
1927 )
1928 {
1929 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n"));
1930
1931 EXhalbtc8192d2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
1932 }
1933
1934 VOID
EXhalbtc8192d2ant_Periodical(IN PBTC_COEXIST pBtCoexist)1935 EXhalbtc8192d2ant_Periodical(
1936 IN PBTC_COEXIST pBtCoexist
1937 )
1938 {
1939 u1Byte algorithm;
1940
1941 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n"));
1942
1943 // NOTE:
1944 // sw mechanism must be done after fw mechanism
1945 //
1946 if(!halbtc8192d2ant_IsBtCoexistEnter(pBtCoexist))
1947 return;
1948
1949 if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
1950 {
1951 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL);
1952
1953 halbtc8192d2ant_MonitorBtState(pBtCoexist);
1954 algorithm = halbtc8192d2ant_ActionAlgorithm(pBtCoexist);
1955 pCoexDm->curAlgorithm = algorithm;
1956 switch(pCoexDm->curAlgorithm)
1957 {
1958 case BT_8192D_2ANT_COEX_ALGO_SCO:
1959 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n"));
1960 halbtc8192d2ant_ActionSco(pBtCoexist);
1961 break;
1962 case BT_8192D_2ANT_COEX_ALGO_HID:
1963 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n"));
1964 halbtc8192d2ant_ActionHid(pBtCoexist);
1965 break;
1966 case BT_8192D_2ANT_COEX_ALGO_A2DP:
1967 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n"));
1968 halbtc8192d2ant_ActionA2dp(pBtCoexist);
1969 break;
1970 case BT_8192D_2ANT_COEX_ALGO_PAN:
1971 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n"));
1972 halbtc8192d2ant_ActionPan(pBtCoexist);
1973 break;
1974 case BT_8192D_2ANT_COEX_ALGO_HID_A2DP:
1975 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n"));
1976 halbtc8192d2ant_ActionHidA2dp(pBtCoexist);
1977 break;
1978 case BT_8192D_2ANT_COEX_ALGO_HID_PAN:
1979 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n"));
1980 halbtc8192d2ant_ActionHidPan(pBtCoexist);
1981 break;
1982 case BT_8192D_2ANT_COEX_ALGO_PAN_A2DP:
1983 RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n"));
1984 halbtc8192d2ant_ActionPanA2dp(pBtCoexist);
1985 break;
1986 default:
1987 break;
1988 }
1989 }
1990 }
1991
1992 #endif
1993
1994