1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in the 16 * file called LICENSE. 17 * 18 * Contact Information: 19 * wlanfae <wlanfae@realtek.com> 20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 21 * Hsinchu 300, Taiwan. 22 * 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 *****************************************************************************/ 26 27 #ifndef __HALDMOUTSRC_H__ 28 #define __HALDMOUTSRC_H__ 29 30 /*@============================================================*/ 31 /*@include files*/ 32 /*@============================================================*/ 33 /*PHYDM header*/ 34 #include "phydm_pre_define.h" 35 #include "phydm_features.h" 36 #include "phydm_dig.h" 37 #ifdef CONFIG_PATH_DIVERSITY 38 #include "phydm_pathdiv.h" 39 #endif 40 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 41 #include "phydm_antdiv.h" 42 #endif 43 44 #include "phydm_soml.h" 45 46 #ifdef CONFIG_SMART_ANTENNA 47 #include "phydm_smt_ant.h" 48 #endif 49 #ifdef CONFIG_ANT_DETECTION 50 #include "phydm_antdect.h" 51 #endif 52 #include "phydm_rainfo.h" 53 #ifdef CONFIG_DYNAMIC_TX_TWR 54 #include "phydm_dynamictxpower.h" 55 #endif 56 #include "phydm_cfotracking.h" 57 #include "phydm_adaptivity.h" 58 #include "phydm_dfs.h" 59 #include "phydm_ccx.h" 60 #include "txbf/phydm_hal_txbf_api.h" 61 #if (PHYDM_LA_MODE_SUPPORT) 62 #include "phydm_adc_sampling.h" 63 #endif 64 #ifdef CONFIG_PSD_TOOL 65 #include "phydm_psd.h" 66 #endif 67 #ifdef PHYDM_PRIMARY_CCA 68 #include "phydm_primary_cca.h" 69 #endif 70 #include "phydm_cck_pd.h" 71 #include "phydm_rssi_monitor.h" 72 #ifdef PHYDM_AUTO_DEGBUG 73 #include "phydm_auto_dbg.h" 74 #endif 75 #include "phydm_math_lib.h" 76 #include "phydm_noisemonitor.h" 77 #include "phydm_api.h" 78 #ifdef PHYDM_POWER_TRAINING_SUPPORT 79 #include "phydm_pow_train.h" 80 #endif 81 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 82 #include "phydm_lna_sat.h" 83 #endif 84 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 85 #include "phydm_pmac_tx_setting.h" 86 #endif 87 #ifdef PHYDM_MP_SUPPORT 88 #include "phydm_mp.h" 89 #endif 90 91 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 92 #include "phydm_cck_rx_pathdiv.h" 93 #endif 94 95 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 96 #include "phydm_beamforming.h" 97 #endif 98 99 #ifdef CONFIG_DIRECTIONAL_BF 100 #include "phydm_direct_bf.h" 101 #endif 102 103 #include "phydm_regtable.h" 104 105 /*@HALRF header*/ 106 #include "halrf/halrf_iqk.h" 107 #include "halrf/halrf_dpk.h" 108 #include "halrf/halrf.h" 109 #include "halrf/halrf_powertracking.h" 110 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 111 #include "halrf/halphyrf_ap.h" 112 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 113 #include "halrf/halphyrf_ce.h" 114 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 115 #include "halrf/halphyrf_win.h" 116 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 117 #include "halrf/halphyrf_iot.h" 118 #endif 119 120 extern const u16 phy_rate_table[84]; 121 122 /*@============================================================*/ 123 /*@Definition */ 124 /*@============================================================*/ 125 126 /* Traffic load decision */ 127 #define TRAFFIC_NO_TP 0 128 #define TRAFFIC_ULTRA_LOW 1 129 #define TRAFFIC_LOW 2 130 #define TRAFFIC_MID 3 131 #define TRAFFIC_HIGH 4 132 133 #define NONE 0 134 135 #if defined(DM_ODM_CE_MAC80211) 136 #define MAX_2(x, y) \ 137 __max2(typeof(x), typeof(y), \ 138 x, y) 139 #define __max2(t1, t2, x, y) ({ \ 140 t1 m80211_max1 = (x); \ 141 t2 m80211_max2 = (y); \ 142 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 143 144 #define MIN_2(x, y) \ 145 __min2(typeof(x), typeof(y), \ 146 x, y) 147 #define __min2(t1, t2, x, y) ({ \ 148 t1 m80211_min1 = (x); \ 149 t2 m80211_min2 = (y); \ 150 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 151 152 #define DIFF_2(x, y) \ 153 __diff2(typeof(x), typeof(y), \ 154 x, y) 155 #define __diff2(t1, t2, x, y) ({ \ 156 t1 __d1 = (x); \ 157 t2 __d2 = (y); \ 158 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 159 #else 160 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 161 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 162 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 163 #endif 164 165 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 166 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 167 168 #if defined(DM_ODM_CE_MAC80211) 169 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 170 u32 __b_dup = (B0);\ 171 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 172 }) 173 #else 174 #define BYTE_DUPLICATE_2_DWORD(B0) \ 175 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 176 #endif 177 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 178 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 179 #define BIT_2_BYTE(B3, B2, B1, B0) \ 180 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 181 182 /*@For cmn sta info*/ 183 #if defined(DM_ODM_CE_MAC80211) 184 #define is_sta_active(sta) ({ \ 185 struct cmn_sta_info *__sta = (sta); \ 186 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 187 }) 188 189 #define IS_FUNC_EN(name) ({ \ 190 u8 *__is_func_name = (name); \ 191 (__is_func_name) && (*__is_func_name); \ 192 }) 193 #else 194 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 195 196 #define IS_FUNC_EN(name) ((name) && (*name)) 197 #endif 198 199 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 200 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 201 #else 202 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 203 #endif 204 205 #define PHY_HIST_SIZE 12 206 #define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) 207 208 /*@============================================================*/ 209 /*structure and define*/ 210 /*@============================================================*/ 211 212 #define dm_type_by_fw 0 213 #define dm_type_by_driver 1 214 215 #define HW_IGI_TXINFO_TABLE_SIZE 64 216 217 #ifdef BB_RAM_SUPPORT 218 219 struct phydm_bb_ram_per_sta { 220 /* @Reg0x1E84 for RAM I/O*/ 221 boolean hw_igi_en; 222 boolean tx_pwr_offset0_en; 223 boolean tx_pwr_offset1_en; 224 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 225 u8 macid_addr; 226 /* @hw_igi value for paths after packet Tx in a period of time*/ 227 u8 hw_igi; 228 /* @tx_pwr_offset0 offset for Tx power index*/ 229 s8 tx_pwr_offset0; 230 s8 tx_pwr_offset1; 231 232 }; 233 234 struct phydm_bb_ram_ctrl { 235 /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ 236 struct phydm_bb_ram_per_sta pram_sta_ctrl[HW_IGI_TXINFO_TABLE_SIZE]; 237 /*------------ For table2 do not set power offset by macid --------*/ 238 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 239 boolean tx_pwr_ofst_reg0_en; 240 u8 tx_pwr_ofst_reg0; 241 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 242 boolean tx_pwr_ofst_reg1_en; 243 u8 tx_pwr_ofst_reg1; 244 boolean hwigi_watchdog_en; 245 u64 macid_is_linked; 246 u64 hwigi_macid_is_linked; 247 }; 248 249 #endif 250 251 struct phydm_phystatus_statistic { 252 /*@[CCK]*/ 253 u32 rssi_cck_sum; 254 u32 rssi_cck_cnt; 255 u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; 256 u32 rssi_beacon_cnt; 257 #ifdef PHYSTS_3RD_TYPE_SUPPORT 258 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 259 u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; 260 #endif 261 #endif 262 /*@[OFDM]*/ 263 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 264 u32 rssi_ofdm_cnt; 265 u32 evm_ofdm_sum; 266 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 267 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 268 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 269 /*@[1SS]*/ 270 u32 rssi_1ss_cnt; 271 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 272 u32 evm_1ss_sum; 273 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 274 u16 evm_1ss_hist[PHY_HIST_SIZE]; 275 u16 snr_1ss_hist[PHY_HIST_SIZE]; 276 /*@[2SS]*/ 277 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 278 u32 rssi_2ss_cnt; 279 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 280 u32 evm_2ss_sum[2]; 281 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 282 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 283 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 284 #endif 285 /*@[3SS]*/ 286 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 287 u32 rssi_3ss_cnt; 288 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 289 u32 evm_3ss_sum[3]; 290 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 291 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 292 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 293 #endif 294 /*@[4SS]*/ 295 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 296 u32 rssi_4ss_cnt; 297 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 298 u32 evm_4ss_sum[4]; 299 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 300 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 301 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 302 #endif 303 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 304 u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ 305 u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ 306 u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; 307 #endif 308 }; 309 310 struct phydm_phystatus_avg { 311 /*@[CCK]*/ 312 u8 rssi_cck_avg; 313 u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; 314 #ifdef PHYSTS_3RD_TYPE_SUPPORT 315 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 316 u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; 317 #endif 318 #endif 319 /*@[OFDM]*/ 320 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 321 u8 evm_ofdm_avg; 322 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 323 /*@[1SS]*/ 324 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 325 u8 evm_1ss_avg; 326 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 327 /*@[2SS]*/ 328 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 329 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 330 u8 evm_2ss_avg[2]; 331 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 332 #endif 333 /*@[3SS]*/ 334 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 335 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 336 u8 evm_3ss_avg[3]; 337 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 338 #endif 339 /*@[4SS]*/ 340 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 341 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 342 u8 evm_4ss_avg[4]; 343 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 344 #endif 345 }; 346 347 struct odm_phy_dbg_info { 348 /*@ODM Write,debug info*/ 349 u32 num_qry_phy_status_cck; 350 u32 num_qry_phy_status_ofdm; 351 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 352 u32 num_qry_mu_pkt; 353 u32 num_qry_bf_pkt; 354 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 355 boolean is_ldpc_pkt; 356 boolean is_stbc_pkt; 357 u8 num_of_ppdu[4]; 358 u8 gid_num[4]; 359 #endif 360 u32 condi_num; /*@condition number U(18,4)*/ 361 u8 condi_num_cdf[CN_CNT_MAX]; 362 u8 num_qry_beacon_pkt; 363 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 364 u8 beacon_phy_rate; 365 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 366 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 367 u16 show_phy_sts_cnt; 368 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 369 u16 num_qry_ht_pkt[HT_RATE_NUM]; 370 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 371 boolean ht_pkt_not_zero; 372 boolean low_bw_20_occur; 373 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 374 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 375 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 376 boolean vht_pkt_not_zero; 377 boolean low_bw_40_occur; 378 #endif 379 u16 snr_hist_th[PHY_HIST_TH_SIZE]; 380 u16 evm_hist_th[PHY_HIST_TH_SIZE]; 381 #ifdef PHYSTS_3RD_TYPE_SUPPORT 382 u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ 383 u8 condition_num_seg0; 384 u8 eigen_val[4]; 385 s16 cfo_tail[4]; /*per-path's cfo_tail */ 386 #endif 387 struct phydm_phystatus_statistic physts_statistic_info; 388 struct phydm_phystatus_avg phystatus_statistic_avg; 389 }; 390 391 enum odm_cmninfo { 392 /*@Fixed value*/ 393 /*@-----------HOOK BEFORE REG INIT-----------*/ 394 ODM_CMNINFO_PLATFORM = 0, 395 ODM_CMNINFO_ABILITY, 396 ODM_CMNINFO_INTERFACE, 397 ODM_CMNINFO_MP_TEST_CHIP, 398 ODM_CMNINFO_IC_TYPE, 399 ODM_CMNINFO_CUT_VER, 400 ODM_CMNINFO_FAB_VER, 401 ODM_CMNINFO_FW_VER, 402 ODM_CMNINFO_FW_SUB_VER, 403 ODM_CMNINFO_RF_TYPE, 404 ODM_CMNINFO_RFE_TYPE, 405 ODM_CMNINFO_DPK_EN, 406 ODM_CMNINFO_BOARD_TYPE, 407 ODM_CMNINFO_PACKAGE_TYPE, 408 ODM_CMNINFO_EXT_LNA, 409 ODM_CMNINFO_5G_EXT_LNA, 410 ODM_CMNINFO_EXT_PA, 411 ODM_CMNINFO_5G_EXT_PA, 412 ODM_CMNINFO_GPA, 413 ODM_CMNINFO_APA, 414 ODM_CMNINFO_GLNA, 415 ODM_CMNINFO_ALNA, 416 ODM_CMNINFO_TDMA, 417 ODM_CMNINFO_EXT_TRSW, 418 ODM_CMNINFO_EXT_LNA_GAIN, 419 ODM_CMNINFO_PATCH_ID, 420 ODM_CMNINFO_BINHCT_TEST, 421 ODM_CMNINFO_BWIFI_TEST, 422 ODM_CMNINFO_SMART_CONCURRENT, 423 ODM_CMNINFO_CONFIG_BB_RF, 424 ODM_CMNINFO_IQKPAOFF, 425 ODM_CMNINFO_HUBUSBMODE, 426 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 427 ODM_CMNINFO_TX_TP, 428 ODM_CMNINFO_RX_TP, 429 ODM_CMNINFO_SOUNDING_SEQ, 430 ODM_CMNINFO_REGRFKFREEENABLE, 431 ODM_CMNINFO_RFKFREEENABLE, 432 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 433 ODM_CMNINFO_VALID_PATH_SET, 434 ODM_CMNINFO_EFUSE0X3D8, 435 ODM_CMNINFO_EFUSE0X3D7, 436 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 437 ODM_CMNINFO_X_CAP_SETTING, 438 ODM_CMNINFO_ADVANCE_OTA, 439 ODM_CMNINFO_HP_HWID, 440 ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/ 441 ODM_CMNINFO_DIS_DPD, 442 ODM_CMNINFO_POWER_VOLTAGE, 443 ODM_CMNINFO_ANTDIV_GPIO, 444 ODM_CMNINFO_EN_AUTO_BW_TH, 445 ODM_CMNINFO_PEAK_DETECT_MODE, 446 /*@-----------HOOK BEFORE REG INIT-----------*/ 447 448 /*@Dynamic value:*/ 449 450 /*@--------- POINTER REFERENCE-----------*/ 451 ODM_CMNINFO_TX_UNI, 452 ODM_CMNINFO_RX_UNI, 453 ODM_CMNINFO_BAND, 454 ODM_CMNINFO_SEC_CHNL_OFFSET, 455 ODM_CMNINFO_SEC_MODE, 456 ODM_CMNINFO_BW, 457 ODM_CMNINFO_CHNL, 458 ODM_CMNINFO_FORCED_RATE, 459 ODM_CMNINFO_ANT_DIV, 460 ODM_CMNINFO_PATH_DIV, 461 ODM_CMNINFO_ADAPTIVE_SOML, 462 ODM_CMNINFO_ADAPTIVITY, 463 ODM_CMNINFO_SCAN, 464 ODM_CMNINFO_POWER_SAVING, 465 ODM_CMNINFO_ONE_PATH_CCA, 466 ODM_CMNINFO_DRV_STOP, 467 ODM_CMNINFO_PNP_IN, 468 ODM_CMNINFO_INIT_ON, 469 ODM_CMNINFO_ANT_TEST, 470 ODM_CMNINFO_NET_CLOSED, 471 ODM_CMNINFO_P2P_LINK, 472 ODM_CMNINFO_FCS_MODE, 473 ODM_CMNINFO_IS1ANTENNA, 474 ODM_CMNINFO_RFDEFAULTPATH, 475 ODM_CMNINFO_DFS_MASTER_ENABLE, 476 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 477 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 478 ODM_CMNINFO_SOFT_AP_MODE, 479 ODM_CMNINFO_MP_MODE, 480 ODM_CMNINFO_INTERRUPT_MASK, 481 ODM_CMNINFO_BB_OPERATION_MODE, 482 ODM_CMNINFO_BF_ANTDIV_DECISION, 483 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 484 ODM_CMNINFO_EN_DYM_BW_INDICATION, 485 /*@--------- POINTER REFERENCE-----------*/ 486 487 /*@------------CALL BY VALUE-------------*/ 488 ODM_CMNINFO_WIFI_DIRECT, 489 ODM_CMNINFO_WIFI_DISPLAY, 490 ODM_CMNINFO_LINK_IN_PROGRESS, 491 ODM_CMNINFO_LINK, 492 ODM_CMNINFO_CMW500LINK, 493 ODM_CMNINFO_STATION_STATE, 494 ODM_CMNINFO_RSSI_MIN, 495 ODM_CMNINFO_RSSI_MIN_BY_PATH, 496 ODM_CMNINFO_DBG_COMP, 497 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 498 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 499 ODM_CMNINFO_RF_ANTENNA_TYPE, 500 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 501 ODM_CMNINFO_BE_FIX_TX_ANT, 502 ODM_CMNINFO_BT_ENABLED, 503 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 504 ODM_CMNINFO_BT_HS_RSSI, 505 ODM_CMNINFO_BT_OPERATION, 506 ODM_CMNINFO_BT_LIMITED_DIG, 507 ODM_CMNINFO_AP_TOTAL_NUM, 508 ODM_CMNINFO_POWER_TRAINING, 509 ODM_CMNINFO_DFS_REGION_DOMAIN, 510 ODM_CMNINFO_BT_CONTINUOUS_TURN, 511 ODM_CMNINFO_IS_DOWNLOAD_FW, 512 ODM_CMNINFO_PHYDM_PATCH_ID, 513 ODM_CMNINFO_RRSR_VAL, 514 ODM_CMNINFO_LINKED_BF_SUPPORT, 515 ODM_CMNINFO_FLATNESS_TYPE, 516 /*@------------CALL BY VALUE-------------*/ 517 518 /*@Dynamic ptr array hook itms.*/ 519 ODM_CMNINFO_STA_STATUS, 520 ODM_CMNINFO_MAX, 521 522 }; 523 524 enum phydm_rfe_bb_source_sel { 525 PAPE_2G = 0, 526 PAPE_5G = 1, 527 LNA0N_2G = 2, 528 LNAON_5G = 3, 529 TRSW = 4, 530 TRSW_B = 5, 531 GNT_BT = 6, 532 ZERO = 7, 533 ANTSEL_0 = 8, 534 ANTSEL_1 = 9, 535 ANTSEL_2 = 0xa, 536 ANTSEL_3 = 0xb, 537 ANTSEL_4 = 0xc, 538 ANTSEL_5 = 0xd, 539 ANTSEL_6 = 0xe, 540 ANTSEL_7 = 0xf 541 }; 542 543 enum phydm_info_query { 544 PHYDM_INFO_FA_OFDM, 545 PHYDM_INFO_FA_CCK, 546 PHYDM_INFO_FA_TOTAL, 547 PHYDM_INFO_CCA_OFDM, 548 PHYDM_INFO_CCA_CCK, 549 PHYDM_INFO_CCA_ALL, 550 PHYDM_INFO_CRC32_OK_VHT, 551 PHYDM_INFO_CRC32_OK_HT, 552 PHYDM_INFO_CRC32_OK_LEGACY, 553 PHYDM_INFO_CRC32_OK_CCK, 554 PHYDM_INFO_CRC32_ERROR_VHT, 555 PHYDM_INFO_CRC32_ERROR_HT, 556 PHYDM_INFO_CRC32_ERROR_LEGACY, 557 PHYDM_INFO_CRC32_ERROR_CCK, 558 PHYDM_INFO_EDCCA_FLAG, 559 PHYDM_INFO_OFDM_ENABLE, 560 PHYDM_INFO_CCK_ENABLE, 561 PHYDM_INFO_CRC32_OK_HT_AGG, 562 PHYDM_INFO_CRC32_ERROR_HT_AGG, 563 PHYDM_INFO_DBG_PORT_0, 564 PHYDM_INFO_CURR_IGI, 565 PHYDM_INFO_RSSI_MIN, 566 PHYDM_INFO_RSSI_MAX, 567 PHYDM_INFO_CLM_RATIO, 568 PHYDM_INFO_NHM_RATIO, 569 PHYDM_INFO_NHM_NOISE_PWR, 570 PHYDM_INFO_NHM_PWR, 571 PHYDM_INFO_NHM_ENV_RATIO, 572 573 }; 574 575 enum phydm_api { 576 PHYDM_API_NBI = 1, 577 PHYDM_API_CSI_MASK = 2, 578 }; 579 580 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 581 582 F00_DIG = 0, 583 F01_RA_MASK = 1, 584 F02_DYN_TXPWR = 2, 585 F03_FA_CNT = 3, 586 F04_RSSI_MNTR = 4, 587 F05_CCK_PD = 5, 588 F06_ANT_DIV = 6, 589 F07_SMT_ANT = 7, 590 F08_PWR_TRAIN = 8, 591 F09_RA = 9, 592 F10_PATH_DIV = 10, 593 F11_DFS = 11, 594 F12_DYN_ARFR = 12, 595 F13_ADPTVTY = 13, 596 F14_CFO_TRK = 14, 597 F15_ENV_MNTR = 15, 598 F16_PRI_CCA = 16, 599 F17_ADPTV_SOML = 17, 600 F18_LNA_SAT_CHK = 18, 601 }; 602 603 /*@=[PHYDM supportability]==========================================*/ 604 enum odm_ability { 605 ODM_BB_DIG = BIT(F00_DIG), 606 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 607 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 608 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 609 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 610 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 611 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 612 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 613 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 614 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 615 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 616 ODM_BB_DFS = BIT(F11_DFS), 617 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 618 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 619 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 620 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 621 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 622 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 623 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 624 }; 625 626 /*@=[PHYDM Debug Component]=====================================*/ 627 enum phydm_dbg_comp { 628 /*@BB Driver Functions*/ 629 DBG_DIG = BIT(F00_DIG), 630 DBG_RA_MASK = BIT(F01_RA_MASK), 631 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 632 DBG_FA_CNT = BIT(F03_FA_CNT), 633 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 634 DBG_CCKPD = BIT(F05_CCK_PD), 635 DBG_ANT_DIV = BIT(F06_ANT_DIV), 636 DBG_SMT_ANT = BIT(F07_SMT_ANT), 637 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 638 DBG_RA = BIT(F09_RA), 639 DBG_PATH_DIV = BIT(F10_PATH_DIV), 640 DBG_DFS = BIT(F11_DFS), 641 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 642 DBG_ADPTVTY = BIT(F13_ADPTVTY), 643 DBG_CFO_TRK = BIT(F14_CFO_TRK), 644 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 645 DBG_PRI_CCA = BIT(F16_PRI_CCA), 646 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 647 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 648 /*Neet to re-arrange*/ 649 DBG_PHY_STATUS = BIT(20), 650 DBG_TMP = BIT(21), 651 DBG_FW_TRACE = BIT(22), 652 DBG_TXBF = BIT(23), 653 DBG_COMMON_FLOW = BIT(24), 654 DBG_COMP_MCC = BIT(25), 655 DBG_FW_DM = BIT(26), 656 DBG_DM_SUMMARY = BIT(27), 657 ODM_PHY_CONFIG = BIT(28), 658 ODM_COMP_INIT = BIT(29), 659 DBG_CMN = BIT(30),/*@common*/ 660 ODM_COMP_API = BIT(31) 661 }; 662 663 /*@=========================================================*/ 664 665 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 666 enum odm_cca_path { 667 ODM_CCA_2R = 0, 668 ODM_CCA_1R_A = 1, 669 ODM_CCA_1R_B = 2, 670 }; 671 672 enum phy_reg_pg_type { 673 PHY_REG_PG_RELATIVE_VALUE = 0, 674 PHY_REG_PG_EXACT_VALUE = 1 675 }; 676 677 enum phydm_offload_ability { 678 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 679 PHYDM_RF_IQK_OFFLOAD = BIT(1), 680 PHYDM_RF_DPK_OFFLOAD = BIT(2), 681 }; 682 683 enum phydm_init_result { 684 PHYDM_INIT_SUCCESS = 0, 685 PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1 686 }; 687 688 struct phydm_pause_lv { 689 s8 lv_dig; 690 s8 lv_cckpd; 691 s8 lv_antdiv; 692 s8 lv_adapt; 693 s8 lv_adsl; 694 }; 695 696 struct phydm_func_poiner { 697 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 698 }; 699 700 struct pkt_process_info { 701 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 702 /*@send phystatus in each sampling time*/ 703 boolean physts_auto_swch_en; 704 u8 mac_ppdu_cnt; 705 u8 phy_ppdu_cnt; /*change with phy cca cnt*/ 706 u8 page_bitmap_target; 707 u8 page_bitmap_record; 708 u8 ppdu_phy_rate; 709 u8 ppdu_macid; 710 boolean is_1st_mpdu; 711 #endif 712 u8 lna_idx; 713 u8 vga_idx; 714 }; 715 716 #ifdef ODM_CONFIG_BT_COEXIST 717 struct phydm_bt_info { 718 boolean is_bt_enabled; /*@BT is enabled*/ 719 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 720 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 721 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 722 boolean is_bt_limited_dig; /*@BT is busy.*/ 723 }; 724 #endif 725 726 struct phydm_iot_center { 727 boolean is_linked_cmw500; 728 u8 win_patch_id; /*Customer ID*/ 729 boolean patch_id_100f0401; 730 boolean patch_id_10120200; 731 boolean patch_id_40010700; 732 boolean patch_id_021f0800; 733 boolean patch_id_011f0500; 734 u32 phydm_patch_id; /*temp for CCX IOT */ 735 }; 736 737 #if (RTL8822B_SUPPORT) 738 struct drp_rtl8822b_struct { 739 enum bb_path path_judge; 740 u16 path_a_cck_fa; 741 u16 path_b_cck_fa; 742 }; 743 #endif 744 745 #ifdef CONFIG_MCC_DM 746 #define MCC_DM_REG_NUM 32 747 struct _phydm_mcc_dm_ { 748 u8 mcc_pre_status; 749 u8 mcc_reg_id[MCC_DM_REG_NUM]; 750 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 751 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 752 /*mcc DIG*/ 753 u8 mcc_rssi[2]; 754 /*u8 mcc_igi[2];*/ 755 756 /* need to be config by driver*/ 757 u8 mcc_status; 758 u8 sta_macid[2][NUM_STA]; 759 u16 mcc_rf_ch[2]; 760 761 }; 762 #endif 763 764 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 765 struct phydm_physts { 766 u8 cck_gi_u_bnd; 767 u8 cck_gi_l_bnd; 768 }; 769 #endif 770 771 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 772 #if (RT_PLATFORM != PLATFORM_LINUX) 773 typedef 774 #endif 775 776 struct dm_struct { 777 #else/*for AP, CE Team*/ 778 struct dm_struct { 779 #endif 780 /*@Add for different team use temporarily*/ 781 void *adapter; /*@For CE/NIC team*/ 782 struct rtl8192cd_priv *priv; /*@For AP team*/ 783 boolean odm_ready; 784 enum phy_reg_pg_type phy_reg_pg_value_type; 785 u8 phy_reg_pg_version; 786 u64 support_ability; /*@PHYDM function Supportability*/ 787 u64 pause_ability; /*@PHYDM function pause Supportability*/ 788 u64 debug_components; 789 u8 cmn_dbg_msg_period; 790 u8 cmn_dbg_msg_cnt; 791 u32 fw_debug_components; 792 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 793 u32 last_num_qry_phy_status_all; 794 u32 rx_pwdb_ave; 795 boolean is_init_hw_info_by_rfe; 796 797 //TSSI 798 u8 en_tssi_mode; 799 800 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 801 boolean is_cck_high_power; 802 u8 rf_path_rx_enable; 803 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 804 805 /* @COMMON INFORMATION */ 806 807 /*@Init value*/ 808 /*@-----------HOOK BEFORE REG INIT-----------*/ 809 810 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 811 u8 normal_rx_path; 812 u8 valid_path_set; /*@use for single rx path only*/ 813 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 814 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 815 u32 support_ic_type; /*@PHYDM supported IC*/ 816 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 817 u8 ic_ip_series; /*N/AC/JGR3*/ 818 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 819 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 820 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 821 u8 fw_version; 822 u8 fw_sub_version; 823 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 824 u8 rfe_type; 825 u8 board_type; 826 u8 package_type; 827 u16 type_glna; 828 u16 type_gpa; 829 u16 type_alna; 830 u16 type_apa; 831 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 832 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 833 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 834 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 835 u8 efuse0x3d7; /*@with Efuse number*/ 836 u8 efuse0x3d8; 837 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 838 u8 ext_lna_gain; /*@gain of external lna*/ 839 boolean is_in_hct_test; 840 u8 wifi_test; 841 boolean is_dual_mac_smart_concurrent; 842 u32 bk_support_ability; /*SD4 only*/ 843 u8 with_extenal_ant_switch; 844 /*@cck agc relative*/ 845 boolean cck_new_agc; 846 s8 cck_lna_gain_table[8]; 847 u8 cck_sat_cnt_th_init; 848 /*@-------------------------------------*/ 849 u32 phydm_sys_up_time; 850 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 851 u32 soft_ap_special_setting; 852 boolean boolean_dummy; 853 s8 s8_dummy; 854 u8 u8_dummy; 855 u16 u16_dummy; 856 u32 u32_dummy; 857 u8 rfe_hwsetting_band; 858 u8 p_advance_ota; 859 boolean hp_hw_id; 860 boolean BOOLEAN_temp; 861 boolean is_dfs_band; 862 u8 is_rx_blocking_en; 863 u16 fw_offload_ability; 864 boolean is_download_fw; 865 boolean en_dis_dpd; 866 u16 dis_dpd_rate; 867 u8 en_auto_bw_th; 868 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 869 u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; 870 u32 bp_0x9b0; 871 #endif 872 #if (RTL8822C_SUPPORT) 873 u8 ofdm_rxagc_l_bnd[16]; 874 boolean l_bnd_detect[16]; 875 u16 agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/ 876 u16 agc_rf_gain[16][64];/*[table][mp_gain_idx]*/ 877 u8 agc_table_cnt; 878 boolean is_agc_tab_pos_shift; 879 u8 agc_table_shift; 880 #endif 881 /*@-----------HOOK BEFORE REG INIT-----------*/ 882 /*@===========================================================*/ 883 /*@====[ CALL BY Reference ]=========================================*/ 884 /*@===========================================================*/ 885 886 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 887 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 888 u8 *band_type; /*@2.4G/5G = 0/1*/ 889 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 890 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 891 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 892 u8 *channel; /*@central CH number*/ 893 boolean *is_scan_in_process; 894 boolean *is_power_saving; 895 boolean *is_tdma; 896 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 897 u8 *antenna_test; 898 boolean *is_net_closed; 899 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 900 /*@--------- For 8723B IQK-------------------------------------*/ 901 boolean *is_1_antenna; 902 u8 *rf_default_path; /* @0:S1, 1:S0 */ 903 /*@-----------------------------------------------------------*/ 904 905 u16 *forced_data_rate; 906 u8 *enable_antdiv; 907 u8 *enable_pathdiv; 908 u8 *en_adap_soml; 909 u8 *edcca_mode; 910 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 911 boolean *is_fw_dw_rsvd_page_in_progress; 912 u32 *current_tx_tp; 913 u32 *current_rx_tp; 914 u8 *sounding_seq; 915 u32 *soft_ap_mode; 916 u8 *mp_mode; 917 u32 *interrupt_mask; 918 u8 *bb_op_mode; 919 u32 *manual_supportability; 920 u8 *dis_dym_bw_indication; 921 /*@===========================================================*/ 922 /*@====[ CALL BY VALUE ]===========================================*/ 923 /*@===========================================================*/ 924 925 u8 disable_phydm_watchdog; 926 boolean is_link_in_process; 927 boolean is_wifi_direct; 928 boolean is_wifi_display; 929 boolean is_linked; 930 boolean pre_is_linked; 931 boolean first_connect; 932 boolean first_disconnect; 933 boolean bsta_state; 934 u8 rssi_min; 935 u8 rssi_min_macid; 936 u8 pre_rssi_min; 937 u8 rssi_max; 938 u8 rssi_max_macid; 939 u8 rssi_min_by_path; 940 boolean is_mp_chip; 941 boolean is_one_entry_only; 942 u32 one_entry_macid; 943 u32 one_entry_tp; 944 u32 pre_one_entry_tp; 945 u8 pre_number_linked_client; 946 u8 number_linked_client; 947 u8 pre_number_active_client; 948 u8 number_active_client; 949 boolean is_disable_phy_api; 950 u8 rssi_a; 951 u8 rssi_b; 952 u8 rssi_c; 953 u8 rssi_d; 954 s8 rxsc_80; 955 s8 rxsc_40; 956 s8 rxsc_20; 957 s8 rxsc_l; 958 u64 rssi_trsw; 959 u64 rssi_trsw_h; 960 u64 rssi_trsw_l; 961 u64 rssi_trsw_iso; 962 u8 tx_ant_status; /*TX path enable*/ 963 u8 rx_ant_status; /*RX path enable*/ 964 #ifdef PHYDM_COMPILE_ABOVE_4SS 965 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 966 #endif 967 #ifdef PHYDM_COMPILE_ABOVE_3SS 968 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 969 #endif 970 #ifdef PHYDM_COMPILE_ABOVE_2SS 971 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 972 #endif 973 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 974 u8 cck_lna_idx; 975 u8 cck_vga_idx; 976 u8 curr_station_id; 977 u8 ofdm_agc_idx[4]; 978 u8 rx_rate; 979 u8 rate_ss; 980 u8 tx_rate; 981 u8 linked_interval; 982 u8 pre_channel; 983 u32 txagc_offset_value_a; 984 boolean is_txagc_offset_positive_a; 985 u32 txagc_offset_value_b; 986 boolean is_txagc_offset_positive_b; 987 u8 ap_total_num; 988 boolean flatness_type; 989 /*@[traffic]*/ 990 u8 traffic_load; 991 u8 pre_traffic_load; 992 u32 tx_tp; /*@Mbps*/ 993 u32 rx_tp; /*@Mbps*/ 994 u32 total_tp; /*@Mbps*/ 995 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 996 u64 cur_tx_ok_cnt; 997 u64 cur_rx_ok_cnt; 998 u64 last_tx_ok_cnt; 999 u64 last_rx_ok_cnt; 1000 u16 consecutive_idlel_time; /*@unit: second*/ 1001 /*@---------------------------*/ 1002 boolean is_bb_swing_offset_positive_a; 1003 boolean is_bb_swing_offset_positive_b; 1004 1005 /*@[DIG]*/ 1006 boolean MPDIG_2G; /*off MPDIG*/ 1007 u8 times_2g; /*@for MP DIG*/ 1008 u8 force_igi; /*@for debug*/ 1009 1010 /*@[TDMA-DIG]*/ 1011 u8 tdma_dig_timer_ms; 1012 u8 tdma_dig_state_number; 1013 u8 tdma_dig_low_upper_bond; 1014 u8 force_tdma_low_igi; 1015 u8 force_tdma_high_igi; 1016 u8 fix_expire_to_zero; 1017 boolean original_dig_restore; 1018 /*@---------------------------*/ 1019 1020 /*@[AntDiv]*/ 1021 u8 ant_div_type; 1022 u8 antdiv_rssi; 1023 u8 fat_comb_a; 1024 u8 fat_comb_b; 1025 u8 antdiv_intvl; 1026 u8 antdiv_delay; 1027 u8 ant_type; 1028 u8 ant_type2; 1029 u8 pre_ant_type; 1030 u8 pre_ant_type2; 1031 u8 antdiv_period; 1032 u8 evm_antdiv_period; 1033 u8 antdiv_select; 1034 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 1035 u8 stop_antdiv_rssi_th; 1036 u16 stop_antdiv_tp_diff_th; 1037 u16 stop_antdiv_tp_th; 1038 u8 antdiv_tp_period; 1039 u16 tp_active_th; 1040 u8 tp_active_occur; 1041 u8 path_select; 1042 u8 antdiv_evm_en; 1043 u8 bdc_holdstate; 1044 u8 antdiv_counter; 1045 /*@---------------------------*/ 1046 1047 u8 ndpa_period; 1048 boolean h2c_rarpt_connect; 1049 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 1050 u8 print_agc; 1051 u8 la_mode; 1052 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 1053 u8 current_rf_set_8821c; 1054 u8 default_rf_set_8821c; 1055 u8 current_ant_num_8821c; 1056 u8 default_ant_num_8821c; 1057 u8 rfe_type_expand; 1058 /*@-----------------------------------------------------------*/ 1059 /*@---For Adaptivtiy---------------------------------------------*/ 1060 s8 TH_L2H_default; 1061 s8 th_edcca_hl_diff_default; 1062 s8 th_l2h_ini; 1063 s8 th_edcca_hl_diff; 1064 boolean carrier_sense_enable; 1065 /*@-----------------------------------------------------------*/ 1066 u8 pre_dbg_priority; 1067 u8 nbi_set_result; 1068 u8 c2h_cmd_start; 1069 u8 fw_debug_trace[60]; 1070 u8 pre_c2h_seq; 1071 boolean fw_buff_is_enpty; 1072 u32 data_frame_num; 1073 /*@--- for spur detection ---------------------------------------*/ 1074 boolean en_reg_mntr_bb; 1075 boolean en_reg_mntr_rf; 1076 boolean en_reg_mntr_mac; 1077 boolean en_reg_mntr_byte; 1078 /*@--------------------------------------------------------------*/ 1079 #if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT) 1080 u8 dsde_sel; 1081 u8 nbi_path_sel; 1082 u8 csi_wgt; 1083 #endif 1084 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT) 1085 u8 csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */ 1086 /* ^ ^ ^ ^ ^ */ 1087 #endif 1088 /*@------------------------------------------*/ 1089 1090 /*@--- for noise detection ---------------------------------------*/ 1091 boolean is_noisy_state; 1092 boolean noisy_decision; /*@b_noisy*/ 1093 boolean pre_b_noisy; 1094 u32 noisy_decision_smooth; 1095 /*@-----------------------------------------------------------*/ 1096 1097 /*@--- for MCC ant weighting ------------------------------------*/ 1098 boolean is_stop_dym_ant_weighting; 1099 /*@-----------------------------------------------------------*/ 1100 1101 boolean is_disable_dym_ecs; 1102 boolean is_disable_dym_ant_weighting; 1103 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1104 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1105 1106 #if (RATE_ADAPTIVE_SUPPORT) 1107 u16 currmin_rpt_time; 1108 struct _phydm_txstatistic_ hw_stats; 1109 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1110 /*Use mac_id as array index. STA mac_id=0*/ 1111 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1112 #endif 1113 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1114 /*We need to colelct all support abilit to a proper area.*/ 1115 boolean ra_support88e; 1116 boolean *is_driver_stopped; 1117 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1118 boolean *pinit_adpt_in_progress; 1119 boolean is_user_assign_level; 1120 u8 RSSI_BT; /*@come from BT*/ 1121 1122 /*@---PSD Relative ---------------------------------------------*/ 1123 boolean is_psd_in_process; 1124 boolean is_psd_active; 1125 /*@-----------------------------------------------------------*/ 1126 1127 boolean bsomlenabled; /* @D-SoML control */ 1128 u8 no_ndp_cnts; 1129 u16 ndp_cnt_pre; 1130 boolean is_beamformed; 1131 u8 linked_bf_support; 1132 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1133 u32 n_iqk_cnt; 1134 u32 n_iqk_ok_cnt; 1135 u32 n_iqk_fail_cnt; 1136 1137 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1138 boolean config_bbrf; 1139 #endif 1140 boolean is_disable_power_training; 1141 boolean is_bt_continuous_turn; 1142 u8 enhance_pwr_th[3]; 1143 u8 set_pwr_th[3]; 1144 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1145 #ifdef BB_RAM_SUPPORT 1146 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1147 #endif 1148 u8 dynamic_tx_high_power_lvl; 1149 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1150 u8 last_dtp_lvl; 1151 u8 min_power_index; 1152 u32 tx_agc_ofdm_18_6; 1153 /*-------------------------------------------------------------*/ 1154 u8 rx_pkt_type; 1155 1156 #ifdef CONFIG_PHYDM_DFS_MASTER 1157 u8 dfs_region_domain; 1158 u8 *dfs_master_enabled; 1159 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1160 u8 radar_detect_dbg_parm_en; 1161 u32 radar_detect_reg_918; 1162 u32 radar_detect_reg_91c; 1163 u32 radar_detect_reg_920; 1164 u32 radar_detect_reg_924; 1165 1166 u32 radar_detect_reg_a40; 1167 u32 radar_detect_reg_a44; 1168 u32 radar_detect_reg_a48; 1169 u32 radar_detect_reg_a4c; 1170 u32 radar_detect_reg_a50; 1171 u32 radar_detect_reg_a54; 1172 1173 u32 radar_detect_reg_f54; 1174 u32 radar_detect_reg_f58; 1175 u32 radar_detect_reg_f5c; 1176 u32 radar_detect_reg_f70; 1177 u32 radar_detect_reg_f74; 1178 /*@---For zero-wait DFS---------------------------------------*/ 1179 boolean seg1_dfs_flag; 1180 /*@-----------------------------------------------------------*/ 1181 /*@-----------------------------------------------------------*/ 1182 #endif 1183 1184 /*@=== RTL8721D ===*/ 1185 #if (RTL8721D_SUPPORT) 1186 boolean cbw20_adc80; 1187 boolean invalid_mode; 1188 u8 power_voltage; 1189 u8 cca_cbw20_lev; 1190 u8 cca_cbw40_lev; 1191 u8 antdiv_gpio; 1192 u8 peak_detect_mode; 1193 #endif 1194 1195 /*@=== PHYDM Timer ========================================== (start)*/ 1196 1197 struct phydm_timer_list mpt_dig_timer; 1198 struct phydm_timer_list fast_ant_training_timer; 1199 #ifdef ODM_EVM_ENHANCE_ANTDIV 1200 struct phydm_timer_list evm_fast_ant_training_timer; 1201 #endif 1202 #ifdef PHYDM_TDMA_DIG_SUPPORT 1203 struct phydm_timer_list tdma_dig_timer; 1204 #endif 1205 struct phydm_timer_list sbdcnt_timer; 1206 1207 /*@=== PHYDM Workitem ======================================= (start)*/ 1208 1209 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1210 #if USE_WORKITEM 1211 RT_WORK_ITEM fast_ant_training_workitem; 1212 RT_WORK_ITEM ra_rpt_workitem; 1213 RT_WORK_ITEM sbdcnt_workitem; 1214 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1215 #ifdef PHYDM_TDMA_DIG_SUPPORT 1216 RT_WORK_ITEM phydm_tdma_dig_workitem; 1217 #endif 1218 #endif 1219 #endif 1220 1221 /*@=== PHYDM Structure ======================================== (start)*/ 1222 struct phydm_func_poiner phydm_func_handler; 1223 struct phydm_iot_center iot_table; 1224 1225 #ifdef ODM_CONFIG_BT_COEXIST 1226 struct phydm_bt_info bt_info_table; 1227 #endif 1228 1229 struct pkt_process_info pkt_proc_struct; 1230 struct phydm_adaptivity_struct adaptivity; 1231 #ifdef CONFIG_PHYDM_DFS_MASTER 1232 struct _DFS_STATISTICS dfs; 1233 #endif 1234 struct odm_noise_monitor noise_level; 1235 struct odm_phy_dbg_info phy_dbg_info; 1236 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1237 struct odm_phy_dbg_info phy_dbg_info_win_bkp; 1238 #endif 1239 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1240 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1241 #endif 1242 1243 #ifdef CONFIG_ADAPTIVE_SOML 1244 struct adaptive_soml dm_soml_table; 1245 #endif 1246 1247 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1248 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1249 struct _BF_DIV_COEX_ dm_bdc_table; 1250 #endif 1251 1252 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1253 struct smt_ant_honbo dm_sat_table; 1254 #endif 1255 #endif 1256 1257 #if (defined(CONFIG_SMART_ANTENNA)) 1258 struct smt_ant smtant_table; 1259 #endif 1260 1261 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1262 struct dm_rf_calibration_struct rf_calibrate_info; 1263 struct dm_iqk_info IQK_info; 1264 struct dm_dpk_info dpk_info; 1265 struct dm_dack_info dack_info; 1266 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1267 struct phydm_fat_struct dm_fat_table; 1268 struct sw_antenna_switch dm_swat_table; 1269 #endif 1270 struct phydm_dig_struct dm_dig_table; 1271 1272 #ifdef PHYDM_SUPPORT_CCKPD 1273 struct phydm_cckpd_struct dm_cckpd_table; 1274 1275 #ifdef PHYDM_DCC_ENHANCE 1276 struct phydm_dcc_struct dm_dcc_info; /*dig cckpd coex*/ 1277 #endif 1278 #endif 1279 1280 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1281 struct phydm_lna_sat_t dm_lna_sat_info; 1282 #endif 1283 1284 #ifdef CONFIG_MCC_DM 1285 struct _phydm_mcc_dm_ mcc_dm; 1286 #endif 1287 1288 #ifdef PHYDM_PRIMARY_CCA 1289 struct phydm_pricca_struct dm_pri_cca; 1290 #endif 1291 1292 struct ra_table dm_ra_table; 1293 struct phydm_fa_struct false_alm_cnt; 1294 #ifdef PHYDM_TDMA_DIG_SUPPORT 1295 struct phydm_fa_acc_struct false_alm_cnt_acc; 1296 #ifdef IS_USE_NEW_TDMA 1297 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1298 #endif 1299 #endif 1300 struct phydm_cfo_track_struct dm_cfo_track; 1301 struct ccx_info dm_ccx_info; 1302 1303 struct odm_power_trim_data power_trim_data; 1304 #if (RTL8822B_SUPPORT) 1305 struct drp_rtl8822b_struct phydm_rtl8822b; 1306 #endif 1307 1308 #ifdef CONFIG_PSD_TOOL 1309 struct psd_info dm_psd_table; 1310 #endif 1311 1312 #if (PHYDM_LA_MODE_SUPPORT) 1313 struct rt_adcsmp adcsmp; 1314 #endif 1315 1316 #if (defined(CONFIG_PATH_DIVERSITY)) 1317 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1318 #endif 1319 1320 #if (defined(CONFIG_ANT_DETECTION)) 1321 struct _ANT_DETECTED_INFO ant_detected_info; 1322 #endif 1323 1324 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1325 #ifdef PHYDM_BEAMFORMING_SUPPORT 1326 struct _RT_BEAMFORMING_INFO beamforming_info; 1327 #endif 1328 #endif 1329 #ifdef PHYDM_AUTO_DEGBUG 1330 struct phydm_auto_dbg_struct auto_dbg_table; 1331 #endif 1332 1333 struct phydm_pause_lv pause_lv_table; 1334 struct phydm_api_stuc api_table; 1335 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1336 struct phydm_pow_train_stuc pow_train_table; 1337 #endif 1338 1339 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1340 struct phydm_pmac_tx dm_pmac_tx_table; 1341 #endif 1342 1343 #ifdef PHYDM_MP_SUPPORT 1344 struct phydm_mp dm_mp_table; 1345 #endif 1346 1347 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 1348 struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; 1349 #endif 1350 /*@==========================================================*/ 1351 1352 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 1353 /*@-------------------phydm_phystatus report --------------------*/ 1354 struct phydm_physts dm_physts_table; 1355 #endif 1356 1357 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1358 1359 #if (RT_PLATFORM != PLATFORM_LINUX) 1360 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1361 #else 1362 }; 1363 #endif 1364 1365 #else /*@for AP,CE Team*/ 1366 }; 1367 #endif 1368 1369 enum phydm_adv_ota { 1370 PHYDM_PATHB_1RCCA = BIT(0), 1371 PHYDM_HP_OTA_SETTING_A = BIT(1), 1372 PHYDM_HP_OTA_SETTING_B = BIT(2), 1373 PHYDM_ASUS_OTA_SETTING = BIT(3), 1374 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1375 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1376 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1377 1378 }; 1379 1380 enum phydm_bb_op_mode { 1381 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1382 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1383 }; 1384 1385 enum phydm_structure_type { 1386 PHYDM_FALSEALMCNT, 1387 PHYDM_CFOTRACK, 1388 PHYDM_ADAPTIVITY, 1389 PHYDM_DFS, 1390 PHYDM_ROMINFO, 1391 1392 }; 1393 1394 enum odm_bb_config_type { 1395 CONFIG_BB_PHY_REG, 1396 CONFIG_BB_AGC_TAB, 1397 CONFIG_BB_AGC_TAB_2G, 1398 CONFIG_BB_AGC_TAB_5G, 1399 CONFIG_BB_PHY_REG_PG, 1400 CONFIG_BB_PHY_REG_MP, 1401 CONFIG_BB_AGC_TAB_DIFF, 1402 CONFIG_BB_RF_CAL_INIT, 1403 }; 1404 1405 enum odm_rf_config_type { 1406 CONFIG_RF_RADIO, 1407 CONFIG_RF_TXPWR_LMT, 1408 CONFIG_RF_SYN_RADIO, 1409 }; 1410 1411 enum odm_fw_config_type { 1412 CONFIG_FW_NIC, 1413 CONFIG_FW_NIC_2, 1414 CONFIG_FW_AP, 1415 CONFIG_FW_AP_2, 1416 CONFIG_FW_MP, 1417 CONFIG_FW_WOWLAN, 1418 CONFIG_FW_WOWLAN_2, 1419 CONFIG_FW_AP_WOWLAN, 1420 CONFIG_FW_BT, 1421 }; 1422 1423 /*status code*/ 1424 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1425 enum rt_status { 1426 RT_STATUS_SUCCESS, 1427 RT_STATUS_FAILURE, 1428 RT_STATUS_PENDING, 1429 RT_STATUS_RESOURCE, 1430 RT_STATUS_INVALID_CONTEXT, 1431 RT_STATUS_INVALID_PARAMETER, 1432 RT_STATUS_NOT_SUPPORT, 1433 RT_STATUS_OS_API_FAILED, 1434 }; 1435 #endif /*@end of enum rt_status definition*/ 1436 1437 void 1438 phydm_watchdog_lps(struct dm_struct *dm); 1439 1440 void 1441 phydm_watchdog_lps_32k(struct dm_struct *dm); 1442 1443 void 1444 phydm_txcurrentcalibration(struct dm_struct *dm); 1445 1446 void 1447 phydm_dm_early_init(struct dm_struct *dm); 1448 1449 enum phydm_init_result 1450 odm_dm_init(struct dm_struct *dm); 1451 1452 void 1453 odm_dm_reset(struct dm_struct *dm); 1454 1455 void 1456 phydm_fwoffload_ability_init(struct dm_struct *dm, 1457 enum phydm_offload_ability offload_ability); 1458 1459 void 1460 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1461 enum phydm_offload_ability offload_ability); 1462 1463 void 1464 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1465 char *output, u32 *_out_len); 1466 1467 void 1468 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1469 1470 void 1471 phydm_watchdog(struct dm_struct *dm); 1472 1473 void 1474 phydm_watchdog_mp(struct dm_struct *dm); 1475 1476 void 1477 phydm_pause_func_init(void *dm_void); 1478 1479 u8 1480 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1481 enum phydm_pause_type pause_type, 1482 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1483 1484 void 1485 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1486 char *output, u32 *_out_len); 1487 1488 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, 1489 enum phydm_pause_type pause_type, u8 rssi); 1490 1491 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, 1492 boolean enable); 1493 1494 void 1495 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1496 1497 void 1498 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1499 1500 void 1501 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1502 1503 u32 1504 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1505 1506 void 1507 odm_init_all_timers(struct dm_struct *dm); 1508 1509 void 1510 odm_cancel_all_timers(struct dm_struct *dm); 1511 1512 void 1513 odm_release_all_timers(struct dm_struct *dm); 1514 1515 void * 1516 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1517 1518 void 1519 phydm_dc_cancellation(struct dm_struct *dm); 1520 1521 void 1522 phydm_receiver_blocking(void *dm_void); 1523 1524 void 1525 phydm_dyn_bw_indication(void *dm_void); 1526 1527 void 1528 phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en); 1529 1530 1531 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH 1532 void 1533 phydm_tx_collsion_th_init(void *dm_void); 1534 1535 void 1536 phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r); 1537 #endif 1538 1539 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1540 void 1541 odm_init_all_work_items( 1542 struct dm_struct *dm 1543 ); 1544 void 1545 odm_free_all_work_items( 1546 struct dm_struct *dm 1547 ); 1548 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1549 1550 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1551 void 1552 odm_dtc(struct dm_struct *dm); 1553 #endif 1554 1555 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1556 void 1557 odm_init_all_threads( 1558 struct dm_struct *dm 1559 ); 1560 1561 void 1562 odm_stop_all_threads( 1563 struct dm_struct *dm 1564 ); 1565 #endif 1566 1567 #endif 1568