1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2014 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #include <drv_types.h>
18 #include <hal_data.h>
19
20 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)21 enum odm_board_type boardType(u8 InterfaceSel)
22 {
23 enum odm_board_type board = ODM_BOARD_DEFAULT;
24
25 #ifdef CONFIG_PCI_HCI
26 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
27 switch (pcie) {
28 case INTF_SEL0_SOLO_MINICARD:
29 board |= ODM_BOARD_MINICARD;
30 break;
31 case INTF_SEL1_BT_COMBO_MINICARD:
32 board |= ODM_BOARD_BT;
33 board |= ODM_BOARD_MINICARD;
34 break;
35 default:
36 board = ODM_BOARD_DEFAULT;
37 break;
38 }
39
40 #elif defined(CONFIG_USB_HCI)
41 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
42 switch (usb) {
43 case INTF_SEL1_USB_High_Power:
44 board |= ODM_BOARD_EXT_LNA;
45 board |= ODM_BOARD_EXT_PA;
46 break;
47 case INTF_SEL2_MINICARD:
48 board |= ODM_BOARD_MINICARD;
49 break;
50 case INTF_SEL4_USB_Combo:
51 board |= ODM_BOARD_BT;
52 break;
53 case INTF_SEL5_USB_Combo_MF:
54 board |= ODM_BOARD_BT;
55 break;
56 case INTF_SEL0_USB:
57 case INTF_SEL3_USB_Solo:
58 default:
59 board = ODM_BOARD_DEFAULT;
60 break;
61 }
62
63 #endif
64 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
65
66 return board;
67 }
68
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)69 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
70 {
71 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
72 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
73
74 if (hal->RegIQKFWOffload) {
75 rtw_sctx_init(&hal->iqk_sctx, 0);
76 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
77 } else
78 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
79
80 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
81
82 if (rtw_mi_check_status(adapter, MI_LINKED)) {
83 #ifdef CONFIG_LPS
84 LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
85 #endif
86 halrf_iqk_trigger(p_dm_odm, _FALSE);
87 }
88 }
89
90 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
91 || (RTL8723F_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)92 void rtw_phydm_iqk_trigger(_adapter *adapter)
93 {
94 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
95 u8 clear = _TRUE;
96 u8 segment = _FALSE;
97 u8 rfk_forbidden = _FALSE;
98
99 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
100 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
101 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
102 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
103 #else
104 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
105 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
106 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
107 #endif
108 }
109 #endif
110
rtw_phydm_iqk_trigger_all(_adapter * adapter)111 void rtw_phydm_iqk_trigger_all(_adapter *adapter)
112 {
113 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
114 u8 clear = _TRUE;
115 u8 segment = _FALSE;
116 u8 rfk_forbidden = _FALSE;
117
118 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
119 || (RTL8723F_SUPPORT == 1))
120 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
121 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
122 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
123 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
124 #else
125 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
126 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
127 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
128 #endif /* (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) (RTL8723F_SUPPORT == 1) */
129 #else
130 halrf_iqk_trigger(p_dm_odm, _FALSE);
131 #endif /* ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
132 (RTL8723F_SUPPORT == 1) */
133 }
134
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)135 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
136 {
137 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
138
139 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
140 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
141 #else
142 halrf_iqk_trigger(p_dm_odm, recovery);
143 #endif
144 }
rtw_phydm_lck_trigger(_adapter * adapter)145 void rtw_phydm_lck_trigger(_adapter *adapter)
146 {
147 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
148
149 halrf_lck_trigger(p_dm_odm);
150 }
151
rtw_hal_phydm_cal_trigger(_adapter * adapter)152 void rtw_hal_phydm_cal_trigger(_adapter *adapter)
153 {
154 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
155
156 rtw_ps_deny(adapter, PS_DENY_IOCTL);
157 LeaveAllPowerSaveModeDirect(adapter);
158
159 rtw_phydm_iqk_trigger_all(adapter);
160
161 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
162 }
163
164 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)165 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
166 {
167 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
168
169 rtw_ps_deny(adapter, PS_DENY_IOCTL);
170 LeaveAllPowerSaveModeDirect(adapter);
171
172 rtw_phydm_ability_backup(adapter);
173 rtw_phydm_func_disable_all(adapter);
174
175 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
176
177 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
178 rtw_phydm_ability_restore(adapter);
179
180 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
181 }
182
rtw_hal_lck_test(_adapter * adapter)183 void rtw_hal_lck_test(_adapter *adapter)
184 {
185 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
186
187 rtw_ps_deny(adapter, PS_DENY_IOCTL);
188 LeaveAllPowerSaveModeDirect(adapter);
189
190 rtw_phydm_ability_backup(adapter);
191 rtw_phydm_func_disable_all(adapter);
192
193 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
194
195 rtw_phydm_lck_trigger(adapter);
196
197 rtw_phydm_ability_restore(adapter);
198 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
199 }
200 #endif
201
202 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)203 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
204 {
205 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
206
207 if (adapter->registrypriv.fw_param_init)
208 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
209 else
210 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
211
212 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
213 }
214 #endif
215
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)216 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
217 {
218 struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
219 _adapter *adapter = p_dm->adapter;
220 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
221 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
222
223 if (p_sta) {
224 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
225 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
226 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
227 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
228
229 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
230 }
231 }
232
233 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
rtw_phydm_fill_desc_dpt(void * dm,u8 * desc,u8 dpt_lv)234 void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
235 {
236 struct dm_struct *p_dm = (struct dm_struct *)dm;
237 _adapter *adapter = p_dm->adapter;
238
239 switch (rtw_get_chip_type(adapter)) {
240 /*
241 #ifdef CONFIG_RTL8188F
242 case RTL8188F:
243 break;
244 #endif
245
246 #ifdef CONFIG_RTL8723B
247 case RTL8723B :
248 break;
249 #endif
250
251 #ifdef CONFIG_RTL8703B
252 case RTL8703B :
253 break;
254 #endif
255
256 #ifdef CONFIG_RTL8812A
257 case RTL8812 :
258 break;
259 #endif
260
261 #ifdef CONFIG_RTL8821A
262 case RTL8821:
263 break;
264 #endif
265
266 #ifdef CONFIG_RTL8814A
267 case RTL8814A :
268 break;
269 #endif
270
271 #ifdef CONFIG_RTL8192F
272 case RTL8192F :
273 break;
274 #endif
275 */
276 /*
277 #ifdef CONFIG_RTL8192E
278 case RTL8192E :
279 SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
280 break;
281 #endif
282 */
283 #ifdef CONFIG_RTL8822B
284 case RTL8822B :
285 SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
286 break;
287 #endif
288
289 #ifdef CONFIG_RTL8821C
290 case RTL8821C :
291 SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
292 break;
293 #endif
294
295 default :
296 RTW_ERR("%s IC not support dynamic tx power\n", __func__);
297 break;
298 }
299 }
rtw_phydm_set_dyntxpwr(_adapter * adapter,u8 * desc,u8 mac_id)300 void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
301 {
302 struct dm_struct *dm = adapter_to_phydm(adapter);
303
304 odm_set_dyntxpwr(dm, desc, mac_id);
305 }
306 #endif
307
308 #ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(_adapter * adapter,u8 state)309 void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
310 {
311 struct registry_priv *pregistrypriv = &adapter->registrypriv;
312 struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
313 struct dm_struct *dm = adapter_to_phydm(adapter);
314 u8 tdma_dig_en;
315
316 switch (state) {
317 case TDMADIG_INIT:
318 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
319 phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
320 break;
321 case TDMADIG_NON_INIT:
322 if(pregistrypriv->tdmadig_dynamic) {
323 if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
324 tdma_dig_en = 0;
325 else
326 tdma_dig_en = pregistrypriv->tdmadig_en;
327 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
328 }
329 break;
330 default:
331 break;
332
333 }
334 }
335 #endif/*CONFIG_TDMADIG*/
rtw_phydm_ops_func_init(struct dm_struct * p_phydm)336 void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
337 {
338 struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
339
340 p_ra_t->record_ra_info = record_ra_info;
341 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
342 p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
343 #endif
344 }
rtw_phydm_priv_init(_adapter * adapter)345 void rtw_phydm_priv_init(_adapter *adapter)
346 {
347 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
348 struct dm_struct *phydm = &(hal->odmpriv);
349
350 phydm->adapter = adapter;
351 odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
352 }
353
Init_ODM_ComInfo(_adapter * adapter)354 void Init_ODM_ComInfo(_adapter *adapter)
355 {
356 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
357 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
358 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
359 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
360 int i;
361
362 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
363 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
364 rtw_odm_init_ic_type(adapter);
365
366 if (rtw_get_intf_type(adapter) == RTW_GSPI)
367 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
368 else
369 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
370
371 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
372
373 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
374
375 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
376
377 #ifdef CONFIG_ADVANCE_OTA
378 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
379 #endif
380 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
381
382 {
383 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
384 u8 odm_board_type = ODM_BOARD_DEFAULT;
385
386 if (pHalData->ExternalLNA_2G != 0) {
387 odm_board_type |= ODM_BOARD_EXT_LNA;
388 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
389 }
390 if (pHalData->external_lna_5g != 0) {
391 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
392 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
393 }
394 if (pHalData->ExternalPA_2G != 0) {
395 odm_board_type |= ODM_BOARD_EXT_PA;
396 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
397 }
398 if (pHalData->external_pa_5g != 0) {
399 odm_board_type |= ODM_BOARD_EXT_PA_5G;
400 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
401 }
402 if (pHalData->EEPROMBluetoothCoexist)
403 odm_board_type |= ODM_BOARD_BT;
404
405 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
406 /* 1 ============== End of BoardType ============== */
407 }
408
409 rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
410
411 #ifdef CONFIG_DFS_MASTER
412 rtw_odm_update_dfs_region(dvobj);
413 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
414 #endif
415
416 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
417 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
418 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
419 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
420
421 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
422 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
423
424 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
425
426 /*Add by YuChen for kfree init*/
427 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
428 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
429
430 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
431 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
432 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
433
434 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
435 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
436 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
437
438 /* waiting for PhyDMV034 support*/
439 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
440 /*Add by YuChen for adaptivity init*/
441 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
442 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
443 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
444 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
445
446 /*halrf info init*/
447 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
448 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
449 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
450
451 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
452 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
453
454 #ifdef CONFIG_IQK_PA_OFF
455 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
456 #endif
457 rtw_hal_update_iqk_fw_offload_cap(adapter);
458 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
459 rtw_hal_update_param_init_fw_offload_cap(adapter);
460 #endif
461
462 /* Pointer reference */
463 /*Antenna diversity relative parameters*/
464 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
465 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
466
467 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
468 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
469 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
470
471 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
472 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
473
474 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
475 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
476 #ifdef CONFIG_NARROWBAND_SUPPORTING
477 if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
478 || (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
479 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
480 }
481 else
482 #endif
483 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
484 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
485 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
486
487 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
488 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
489 /*Add by Yuchen for phydm beamforming*/
490 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
491 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
492 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
493 #ifdef CONFIG_RTL8723B
494 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
495 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
496 #endif /*CONFIG_RTL8723B*/
497 #ifdef CONFIG_USB_HCI
498 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
499 #endif
500
501 #ifdef CONFIG_DYNAMIC_SOML
502 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
503 #endif
504 #ifdef CONFIG_RTW_PATH_DIV
505 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
506 #endif
507 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
508
509 /*halrf info hook*/
510 /* waiting for PhyDMV034 support*/
511 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
512 #ifdef CONFIG_MP_INCLUDED
513 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
514 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
515 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
516 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
517 #endif/*CONFIG_MP_INCLUDED*/
518 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
519 phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
520
521 rtw_phydm_ops_func_init(pDM_Odm);
522 phydm_dm_early_init(pDM_Odm);
523 /* TODO */
524 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
525 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
526 }
527
528
529 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
530 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
531 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
532 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
533
534 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
535 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
536 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
537 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
538
539 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
540 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
541 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
542 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
543
544
545 struct turbo_edca_setting{
546 u32 edca_ul; /* uplink, tx */
547 u32 edca_dl; /* downlink, rx */
548 };
549
550 #define TURBO_EDCA_ENT(UL, DL) {UL, DL}
551
552 #if 0
553 #define TURBO_EDCA_MODE_NUM 18
554 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
555 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
556 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
557 TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
558
559 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
560 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
561 TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
562
563 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
564 TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
565 TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
566
567 TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
568 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
569 TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
570
571 TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
572 TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
573 TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
574
575 TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
576
577 TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
578
579 TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
580 };
581 #else
582 #define TURBO_EDCA_MODE_NUM 8
583 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
584 /* { UL, DL } */
585 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
586
587 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
588
589 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
590
591 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
592
593 TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
594
595 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
596
597 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
598
599 TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
600 };
601 #endif
602
rtw_hal_turbo_edca(_adapter * adapter)603 void rtw_hal_turbo_edca(_adapter *adapter)
604 {
605 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
606 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
607 struct recv_priv *precvpriv = &(adapter->recvpriv);
608 struct registry_priv *pregpriv = &adapter->registrypriv;
609 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
610 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
611
612 /* Parameter suggested by Scott */
613 #if 0
614 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
615 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
616 #endif
617 u32 EDCA_BE_UL = 0x5ea42b;
618 u32 EDCA_BE_DL = 0x00a42b;
619 u8 ic_type = rtw_get_chip_type(adapter);
620
621 u8 iot_peer = 0;
622 u8 wireless_mode = 0xFF; /* invalid value */
623 u8 traffic_index;
624 u32 edca_param;
625 u64 cur_tx_bytes = 0;
626 u64 cur_rx_bytes = 0;
627 u8 bbtchange = _TRUE;
628 u8 is_bias_on_rx = _FALSE;
629 u8 is_linked = _FALSE;
630 u8 interface_type;
631
632 if (hal_data->dis_turboedca == 1)
633 return;
634
635 if (rtw_mi_check_status(adapter, MI_ASSOC))
636 is_linked = _TRUE;
637
638 if (is_linked != _TRUE) {
639 precvpriv->is_any_non_be_pkts = _FALSE;
640 return;
641 }
642
643 if (pregpriv->wifi_spec == 1) { /* || (pmlmeinfo->HT_enable == 0)) */
644 precvpriv->is_any_non_be_pkts = _FALSE;
645 return;
646 }
647
648 interface_type = rtw_get_intf_type(adapter);
649 wireless_mode = pmlmeext->cur_wireless_mode;
650
651 iot_peer = pmlmeinfo->assoc_AP_vendor;
652
653 if (iot_peer >= HT_IOT_PEER_MAX) {
654 precvpriv->is_any_non_be_pkts = _FALSE;
655 return;
656 }
657
658 if (ic_type == RTL8188E) {
659 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
660 is_bias_on_rx = _TRUE;
661 }
662
663 /* Check if the status needs to be changed. */
664 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
665 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
666 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
667
668 /* traffic, TX or RX */
669 if (is_bias_on_rx) {
670 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
671 /* Uplink TP is present. */
672 traffic_index = UP_LINK;
673 } else {
674 /* Balance TP is present. */
675 traffic_index = DOWN_LINK;
676 }
677 } else {
678 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
679 /* Downlink TP is present. */
680 traffic_index = DOWN_LINK;
681 } else {
682 /* Balance TP is present. */
683 traffic_index = UP_LINK;
684 }
685 }
686 #if 0
687 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
688 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
689 #endif
690 {
691 if (interface_type == RTW_PCIE) {
692 EDCA_BE_UL = 0x6ea42b;
693 EDCA_BE_DL = 0x6ea42b;
694 }
695
696 /* 92D txop can't be set to 0x3e for cisco1250 */
697 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
698 EDCA_BE_DL = edca_setting_DL[iot_peer];
699 EDCA_BE_UL = edca_setting_UL[iot_peer];
700 }
701 /* merge from 92s_92c_merge temp*/
702 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
703 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
704 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
705 EDCA_BE_DL = 0xa630;
706 else if (iot_peer == HT_IOT_PEER_MARVELL) {
707 EDCA_BE_DL = edca_setting_DL[iot_peer];
708 EDCA_BE_UL = edca_setting_UL[iot_peer];
709 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
710 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
711 /* Suggested by SD3 Wilson for ASUS TP issue.*/
712 EDCA_BE_DL = edca_setting_DL[iot_peer];
713 }
714
715 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
716 EDCA_BE_UL = 0x5ea42b;
717 EDCA_BE_DL = 0x5ea42b;
718
719 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
720 }
721
722 if (interface_type == RTW_PCIE &&
723 ((ic_type == RTL8822B)
724 || (ic_type == RTL8822C)
725 || (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
726 EDCA_BE_UL = 0x6ea42b;
727 EDCA_BE_DL = 0x6ea42b;
728 }
729
730 if ((ic_type == RTL8822B)
731 && (interface_type == RTW_SDIO))
732 EDCA_BE_DL = 0x00431c;
733
734 #ifdef CONFIG_RTW_TPT_MODE
735 if ( dvobj->tpt_mode > 0 ) {
736 EDCA_BE_UL = dvobj->edca_be_ul;
737 EDCA_BE_DL = dvobj->edca_be_dl;
738 }
739 #endif /* CONFIG_RTW_TPT_MODE */
740
741 /* keep this condition at last check */
742 if (hal_data->dis_turboedca == 2) {
743
744 if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
745
746 struct turbo_edca_setting param;
747
748 param = rtw_turbo_edca[hal_data->edca_param_mode];
749
750 EDCA_BE_UL = param.edca_ul;
751 EDCA_BE_DL = param.edca_dl;
752
753 } else {
754
755 EDCA_BE_UL = hal_data->edca_param_mode;
756 EDCA_BE_DL = hal_data->edca_param_mode;
757 }
758 }
759
760 if (traffic_index == DOWN_LINK)
761 edca_param = EDCA_BE_DL;
762 else
763 edca_param = EDCA_BE_UL;
764
765 #ifdef CONFIG_EXTEND_LOWRATE_TXOP
766 #define TXOP_CCK1M 0x01A6
767 #define TXOP_CCK2M 0x00E6
768 #define TXOP_CCK5M 0x006B
769 #define TXOP_OFD6M 0x0066
770 #define TXOP_MCS6M 0x0061
771 {
772 struct sta_info *psta;
773 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
774 u8 mac_id, role, current_rate_id;
775
776 /* search all used & connect2AP macid */
777 for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
778 if (rtw_macid_is_used(macid_ctl, mac_id)) {
779 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
780 if (role != H2C_MSR_ROLE_AP)
781 continue;
782
783 psta = macid_ctl->sta[mac_id];
784 current_rate_id = rtw_get_current_tx_rate(adapter, psta);
785 /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
786 switch (current_rate_id) {
787 case DESC_RATE1M:
788 edca_param &= 0x0000FFFF;
789 edca_param |= (TXOP_CCK1M<<16);
790 break;
791 case DESC_RATE2M:
792 edca_param &= 0x0000FFFF;
793 edca_param |= (TXOP_CCK2M<<16);
794 break;
795 case DESC_RATE5_5M:
796 edca_param &= 0x0000FFFF;
797 edca_param |= (TXOP_CCK5M<<16);
798 break;
799 case DESC_RATE6M:
800 edca_param &= 0x0000FFFF;
801 edca_param |= (TXOP_OFD6M<<16);
802 break;
803 case DESC_RATEMCS0:
804 edca_param &= 0x0000FFFF;
805 edca_param |= (TXOP_MCS6M<<16);
806 break;
807 default:
808 break;
809 }
810 }
811 }
812 }
813 #endif /* CONFIG_EXTEND_LOWRATE_TXOP */
814
815 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
816 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
817 #endif
818
819 if ( edca_param != hal_data->ac_param_be) {
820
821 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
822
823 RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
824 }
825
826 hal_data->prv_traffic_idx = traffic_index;
827 }
828
829 hal_data->is_turbo_edca = _TRUE;
830 } else {
831 /* */
832 /* Turn Off EDCA turbo here. */
833 /* Restore original EDCA according to the declaration of AP. */
834 /* */
835 if (hal_data->is_turbo_edca) {
836 edca_param = hal_data->ac_param_be;
837 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
838 hal_data->is_turbo_edca = _FALSE;
839 }
840 }
841
842 }
843
rtw_dm_get_min_rssi(_adapter * adapter)844 s8 rtw_dm_get_min_rssi(_adapter *adapter)
845 {
846 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
847 struct sta_info *sta;
848 s8 min_rssi = 127, rssi;
849 int i;
850
851 for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
852 sta = macid_ctl->sta[i];
853 if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
854 || is_broadcast_mac_addr(sta->cmn.mac_addr))
855 continue;
856 rssi = sta->cmn.rssi_stat.rssi;
857 if (rssi >= 0 && min_rssi > rssi)
858 min_rssi = rssi;
859 }
860
861 return min_rssi == 127 ? 0 : min_rssi;
862 }
863
rtw_phydm_get_min_rssi(_adapter * adapter)864 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
865 {
866 struct dm_struct *phydm = adapter_to_phydm(adapter);
867 s8 rssi_min = 0;
868
869 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
870 return rssi_min;
871 }
872
rtw_phydm_get_cur_igi(_adapter * adapter)873 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
874 {
875 struct dm_struct *phydm = adapter_to_phydm(adapter);
876 u8 cur_igi = 0;
877
878 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
879 return cur_igi;
880 }
881
rtw_phydm_get_edcca_flag(_adapter * adapter)882 bool rtw_phydm_get_edcca_flag(_adapter *adapter)
883 {
884 struct dm_struct *phydm = adapter_to_phydm(adapter);
885 bool cur_edcca_flag = 0;
886
887 cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
888 return cur_edcca_flag;
889 }
890
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)891 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
892 {
893 struct dm_struct *phydm = adapter_to_phydm(adapter);
894
895 if (cnt == FA_OFDM)
896 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
897 else if (cnt == FA_CCK)
898 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
899 else if (cnt == FA_TOTAL)
900 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
901 else if (cnt == CCA_OFDM)
902 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
903 else if (cnt == CCA_CCK)
904 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
905 else if (cnt == CCA_ALL)
906 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
907 else if (cnt == CRC32_OK_VHT)
908 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
909 else if (cnt == CRC32_OK_HT)
910 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
911 else if (cnt == CRC32_OK_LEGACY)
912 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
913 else if (cnt == CRC32_OK_CCK)
914 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
915 else if (cnt == CRC32_ERROR_VHT)
916 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
917 else if (cnt == CRC32_ERROR_HT)
918 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
919 else if (cnt == CRC32_ERROR_LEGACY)
920 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
921 else if (cnt == CRC32_ERROR_CCK)
922 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
923 else
924 return 0;
925 }
926
rtw_phydm_is_iqk_in_progress(_adapter * adapter)927 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
928 {
929 u8 rts = _FALSE;
930 struct dm_struct *podmpriv = adapter_to_phydm(adapter);
931
932 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
933 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
934 RTW_ERR("IQK InProgress\n");
935 rts = _TRUE;
936 }
937 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
938
939 return rts;
940 }
941
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)942 void SetHalODMVar(
943 PADAPTER Adapter,
944 HAL_ODM_VARIABLE eVariable,
945 void *pValue1,
946 BOOLEAN bSet)
947 {
948 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
949 /* _irqL irqL; */
950 switch (eVariable) {
951 case HAL_ODM_STA_INFO: {
952 struct sta_info *psta = (struct sta_info *)pValue1;
953
954 if (bSet) {
955 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
956 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
957 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
958 } else {
959 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
960 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
961 psta->cmn.dm_ctrl = 0;
962 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
963
964 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
965 }
966 }
967 break;
968 case HAL_ODM_P2P_STATE:
969 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
970 break;
971 case HAL_ODM_WIFI_DISPLAY_STATE:
972 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
973 break;
974 case HAL_ODM_REGULATION:
975 /* used to auto enable/disable adaptivity by SD7 */
976 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
977 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
978 break;
979 case HAL_ODM_INITIAL_GAIN: {
980 u8 rx_gain = *((u8 *)(pValue1));
981 /*printk("rx_gain:%x\n",rx_gain);*/
982 if (rx_gain == 0xff) {/*restore rx gain*/
983 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
984 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
985 } else {
986 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
987 /*odm_write_dig(podmpriv,rx_gain);*/
988 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
989 }
990 }
991 break;
992 case HAL_ODM_RX_INFO_DUMP: {
993 u8 cur_igi = 0;
994 s8 rssi_min;
995 void *sel;
996
997 sel = pValue1;
998 cur_igi = rtw_phydm_get_cur_igi(Adapter);
999 rssi_min = rtw_phydm_get_min_rssi(Adapter);
1000
1001 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
1002 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
1003 , podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
1004 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
1005 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
1006 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
1007 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
1008
1009 if (podmpriv->is_linked) {
1010 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
1011 if (IS_HARDWARE_TYPE_8814A(Adapter))
1012 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
1013 podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
1014 else
1015 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
1016 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1017 rtw_dump_raw_rssi_info(Adapter, sel);
1018 #endif
1019 }
1020 }
1021 break;
1022 case HAL_ODM_RX_Dframe_INFO: {
1023 void *sel;
1024
1025 sel = pValue1;
1026
1027 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
1028 #ifdef DBG_RX_DFRAME_RAW_DATA
1029 rtw_dump_rx_dframe_info(Adapter, sel);
1030 #endif
1031 }
1032 break;
1033
1034 #ifdef CONFIG_ANTENNA_DIVERSITY
1035 case HAL_ODM_ANTDIV_SELECT: {
1036 u8 antenna = (*(u8 *)pValue1);
1037 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1038 /*switch antenna*/
1039 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
1040 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
1041
1042 }
1043 break;
1044 #endif
1045
1046 default:
1047 break;
1048 }
1049 }
1050
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1051 void GetHalODMVar(
1052 PADAPTER Adapter,
1053 HAL_ODM_VARIABLE eVariable,
1054 void *pValue1,
1055 void *pValue2)
1056 {
1057 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
1058
1059 switch (eVariable) {
1060 #ifdef CONFIG_ANTENNA_DIVERSITY
1061 case HAL_ODM_ANTDIV_SELECT: {
1062 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
1063 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
1064 }
1065 break;
1066 #endif
1067 case HAL_ODM_INITIAL_GAIN:
1068 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
1069 break;
1070 default:
1071 break;
1072 }
1073 }
1074
1075 #ifdef RTW_HALMAC
1076 #include "../hal_halmac.h"
1077 #endif
rtw_phydm_rfe_ctrl_gpio(_adapter * adapter,u8 gpio_num)1078 bool rtw_phydm_rfe_ctrl_gpio(
1079 _adapter *adapter,
1080 u8 gpio_num
1081 )
1082 {
1083 #ifdef RTW_HALMAC
1084 if(rtw_halmac_rfe_ctrl_cfg(adapter_to_dvobj(adapter), gpio_num))
1085 return _TRUE;
1086 else
1087 #endif/*RTW_HALMAC*/
1088 return _FALSE;
1089 }
1090
1091 enum hal_status
rtw_phydm_fw_iqk(struct dm_struct * p_dm_odm,u8 clear,u8 segment)1092 rtw_phydm_fw_iqk(
1093 struct dm_struct *p_dm_odm,
1094 u8 clear,
1095 u8 segment
1096 )
1097 {
1098 #ifdef RTW_HALMAC
1099 struct _ADAPTER *adapter = p_dm_odm->adapter;
1100
1101 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
1102 return HAL_STATUS_SUCCESS;
1103 #endif
1104 return HAL_STATUS_FAILURE;
1105 }
1106
1107 enum hal_status
rtw_phydm_cfg_phy_para(struct dm_struct * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)1108 rtw_phydm_cfg_phy_para(
1109 struct dm_struct *p_dm_odm,
1110 enum phydm_halmac_param config_type,
1111 u32 offset,
1112 u32 data,
1113 u32 mask,
1114 enum rf_path e_rf_path,
1115 u32 delay_time)
1116 {
1117 #ifdef RTW_HALMAC
1118 struct _ADAPTER *adapter = p_dm_odm->adapter;
1119 struct rtw_phy_parameter para;
1120
1121 switch (config_type) {
1122 case PHYDM_HALMAC_CMD_MAC_W8:
1123 para.cmd = 0; /* MAC register */
1124 para.data.mac.offset = offset;
1125 para.data.mac.value = data;
1126 para.data.mac.msk = mask;
1127 para.data.mac.msk_en = (mask) ? 1 : 0;
1128 para.data.mac.size = 1;
1129 break;
1130 case PHYDM_HALMAC_CMD_MAC_W16:
1131 para.cmd = 0; /* MAC register */
1132 para.data.mac.offset = offset;
1133 para.data.mac.value = data;
1134 para.data.mac.msk = mask;
1135 para.data.mac.msk_en = (mask) ? 1 : 0;
1136 para.data.mac.size = 2;
1137 break;
1138 case PHYDM_HALMAC_CMD_MAC_W32:
1139 para.cmd = 0; /* MAC register */
1140 para.data.mac.offset = offset;
1141 para.data.mac.value = data;
1142 para.data.mac.msk = mask;
1143 para.data.mac.msk_en = (mask) ? 1 : 0;
1144 para.data.mac.size = 4;
1145 break;
1146 case PHYDM_HALMAC_CMD_BB_W8:
1147 para.cmd = 1; /* BB register */
1148 para.data.bb.offset = offset;
1149 para.data.bb.value = data;
1150 para.data.bb.msk = mask;
1151 para.data.bb.msk_en = (mask) ? 1 : 0;
1152 para.data.bb.size = 1;
1153 break;
1154 case PHYDM_HALMAC_CMD_BB_W16:
1155 para.cmd = 1; /* BB register */
1156 para.data.bb.offset = offset;
1157 para.data.bb.value = data;
1158 para.data.bb.msk = mask;
1159 para.data.bb.msk_en = (mask) ? 1 : 0;
1160 para.data.bb.size = 2;
1161 break;
1162 case PHYDM_HALMAC_CMD_BB_W32:
1163 para.cmd = 1; /* BB register */
1164 para.data.bb.offset = offset;
1165 para.data.bb.value = data;
1166 para.data.bb.msk = mask;
1167 para.data.bb.msk_en = (mask) ? 1 : 0;
1168 para.data.bb.size = 4;
1169 break;
1170 case PHYDM_HALMAC_CMD_RF_W:
1171 para.cmd = 2; /* RF register */
1172 para.data.rf.offset = offset;
1173 para.data.rf.value = data;
1174 para.data.rf.msk = mask;
1175 para.data.rf.msk_en = (mask) ? 1 : 0;
1176 if (e_rf_path == RF_PATH_A)
1177 para.data.rf.path = 0;
1178 else if (e_rf_path == RF_PATH_B)
1179 para.data.rf.path = 1;
1180 else if (e_rf_path == RF_PATH_C)
1181 para.data.rf.path = 2;
1182 else if (e_rf_path == RF_PATH_D)
1183 para.data.rf.path = 3;
1184 else
1185 para.data.rf.path = 0;
1186 break;
1187 case PHYDM_HALMAC_CMD_DELAY_US:
1188 para.cmd = 3; /* Delay */
1189 para.data.delay.unit = 0; /* microsecond */
1190 para.data.delay.value = delay_time;
1191 break;
1192 case PHYDM_HALMAC_CMD_DELAY_MS:
1193 para.cmd = 3; /* Delay */
1194 para.data.delay.unit = 1; /* millisecond */
1195 para.data.delay.value = delay_time;
1196 break;
1197 case PHYDM_HALMAC_CMD_END:
1198 para.cmd = 0xFF; /* End command */
1199 break;
1200 default:
1201 return HAL_STATUS_FAILURE;
1202 }
1203
1204 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
1205 return HAL_STATUS_FAILURE;
1206 #endif /*RTW_HALMAC*/
1207 return HAL_STATUS_SUCCESS;
1208 }
1209
1210
1211 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)1212 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
1213 {
1214 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1215 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1216 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1217 struct sta_priv *pstapriv = &adapter->stapriv;
1218 struct sta_info *psta = NULL;
1219 bool is_linked = _FALSE;
1220
1221 if (!rtw_is_hw_init_completed(adapter))
1222 return;
1223
1224 if (rtw_mi_check_status(adapter, MI_ASSOC))
1225 is_linked = _TRUE;
1226
1227 if (is_linked == _FALSE)
1228 return;
1229
1230 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1231 if (psta == NULL)
1232 return;
1233
1234 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
1235
1236 phydm_watchdog_lps_32k(&pHalData->odmpriv);
1237
1238 #ifdef CONFIG_LPS_PG
1239 if (pwrpriv->lps_level == LPS_PG) {
1240 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
1241 RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n",
1242 FUNC_ADPT_ARG(adapter));
1243 }
1244 #endif /* CONFIG_LPS_PG */
1245 }
1246
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)1247 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
1248 {
1249 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1250 struct sta_priv *pstapriv = &adapter->stapriv;
1251 u8 cur_igi = 0;
1252 s8 min_rssi = 0;
1253
1254 if (!rtw_is_hw_init_completed(adapter))
1255 return;
1256
1257 cur_igi = rtw_phydm_get_cur_igi(adapter);
1258 min_rssi = rtw_dm_get_min_rssi(adapter);
1259 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
1260
1261 if (min_rssi <= 0)
1262 return;
1263
1264 if ((cur_igi > min_rssi + 5) ||
1265 (cur_igi < min_rssi - 5)) {
1266 #ifdef CONFIG_LPS
1267 rtw_dm_in_lps_wk_cmd(adapter);
1268 #endif
1269 }
1270 }
1271 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1272
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)1273 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
1274 {
1275 struct ra_sta_info *ra_info;
1276 u8 curr_sgi = _FALSE;
1277 u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
1278
1279 if (!psta)
1280 return;
1281 RTW_PRINT_SEL(sel, "\n");
1282 RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
1283 psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
1284
1285 if (is_client_associated_to_ap(psta->padapter))
1286 RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
1287 rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
1288
1289 ra_info = &psta->cmn.ra_info;
1290 curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
1291 RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
1292 , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
1293 , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
1294 );
1295
1296 if (0) {
1297 RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
1298 , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
1299 , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
1300 );
1301 RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
1302 , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
1303 , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
1304 );
1305 RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
1306 , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
1307 , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
1308 );
1309 RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
1310 , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
1311 , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
1312 );
1313 }
1314
1315 _RTW_PRINT_SEL(sel, "RTW: [TP] ");
1316 tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
1317 rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
1318 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1319
1320 if (tx_tp_mbips)
1321 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1322 else
1323 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
1324
1325 if (rx_tp_mbips)
1326 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1327 else
1328 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
1329
1330 if (bi_tp_mbips)
1331 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1332 else
1333 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1334
1335
1336 _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
1337 tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
1338 rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
1339 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1340 if (tx_tp_mbips)
1341 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1342 else
1343 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
1344
1345 if (rx_tp_mbips)
1346 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1347 else
1348 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
1349
1350 if (bi_tp_mbips)
1351 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1352 else
1353 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1354
1355 #if 0
1356 RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
1357 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
1358 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
1359 #endif
1360 }
1361
dump_sta_info(void * sel,struct sta_info * psta)1362 void dump_sta_info(void *sel, struct sta_info *psta)
1363 {
1364 struct ra_sta_info *ra_info;
1365 u8 curr_tx_sgi = _FALSE;
1366 u8 curr_tx_rate = 0;
1367
1368 if (!psta)
1369 return;
1370
1371 ra_info = &psta->cmn.ra_info;
1372
1373 RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
1374 MAC_ARG(psta->cmn.mac_addr));
1375 RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
1376 RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
1377 RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
1378 RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
1379 RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
1380 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
1381 RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
1382 RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
1383 RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
1384 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
1385 RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
1386 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
1387 RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
1388 RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
1389
1390 curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
1391 curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
1392 RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
1393 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
1394 RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
1395 RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
1396 RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
1397 }
1398
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)1399 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
1400 {
1401 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1402 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1403 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
1404
1405 if (psta == NULL) {
1406 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
1407 rtw_warn_on(1);
1408 return;
1409 }
1410
1411 if (psta->cmn.mac_id >= macid_ctl->num)
1412 return;
1413
1414 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
1415 dump_sta_info(RTW_DBGDUMP, psta);
1416 }
1417
init_phydm_info(_adapter * adapter)1418 static void init_phydm_info(_adapter *adapter)
1419 {
1420 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1421 struct dm_struct *phydm = &(hal_data->odmpriv);
1422
1423 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
1424 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
1425 }
1426
1427 #ifdef CONFIG_CTRL_TXSS_BY_TP
rtw_phydm_trx_cfg(_adapter * adapter,bool tx_1ss)1428 void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
1429 {
1430 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1431 enum bb_path txpath = BB_PATH_AB;
1432 enum bb_path rxpath = BB_PATH_AB;
1433 /*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
1434 enum bb_path txpath_1ss = BB_PATH_A;
1435
1436 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1437 txpath = (tx_1ss) ? BB_PATH_A : txpath;
1438
1439 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
1440 RTW_ERR("%s failed\n", __func__);
1441 }
1442 #endif
1443
rtw_hal_runtime_trx_path_decision(_adapter * adapter)1444 u8 rtw_hal_runtime_trx_path_decision(_adapter *adapter)
1445 {
1446 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1447 enum bb_path txpath;
1448 enum bb_path rxpath;
1449 int i;
1450 u8 rst = _FAIL;
1451
1452 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1453 if (!txpath) {
1454 RTW_ERR("%s tx_path_bmp is empty\n", __func__);
1455 rtw_warn_on(1);
1456 goto exit;
1457 }
1458 if (!rxpath) {
1459 RTW_ERR("%s rx_path_bmp is empty\n", __func__);
1460 rtw_warn_on(1);
1461 goto exit;
1462 }
1463
1464 tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
1465 , GET_HAL_TX_PATH_BMP(adapter));
1466
1467 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1468 {
1469 enum bb_path txpath_1ss;
1470
1471 if (txpath == BB_PATH_AB) {
1472 switch (hal_data->max_tx_cnt) {
1473 case 2:
1474 #ifdef CONFIG_RTW_TX_NPATH_EN
1475 if (adapter->registrypriv.tx_npath == 1)
1476 txpath_1ss = BB_PATH_AB;
1477 else
1478 #endif
1479 #ifdef CONFIG_RTW_PATH_DIV
1480 if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
1481 txpath_1ss = BB_PATH_AUTO;
1482 else
1483 #endif
1484 txpath_1ss = BB_PATH_A;
1485 break;
1486 case 1:
1487 #ifdef CONFIG_RTW_PATH_DIV
1488 if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
1489 txpath = txpath_1ss = BB_PATH_AUTO;
1490 else
1491 #endif
1492 txpath = txpath_1ss = BB_PATH_A;
1493 break;
1494 default:
1495 RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
1496 , hal_data->max_tx_cnt);
1497 rtw_warn_on(1);
1498 goto exit;
1499 }
1500 } else
1501 txpath_1ss = txpath;
1502
1503 if (hal_data->txpath_nss[0] != txpath_1ss) {
1504 hal_data->txpath_nss[0] = txpath_1ss;
1505 if (txpath_1ss == BB_PATH_AUTO)
1506 hal_data->txpath_num_nss[0] = 1;
1507 else {
1508 hal_data->txpath_num_nss[0] = 0;
1509 for (i = 0; i < RF_PATH_MAX; i++) {
1510 if (txpath_1ss & BIT(i))
1511 hal_data->txpath_num_nss[0]++;
1512 }
1513 }
1514 }
1515 }
1516 #elif defined(CONFIG_RTL8814B)
1517 {
1518 /* 8814B is always full-TX */
1519 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1520 }
1521 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1522 {
1523 #ifdef CONFIG_RTW_TX_NPATH_EN
1524 if (adapter->registrypriv.tx_npath == 1)
1525 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1526 #endif
1527 }
1528 #endif
1529
1530 hal_data->txpath = txpath;
1531 hal_data->rxpath = rxpath;
1532 dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
1533 rst = _SUCCESS;
1534
1535 exit:
1536 return rst;
1537 }
1538
1539 /*
1540 * trx_mode init - 8822B / 8822C / 8192F
1541 * 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
1542 * Path-diversity - 8822B / 8822C / 8192F
1543 * PHYDM API - phydm_api_trx_mode
1544 */
rtw_phydm_config_trx_path(_adapter * adapter)1545 static u8 rtw_phydm_config_trx_path(_adapter *adapter)
1546 {
1547 u8 rst = _SUCCESS;
1548
1549 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1550 {
1551 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1552 enum bb_path txpath = hal_data->txpath;
1553 enum bb_path rxpath = hal_data->rxpath;
1554 enum bb_path txpath_1ss = hal_data->txpath_nss[0];
1555
1556 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
1557 RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
1558 , txpath, rxpath, txpath_1ss);
1559 rtw_warn_on(1);
1560 rst = _FAIL;
1561 }
1562 }
1563 #elif defined(CONFIG_RTL8814B)
1564 {
1565 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1566 enum bb_path txpath = hal_data->txpath;
1567 enum bb_path rxpath = hal_data->rxpath;
1568
1569 if (txpath == BB_PATH_ABCD && rxpath == BB_PATH_ABCD)
1570 rst = config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath);
1571 else
1572 rst = config_phydm_trx_mode_ext_8814b(adapter_to_phydm(adapter), txpath,
1573 rxpath,
1574 txpath, txpath, txpath);
1575 if (rst == FALSE) {
1576 RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
1577 , txpath, rxpath);
1578 rtw_warn_on(1);
1579 rst = _FAIL;
1580 }
1581 }
1582 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1583 {
1584 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1585
1586 if (hal_data->txpath_num_nss[0] == 2)
1587 phydm_tx_2path(adapter_to_phydm(adapter));
1588 }
1589 #endif
1590
1591 return rst;
1592 }
1593
rtw_phydm_init(_adapter * adapter)1594 void rtw_phydm_init(_adapter *adapter)
1595 {
1596 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1597 struct dm_struct *phydm = &(hal_data->odmpriv);
1598
1599 rtw_phydm_config_trx_path(adapter);
1600 init_phydm_info(adapter);
1601 hal_data->phydm_init_result = odm_dm_init(phydm);
1602
1603 #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
1604 phydm_pathb_q_matrix_rotate_en(phydm);
1605 #endif
1606 }
1607
rtw_phydm_set_crystal_cap(_adapter * adapter,u8 crystal_cap)1608 bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
1609 {
1610 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1611 struct dm_struct *phydm = &(hal_data->odmpriv);
1612
1613 return phydm_set_crystal_cap_reg(phydm, crystal_cap);
1614 }
1615
1616 #ifdef CONFIG_LPS_PG
1617 /*
1618 static void _lps_pg_state_update(_adapter *adapter)
1619 {
1620 u8 is_in_lpspg = _FALSE;
1621 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1622 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1623 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1624 struct sta_priv *pstapriv = &adapter->stapriv;
1625 struct sta_info *psta = NULL;
1626
1627 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1628 is_in_lpspg = _TRUE;
1629 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1630
1631 if (psta)
1632 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1633 }
1634 */
rtw_phydm_lps_pg_hdl(_adapter * adapter,struct sta_info * sta,bool in_lpspg)1635 void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
1636 {
1637 struct dm_struct *phydm = adapter_to_phydm(adapter);
1638 /*u8 rate_id;*/
1639
1640 if(sta == NULL) {
1641 RTW_ERR("%s sta is null\n", __func__);
1642 rtw_warn_on(1);
1643 return;
1644 }
1645
1646 if (in_lpspg) {
1647 sta->cmn.ra_info.disable_ra = _TRUE;
1648 sta->cmn.ra_info.disable_pt = _TRUE;
1649 /*TODO : DRV fix tx rate*/
1650 /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
1651 } else {
1652 sta->cmn.ra_info.disable_ra = _FALSE;
1653 sta->cmn.ra_info.disable_pt = _FALSE;
1654 }
1655
1656 rtw_phydm_ra_registed(adapter, sta);
1657 }
1658 #endif
1659
1660 /*#define DBG_PHYDM_STATE_CHK*/
1661
1662
_rtw_phydm_rfk_condition_check(_adapter * adapter,u8 is_scaning,u8 ifs_linked)1663 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
1664 {
1665 u8 rfk_allowed = _TRUE;
1666
1667 #ifdef CONFIG_SKIP_RFK_IN_DM
1668 rfk_allowed = _FALSE;
1669 if (0)
1670 RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
1671 return rfk_allowed;
1672 #endif
1673
1674 #ifdef CONFIG_MCC_MODE
1675 /*not in MCC State*/
1676 if (MCC_EN(adapter) &&
1677 rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
1678 rfk_allowed = _FALSE;
1679 if (0)
1680 RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
1681 return rfk_allowed;
1682 }
1683 #endif
1684
1685 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1686
1687 #endif
1688
1689 if (ifs_linked) {
1690 if (is_scaning) {
1691 rfk_allowed = _FALSE;
1692 RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
1693 }
1694 else {
1695 rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
1696 if (rfk_allowed == _FALSE)
1697 RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
1698 }
1699 }
1700
1701 return rfk_allowed;
1702 }
1703
1704 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter,u8 ifs_linked)1705 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
1706 {
1707 u8 iqk_sgt = _FALSE;
1708
1709 #if 0
1710 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1711 if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
1712 rst = _TRUE;
1713 #else
1714 if (ifs_linked)
1715 iqk_sgt = _TRUE;
1716 #endif
1717 return iqk_sgt;
1718 }
1719 #endif
1720
1721 /*check the tx low rate while unlinked to any AP;for pwr tracking */
_rtw_phydm_pwr_tracking_rate_check(_adapter * adapter)1722 static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
1723 {
1724 int i;
1725 _adapter *iface;
1726 u8 if_tx_rate = 0xFF;
1727 u8 tx_rate = 0xFF;
1728 struct mlme_ext_priv *pmlmeext = NULL;
1729 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1730 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1731 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
1732
1733 for (i = 0; i < dvobj->iface_nums; i++) {
1734 iface = dvobj->padapters[i];
1735 pmlmeext = &(iface->mlmeextpriv);
1736 if ((iface) && rtw_is_adapter_up(iface)) {
1737 #ifdef CONFIG_P2P
1738 if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
1739 if_tx_rate = IEEE80211_OFDM_RATE_6MB;
1740 else
1741 #endif
1742 if_tx_rate = pmlmeext->tx_rate;
1743
1744 if (if_tx_rate < tx_rate) {
1745 /*5G limit ofdm rate*/
1746 if (pHalData->current_channel > 14) {
1747 if (!IS_CCK_RATE(if_tx_rate))
1748 tx_rate = if_tx_rate;
1749 } else {
1750 tx_rate = if_tx_rate;
1751 }
1752 }
1753 RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
1754 }
1755 }
1756
1757 /*suggest by RF James,unlinked setting ofdm rate*/
1758 if (tx_rate == 0xFF)
1759 tx_rate = IEEE80211_OFDM_RATE_6MB;
1760
1761 RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
1762 return tx_rate;
1763 }
1764
1765 #ifdef CONFIG_DYNAMIC_SOML
rtw_dyn_soml_byte_update(_adapter * adapter,u8 data_rate,u32 size)1766 void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
1767 {
1768 struct dm_struct *phydm = adapter_to_phydm(adapter);
1769
1770 phydm_soml_bytes_acq(phydm, data_rate, size);
1771 }
1772
rtw_dyn_soml_para_set(_adapter * adapter,u8 train_num,u8 intvl,u8 period,u8 delay)1773 void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
1774 u8 period, u8 delay)
1775 {
1776 struct dm_struct *phydm = adapter_to_phydm(adapter);
1777
1778 phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
1779 RTW_INFO("%s.\n", __func__);
1780 }
1781
rtw_dyn_soml_config(_adapter * adapter)1782 void rtw_dyn_soml_config(_adapter *adapter)
1783 {
1784 RTW_INFO("%s.\n", __func__);
1785
1786 if (adapter->registrypriv.dyn_soml_en == 1) {
1787 /* Must after phydm_adaptive_soml_init() */
1788 rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
1789 RTW_INFO("dyn_soml_en = 1\n");
1790 } else {
1791 if (adapter->registrypriv.dyn_soml_en == 2) {
1792 rtw_dyn_soml_para_set(adapter,
1793 adapter->registrypriv.dyn_soml_train_num,
1794 adapter->registrypriv.dyn_soml_interval,
1795 adapter->registrypriv.dyn_soml_period,
1796 adapter->registrypriv.dyn_soml_delay);
1797 RTW_INFO("dyn_soml_en = 2\n");
1798 RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
1799 adapter->registrypriv.dyn_soml_train_num,
1800 adapter->registrypriv.dyn_soml_interval,
1801 adapter->registrypriv.dyn_soml_period,
1802 adapter->registrypriv.dyn_soml_delay);
1803 } else if (adapter->registrypriv.dyn_soml_en == 0) {
1804 RTW_INFO("dyn_soml_en = 0\n");
1805 } else
1806 RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
1807 adapter->registrypriv.dyn_soml_en);
1808 }
1809 }
1810 #endif
1811
rtw_phydm_set_rrsr(_adapter * adapter,u32 rrsr_value,bool write_rrsr)1812 void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
1813 {
1814 struct dm_struct *phydm = adapter_to_phydm(adapter);
1815 u32 temp_rrsr =0xFFFFFFFF;
1816
1817 if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
1818 temp_rrsr = adapter->registrypriv.set_rrsr_value;
1819 else
1820 temp_rrsr = rrsr_value;
1821
1822 odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
1823 if(write_rrsr)
1824 phydm_rrsr_set_register(phydm, temp_rrsr);
1825 }
rtw_phydm_dyn_rrsr_en(_adapter * adapter,bool en_rrsr)1826 void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
1827 {
1828 struct dm_struct *phydm = adapter_to_phydm(adapter);
1829
1830 phydm_rrsr_en(phydm, en_rrsr);
1831 }
rtw_phydm_read_efuse(_adapter * adapter)1832 void rtw_phydm_read_efuse(_adapter *adapter)
1833 {
1834 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1835 struct dm_struct *phydm = &(hal_data->odmpriv);
1836
1837 /*PHYDM API - thermal trim*/
1838 phydm_get_thermal_trim_offset(phydm);
1839 /*PHYDM API - power trim*/
1840 phydm_get_power_trim_offset(phydm);
1841 }
1842
1843 #ifdef CONFIG_LPS_PWR_TRACKING
rtw_phydm_pwr_tracking_directly(_adapter * adapter)1844 void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
1845 {
1846 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1847 u8 rfk_forbidden = _TRUE;
1848 u8 is_linked = _FALSE;
1849
1850 if (rtw_mi_check_status(adapter, MI_ASSOC))
1851 is_linked = _TRUE;
1852
1853 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
1854 halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1855
1856 odm_txpowertracking_direct_ce(&hal_data->odmpriv);
1857 }
1858 #endif
1859
rtw_phydm_watchdog(_adapter * adapter,bool in_lps)1860 void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
1861 {
1862 u8 bLinked = _FALSE;
1863 u8 bsta_state = _FALSE;
1864 u8 bBtDisabled = _TRUE;
1865 u8 rfk_forbidden = _FALSE;
1866 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1867 u8 segment_iqk = _FALSE;
1868 #endif
1869 u8 tx_unlinked_low_rate = 0xFF;
1870 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1871
1872 if (!rtw_is_hw_init_completed(adapter)) {
1873 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1874 return;
1875 }
1876 if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
1877 pHalData->bScanInProcess = _TRUE;
1878 else
1879 pHalData->bScanInProcess = _FALSE;
1880
1881 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1882 bLinked = _TRUE;
1883 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1884 bsta_state = _TRUE;
1885 }
1886
1887 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1888 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1889
1890 #ifdef CONFIG_BT_COEXIST
1891 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1892 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1893 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1894 #else
1895 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
1896 #endif /* CONFIG_BT_COEXIST */
1897
1898 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
1899 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1900
1901 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1902 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
1903 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1904 #endif
1905 #ifdef DBG_PHYDM_STATE_CHK
1906 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1907 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1908 #endif
1909
1910 if (bLinked == _FALSE) {
1911 tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
1912 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
1913 }
1914
1915 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1916 #ifdef DBG_PHYDM_STATE_CHK
1917 RTW_ERR("Not stay in union band, skip phydm\n");
1918 #endif
1919 goto _exit;
1920 }*/
1921
1922 #ifdef CONFIG_TDMADIG
1923 rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
1924 #endif/*CONFIG_TDMADIG*/
1925
1926 if (in_lps)
1927 phydm_watchdog_lps(&pHalData->odmpriv);
1928 else
1929 phydm_watchdog(&pHalData->odmpriv);
1930
1931 #ifdef CONFIG_RTW_ACS
1932 rtw_acs_update_current_info(adapter);
1933 #endif
1934
1935 return;
1936 }
1937
1938
1939