1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in the
16 * file called LICENSE.
17 *
18 * Contact Information:
19 * wlanfae <wlanfae@realtek.com>
20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
21 * Hsinchu 300, Taiwan.
22 *
23 * Larry Finger <Larry.Finger@lwfinger.net>
24 *
25 *****************************************************************************/
26
27 /*@************************************************************
28 * include files
29 ************************************************************/
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 const u16 phy_rate_table[] = {
35 /*@20M*/
36 1, 2, 5, 11,
37 6, 9, 12, 18, 24, 36, 48, 54,
38 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
39 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
40 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
41 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
42 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
43 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
44 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
45 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
46 };
47
phydm_traffic_load_decision(void * dm_void)48 void phydm_traffic_load_decision(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51 u8 shift = 0;
52
53 /*@---TP & Trafic-load calculation---*/
54
55 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
56 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
57
58 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
59 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
60
61 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
62 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
63 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
64 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
65
66 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
67 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
68 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
69
70 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
71 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
72
73 dm->total_tp = dm->tx_tp + dm->rx_tp;
74
75 /*@[Calculate TX/RX state]*/
76 if (dm->tx_tp > (dm->rx_tp << 1))
77 dm->txrx_state_all = TX_STATE;
78 else if (dm->rx_tp > (dm->tx_tp << 1))
79 dm->txrx_state_all = RX_STATE;
80 else
81 dm->txrx_state_all = BI_DIRECTION_STATE;
82
83 /*@[Traffic load decision]*/
84 dm->pre_traffic_load = dm->traffic_load;
85
86 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
87 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
88 dm->traffic_load = TRAFFIC_HIGH;
89 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
90 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
91 dm->traffic_load = TRAFFIC_MID;
92 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
93 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
94 dm->traffic_load = TRAFFIC_LOW;
95 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
96 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
97 dm->traffic_load = TRAFFIC_ULTRA_LOW;
98 } else {
99 dm->traffic_load = TRAFFIC_NO_TP;
100 }
101
102 /*@[Calculate consecutive idlel time]*/
103 if (dm->traffic_load == 0)
104 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
105 else
106 dm->consecutive_idlel_time = 0;
107
108 #if 0
109 PHYDM_DBG(dm, DBG_COMMON_FLOW,
110 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
111 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
112 dm->last_rx_ok_cnt);
113
114 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
115 dm->rx_tp);
116 #endif
117 }
118
phydm_cck_new_agc_chk(struct dm_struct * dm)119 void phydm_cck_new_agc_chk(struct dm_struct *dm)
120 {
121 u32 new_agc_addr = 0x0;
122
123 dm->cck_new_agc = false;
124 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
125 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
126 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
127 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
128 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
129 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
130 ODM_RTL8721D | ODM_RTL8710C)) {
131 new_agc_addr = R_0xa9c;
132 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
133 ODM_RTL8814B | ODM_RTL8197G)) {
134 new_agc_addr = R_0x1a9c;
135 }
136
137 /*@1: new agc 0: old agc*/
138 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
139 #endif
140 }
141
142 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)143 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
144 {
145 boolean report_type = 0;
146 #if (RTL8192E_SUPPORT)
147 u32 value_824, value_82c;
148 #endif
149
150 #if (RTL8192E_SUPPORT)
151 if (dm->support_ic_type & (ODM_RTL8192E)) {
152 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
153 * should be equal or CCK RSSI report may be incorrect
154 */
155 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
156 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
157
158 if (value_824 != value_82c)
159 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
160 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
161 report_type = (boolean)value_824;
162 }
163 #endif
164
165 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
166 if (dm->support_ic_type &
167 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
168 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
169
170 if (report_type != 1)
171 pr_debug("[Warning] CCK should be 4bit LNA\n");
172 }
173 #endif
174
175 #if (RTL8821C_SUPPORT)
176 if (dm->support_ic_type & ODM_RTL8821C) {
177 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
178 report_type = 1;
179 }
180 #endif
181
182 dm->cck_agc_report_type = report_type;
183
184 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
185 dm->cck_agc_report_type);
186 }
187
phydm_init_cck_setting(struct dm_struct * dm)188 void phydm_init_cck_setting(struct dm_struct *dm)
189 {
190 u32 reg_tmp = 0;
191 u32 mask_tmp = 0;
192
193 phydm_cck_new_agc_chk(dm);
194
195 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
196 return;
197
198 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
199 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
200 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
201
202 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
203
204 phydm_config_cck_rx_antenna_init(dm);
205
206 if (dm->support_ic_type & ODM_RTL8192F)
207 phydm_config_cck_rx_path(dm, BB_PATH_AB);
208 else if (dm->valid_path_set == BB_PATH_A)
209 phydm_config_cck_rx_path(dm, BB_PATH_A);
210 else if (dm->valid_path_set == BB_PATH_B)
211 phydm_config_cck_rx_path(dm, BB_PATH_B);
212
213 phydm_cck_lna_bit_num_chk(dm);
214 phydm_get_cck_rssi_table_from_reg(dm);
215 }
216
217 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)218 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
219 {
220 #if (RTL8821C_SUPPORT)
221 if (dm->support_ic_type & ODM_RTL8821C)
222 phydm_init_hw_info_by_rfe_type_8821c(dm);
223 #endif
224 #if (RTL8197F_SUPPORT)
225 if (dm->support_ic_type & ODM_RTL8197F)
226 phydm_init_hw_info_by_rfe_type_8197f(dm);
227 #endif
228 #if (RTL8197G_SUPPORT)
229 if (dm->support_ic_type & ODM_RTL8197G)
230 phydm_init_hw_info_by_rfe_type_8197g(dm);
231 #endif
232 }
233 #endif
234
phydm_common_info_self_init(struct dm_struct * dm)235 void phydm_common_info_self_init(struct dm_struct *dm)
236 {
237 u32 reg_tmp = 0;
238 u32 mask_tmp = 0;
239
240 dm->run_in_drv_fw = RUN_IN_DRIVER;
241
242 /*@BB IP Generation*/
243 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
244 dm->ic_ip_series = PHYDM_IC_JGR3;
245 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
246 dm->ic_ip_series = PHYDM_IC_AC;
247 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
248 dm->ic_ip_series = PHYDM_IC_N;
249
250 /*@BB phy-status Generation*/
251 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
252 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
253 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
254 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
255 else
256 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
257
258 phydm_init_cck_setting(dm);
259
260 reg_tmp = ODM_REG(BB_RX_PATH, dm);
261 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
262 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
263 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
264 dm->is_net_closed = &dm->BOOLEAN_temp;
265
266 phydm_init_debug_setting(dm);
267 #endif
268 phydm_init_soft_ml_setting(dm);
269
270 dm->phydm_sys_up_time = 0;
271
272 if (dm->support_ic_type & ODM_IC_1SS)
273 dm->num_rf_path = 1;
274 else if (dm->support_ic_type & ODM_IC_2SS)
275 dm->num_rf_path = 2;
276 #if 0
277 /* @RTK do not has IC which is equipped with 3 RF paths,
278 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
279 */
280 else if (dm->support_ic_type & ODM_IC_3SS)
281 dm->num_rf_path = 3;
282 #endif
283 else if (dm->support_ic_type & ODM_IC_4SS)
284 dm->num_rf_path = 4;
285 else
286 dm->num_rf_path = 1;
287
288 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
289
290 dm->tx_rate = 0xFF;
291 dm->rssi_min_by_path = 0xFF;
292
293 dm->number_linked_client = 0;
294 dm->pre_number_linked_client = 0;
295 dm->number_active_client = 0;
296 dm->pre_number_active_client = 0;
297
298 dm->last_tx_ok_cnt = 0;
299 dm->last_rx_ok_cnt = 0;
300 dm->tx_tp = 0;
301 dm->rx_tp = 0;
302 dm->total_tp = 0;
303 dm->traffic_load = TRAFFIC_LOW;
304
305 dm->nbi_set_result = 0;
306 dm->is_init_hw_info_by_rfe = false;
307 dm->pre_dbg_priority = DBGPORT_RELEASE;
308 dm->tp_active_th = 5;
309 dm->disable_phydm_watchdog = 0;
310
311 dm->u8_dummy = 0xf;
312 dm->u16_dummy = 0xffff;
313 dm->u32_dummy = 0xffffffff;
314 #if (RTL8814B_SUPPORT)
315 /*@------------For spur detection Default Mode------------@*/
316 dm->dsde_sel = DET_CSI;
317 dm->csi_wgt = 4;
318 /*@-------------------------------------------------------@*/
319 #endif
320 dm->pre_is_linked = false;
321 dm->is_linked = false;
322 /*dym bw thre and it can config by registry*/
323 if (dm->en_auto_bw_th == 0)
324 dm->en_auto_bw_th = 20;
325
326 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
327 if (!(dm->is_fcs_mode_enable)) {
328 dm->is_fcs_mode_enable = &dm->boolean_dummy;
329 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
330 }
331 #endif
332 /*init IOT table*/
333 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
334 }
335
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)336 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
337 {
338 struct dm_struct *dm = (struct dm_struct *)dm_void;
339 struct phydm_iot_center *iot_table = &dm->iot_table;
340
341 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
342 switch (iot_idx) {
343 case 0x100f0401:
344 iot_table->patch_id_100f0401 = en;
345 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
346 iot_table->patch_id_100f0401);
347 break;
348 case 0x10120200:
349 iot_table->patch_id_10120200 = en;
350 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
351 iot_table->patch_id_10120200);
352 break;
353 case 0x40010700:
354 iot_table->patch_id_40010700 = en;
355 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
356 iot_table->patch_id_40010700);
357 break;
358 case 0x021f0800:
359 iot_table->patch_id_021f0800 = en;
360 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
361 iot_table->patch_id_021f0800);
362 break;
363 default:
364 pr_debug("[%s] warning!\n", __func__);
365 break;
366 }
367 }
368
phydm_cmn_sta_info_update(void * dm_void,u8 macid)369 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
370 {
371 struct dm_struct *dm = (struct dm_struct *)dm_void;
372 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
373 struct ra_sta_info *ra = NULL;
374
375 if (is_sta_active(sta)) {
376 ra = &sta->ra_info;
377 } else {
378 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
379 __func__);
380 return;
381 }
382
383 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
384 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
385
386 /*@[Calculate TX/RX state]*/
387 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
388 ra->txrx_state = TX_STATE;
389 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
390 ra->txrx_state = RX_STATE;
391 else
392 ra->txrx_state = BI_DIRECTION_STATE;
393
394 ra->is_noisy = dm->noisy_decision;
395 }
396
phydm_common_info_self_update(struct dm_struct * dm)397 void phydm_common_info_self_update(struct dm_struct *dm)
398 {
399 u8 sta_cnt = 0, num_active_client = 0;
400 u32 i, one_entry_macid = 0;
401 u32 ma_rx_tp = 0;
402 u32 tp_diff = 0;
403 struct cmn_sta_info *sta;
404 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
405 PADAPTER adapter = (PADAPTER)dm->adapter;
406 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
407
408 sta = dm->phydm_sta_info[0];
409
410 /* STA mode is linked to AP */
411 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
412 dm->bsta_state = true;
413 else
414 dm->bsta_state = false;
415 #endif
416
417 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
418 sta = dm->phydm_sta_info[i];
419 if (is_sta_active(sta)) {
420 sta_cnt++;
421
422 if (sta_cnt == 1)
423 one_entry_macid = i;
424
425 phydm_cmn_sta_info_update(dm, (u8)i);
426 #ifdef PHYDM_BEAMFORMING_SUPPORT
427 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
428 #endif
429
430 ma_rx_tp = sta->rx_moving_average_tp +
431 sta->tx_moving_average_tp;
432
433 PHYDM_DBG(dm, DBG_COMMON_FLOW,
434 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
435
436 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
437 num_active_client++;
438 }
439 }
440
441 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
442 dm->is_linked = (sta_cnt != 0) ? true : false;
443 #endif
444
445 if (sta_cnt == 1) {
446 dm->is_one_entry_only = true;
447 dm->one_entry_macid = one_entry_macid;
448 dm->one_entry_tp = ma_rx_tp;
449
450 dm->tp_active_occur = 0;
451
452 PHYDM_DBG(dm, DBG_COMMON_FLOW,
453 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
454 dm->one_entry_tp, dm->pre_one_entry_tp);
455
456 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
457 dm->pre_one_entry_tp <= 2) {
458 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
459
460 if (tp_diff > dm->tp_active_th)
461 dm->tp_active_occur = 1;
462 }
463 dm->pre_one_entry_tp = dm->one_entry_tp;
464 } else {
465 dm->is_one_entry_only = false;
466 }
467
468 dm->pre_number_linked_client = dm->number_linked_client;
469 dm->pre_number_active_client = dm->number_active_client;
470
471 dm->number_linked_client = sta_cnt;
472 dm->number_active_client = num_active_client;
473
474 /*Traffic load information update*/
475 phydm_traffic_load_decision(dm);
476
477 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
478
479 dm->is_dfs_band = phydm_is_dfs_band(dm);
480 dm->phy_dbg_info.show_phy_sts_cnt = 0;
481
482 /*[Link Status Check]*/
483 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
484 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
485 dm->pre_is_linked = dm->is_linked;
486 }
487
phydm_common_info_self_reset(struct dm_struct * dm)488 void phydm_common_info_self_reset(struct dm_struct *dm)
489 {
490 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
491
492 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
493 dbg_t->num_qry_beacon_pkt = 0;
494
495 dm->rxsc_l = 0xff;
496 dm->rxsc_20 = 0xff;
497 dm->rxsc_40 = 0xff;
498 dm->rxsc_80 = 0xff;
499 }
500
501 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)502 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
503
504 {
505 void *structure = NULL;
506
507 switch (structure_type) {
508 case PHYDM_FALSEALMCNT:
509 structure = &dm->false_alm_cnt;
510 break;
511
512 case PHYDM_CFOTRACK:
513 structure = &dm->dm_cfo_track;
514 break;
515
516 case PHYDM_ADAPTIVITY:
517 structure = &dm->adaptivity;
518 break;
519 #ifdef CONFIG_PHYDM_DFS_MASTER
520 case PHYDM_DFS:
521 structure = &dm->dfs;
522 break;
523 #endif
524 default:
525 break;
526 }
527
528 return structure;
529 }
530
phydm_phy_info_update(struct dm_struct * dm)531 void phydm_phy_info_update(struct dm_struct *dm)
532 {
533 #if (RTL8822B_SUPPORT)
534 if (dm->support_ic_type == ODM_RTL8822B)
535 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
536 #endif
537 }
538
phydm_hw_setting(struct dm_struct * dm)539 void phydm_hw_setting(struct dm_struct *dm)
540 {
541 #if (RTL8821A_SUPPORT)
542 if (dm->support_ic_type & ODM_RTL8821)
543 odm_hw_setting_8821a(dm);
544 #endif
545
546 #if (RTL8814A_SUPPORT)
547 if (dm->support_ic_type & ODM_RTL8814A)
548 phydm_hwsetting_8814a(dm);
549 #endif
550
551 #if (RTL8822B_SUPPORT)
552 if (dm->support_ic_type & ODM_RTL8822B)
553 phydm_hwsetting_8822b(dm);
554 #endif
555
556 #if (RTL8812A_SUPPORT)
557 if (dm->support_ic_type & ODM_RTL8812)
558 phydm_hwsetting_8812a(dm);
559 #endif
560
561 #if (RTL8197F_SUPPORT)
562 if (dm->support_ic_type & ODM_RTL8197F)
563 phydm_hwsetting_8197f(dm);
564 #endif
565
566 #if (RTL8192F_SUPPORT)
567 if (dm->support_ic_type & ODM_RTL8192F)
568 phydm_hwsetting_8192f(dm);
569 #endif
570
571 #if (RTL8822C_SUPPORT)
572 if (dm->support_ic_type & ODM_RTL8822C)
573 phydm_hwsetting_8822c(dm);
574 #endif
575
576 #if (RTL8197G_SUPPORT)
577 if (dm->support_ic_type & ODM_RTL8197G)
578 phydm_hwsetting_8197g(dm);
579 #endif
580
581 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
582 phydm_cck_rx_pathdiv_watchdog(dm);
583 #endif
584 }
585
586 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)587 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
588 {
589 boolean valid = true;
590
591 if (dm->support_ic_type == ODM_RTL8822C) {
592 #if (RTL8822C_SUPPORT)
593 valid = phydm_chk_pkg_set_valid_8822c(dm,
594 RELEASE_VERSION_8822C,
595 RF_RELEASE_VERSION_8822C);
596 #else
597 valid = true; /*@Just for preventing compile warnings*/
598 #endif
599 #if (RTL8812F_SUPPORT)
600 } else if (dm->support_ic_type == ODM_RTL8812F) {
601 valid = phydm_chk_pkg_set_valid_8812f(dm,
602 RELEASE_VERSION_8812F,
603 RF_RELEASE_VERSION_8812F);
604 #endif
605 #if (RTL8197G_SUPPORT)
606 } else if (dm->support_ic_type == ODM_RTL8197G) {
607 valid = phydm_chk_pkg_set_valid_8197g(dm,
608 RELEASE_VERSION_8197G,
609 RF_RELEASE_VERSION_8197G);
610 #endif
611 #if (RTL8812F_SUPPORT)
612 } else if (dm->support_ic_type == ODM_RTL8812F) {
613 valid = phydm_chk_pkg_set_valid_8812f(dm,
614 RELEASE_VERSION_8812F,
615 RF_RELEASE_VERSION_8812F);
616 #endif
617 #if (RTL8198F_SUPPORT)
618 } else if (dm->support_ic_type == ODM_RTL8198F) {
619 valid = phydm_chk_pkg_set_valid_8198f(dm,
620 RELEASE_VERSION_8198F,
621 RF_RELEASE_VERSION_8198F);
622 #endif
623 #if (RTL8814B_SUPPORT)
624 } else if (dm->support_ic_type == ODM_RTL8814B) {
625 valid = phydm_chk_pkg_set_valid_8814b(dm,
626 RELEASE_VERSION_8814B,
627 RF_RELEASE_VERSION_8814B);
628 #endif
629 }
630
631 return valid;
632 }
633
634 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)635 u64 phydm_supportability_init_win(
636 void *dm_void)
637 {
638 struct dm_struct *dm = (struct dm_struct *)dm_void;
639 u64 support_ability = 0;
640
641 switch (dm->support_ic_type) {
642 /*@---------------N Series--------------------*/
643 #if (RTL8188E_SUPPORT)
644 case ODM_RTL8188E:
645 support_ability |=
646 ODM_BB_DIG |
647 ODM_BB_RA_MASK |
648 /*ODM_BB_DYNAMIC_TXPWR |*/
649 ODM_BB_FA_CNT |
650 ODM_BB_RSSI_MONITOR |
651 ODM_BB_CCK_PD |
652 /*ODM_BB_PWR_TRAIN |*/
653 ODM_BB_RATE_ADAPTIVE |
654 ODM_BB_ADAPTIVITY |
655 ODM_BB_CFO_TRACKING |
656 ODM_BB_ENV_MONITOR |
657 ODM_BB_PRIMARY_CCA;
658 break;
659 #endif
660
661 #if (RTL8192E_SUPPORT)
662 case ODM_RTL8192E:
663 support_ability |=
664 ODM_BB_DIG |
665 ODM_BB_RA_MASK |
666 /*ODM_BB_DYNAMIC_TXPWR |*/
667 ODM_BB_FA_CNT |
668 ODM_BB_RSSI_MONITOR |
669 ODM_BB_CCK_PD |
670 /*ODM_BB_PWR_TRAIN |*/
671 ODM_BB_RATE_ADAPTIVE |
672 ODM_BB_ADAPTIVITY |
673 ODM_BB_CFO_TRACKING |
674 ODM_BB_ENV_MONITOR |
675 ODM_BB_PRIMARY_CCA;
676 break;
677 #endif
678
679 #if (RTL8723B_SUPPORT)
680 case ODM_RTL8723B:
681 support_ability |=
682 ODM_BB_DIG |
683 ODM_BB_RA_MASK |
684 /*ODM_BB_DYNAMIC_TXPWR |*/
685 ODM_BB_FA_CNT |
686 ODM_BB_RSSI_MONITOR |
687 ODM_BB_CCK_PD |
688 /*ODM_BB_PWR_TRAIN |*/
689 ODM_BB_RATE_ADAPTIVE |
690 ODM_BB_ADAPTIVITY |
691 ODM_BB_CFO_TRACKING |
692 ODM_BB_ENV_MONITOR |
693 ODM_BB_PRIMARY_CCA;
694 break;
695 #endif
696
697 #if (RTL8703B_SUPPORT)
698 case ODM_RTL8703B:
699 support_ability |=
700 ODM_BB_DIG |
701 ODM_BB_RA_MASK |
702 /*ODM_BB_DYNAMIC_TXPWR |*/
703 ODM_BB_FA_CNT |
704 ODM_BB_RSSI_MONITOR |
705 ODM_BB_CCK_PD |
706 /*ODM_BB_PWR_TRAIN |*/
707 ODM_BB_RATE_ADAPTIVE |
708 ODM_BB_ADAPTIVITY |
709 ODM_BB_CFO_TRACKING |
710 ODM_BB_ENV_MONITOR;
711 break;
712 #endif
713
714 #if (RTL8723D_SUPPORT)
715 case ODM_RTL8723D:
716 support_ability |=
717 ODM_BB_DIG |
718 ODM_BB_RA_MASK |
719 /*ODM_BB_DYNAMIC_TXPWR |*/
720 ODM_BB_FA_CNT |
721 ODM_BB_RSSI_MONITOR |
722 ODM_BB_CCK_PD |
723 ODM_BB_PWR_TRAIN |
724 ODM_BB_RATE_ADAPTIVE |
725 ODM_BB_ADAPTIVITY |
726 ODM_BB_CFO_TRACKING |
727 ODM_BB_ENV_MONITOR;
728 break;
729 #endif
730
731 #if (RTL8710B_SUPPORT)
732 case ODM_RTL8710B:
733 support_ability |=
734 ODM_BB_DIG |
735 ODM_BB_RA_MASK |
736 /*ODM_BB_DYNAMIC_TXPWR |*/
737 ODM_BB_FA_CNT |
738 ODM_BB_RSSI_MONITOR |
739 ODM_BB_CCK_PD |
740 ODM_BB_PWR_TRAIN |
741 ODM_BB_RATE_ADAPTIVE |
742 ODM_BB_ADAPTIVITY |
743 ODM_BB_CFO_TRACKING |
744 ODM_BB_ENV_MONITOR;
745 break;
746 #endif
747
748 #if (RTL8188F_SUPPORT)
749 case ODM_RTL8188F:
750 support_ability |=
751 ODM_BB_DIG |
752 ODM_BB_RA_MASK |
753 /*ODM_BB_DYNAMIC_TXPWR |*/
754 ODM_BB_FA_CNT |
755 ODM_BB_RSSI_MONITOR |
756 ODM_BB_CCK_PD |
757 /*ODM_BB_PWR_TRAIN |*/
758 ODM_BB_RATE_ADAPTIVE |
759 ODM_BB_ADAPTIVITY |
760 ODM_BB_CFO_TRACKING |
761 ODM_BB_ENV_MONITOR;
762 break;
763 #endif
764
765 #if (RTL8192F_SUPPORT)
766 case ODM_RTL8192F:
767 support_ability |=
768 ODM_BB_DIG |
769 ODM_BB_RA_MASK |
770 ODM_BB_FA_CNT |
771 ODM_BB_RSSI_MONITOR |
772 ODM_BB_CCK_PD |
773 ODM_BB_PWR_TRAIN |
774 ODM_BB_RATE_ADAPTIVE |
775 /*ODM_BB_PATH_DIV |*/
776 ODM_BB_ADAPTIVITY |
777 ODM_BB_CFO_TRACKING |
778 ODM_BB_ADAPTIVE_SOML |
779 ODM_BB_ENV_MONITOR;
780 /*ODM_BB_LNA_SAT_CHK |*/
781 /*ODM_BB_PRIMARY_CCA*/
782
783 break;
784 #endif
785
786 /*@---------------AC Series-------------------*/
787
788 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
789 case ODM_RTL8812:
790 case ODM_RTL8821:
791 support_ability |=
792 ODM_BB_DIG |
793 ODM_BB_RA_MASK |
794 ODM_BB_DYNAMIC_TXPWR |
795 ODM_BB_FA_CNT |
796 ODM_BB_RSSI_MONITOR |
797 ODM_BB_CCK_PD |
798 /*ODM_BB_PWR_TRAIN |*/
799 ODM_BB_RATE_ADAPTIVE |
800 ODM_BB_ADAPTIVITY |
801 ODM_BB_CFO_TRACKING |
802 ODM_BB_ENV_MONITOR;
803 break;
804 #endif
805
806 #if (RTL8814A_SUPPORT)
807 case ODM_RTL8814A:
808 support_ability |=
809 ODM_BB_DIG |
810 ODM_BB_RA_MASK |
811 ODM_BB_DYNAMIC_TXPWR |
812 ODM_BB_FA_CNT |
813 ODM_BB_RSSI_MONITOR |
814 ODM_BB_CCK_PD |
815 /*ODM_BB_PWR_TRAIN |*/
816 ODM_BB_RATE_ADAPTIVE |
817 ODM_BB_ADAPTIVITY |
818 ODM_BB_CFO_TRACKING |
819 ODM_BB_ENV_MONITOR;
820 break;
821 #endif
822
823 #if (RTL8822B_SUPPORT)
824 case ODM_RTL8822B:
825 support_ability |=
826 ODM_BB_DIG |
827 ODM_BB_RA_MASK |
828 /*ODM_BB_DYNAMIC_TXPWR |*/
829 ODM_BB_FA_CNT |
830 ODM_BB_RSSI_MONITOR |
831 ODM_BB_CCK_PD |
832 /*ODM_BB_PWR_TRAIN |*/
833 /*ODM_BB_ADAPTIVE_SOML |*/
834 ODM_BB_RATE_ADAPTIVE |
835 /*ODM_BB_PATH_DIV |*/
836 ODM_BB_ADAPTIVITY |
837 ODM_BB_CFO_TRACKING |
838 ODM_BB_ENV_MONITOR;
839 break;
840 #endif
841
842 #if (RTL8821C_SUPPORT)
843 case ODM_RTL8821C:
844 support_ability |=
845 ODM_BB_DIG |
846 ODM_BB_RA_MASK |
847 /*ODM_BB_DYNAMIC_TXPWR |*/
848 ODM_BB_FA_CNT |
849 ODM_BB_RSSI_MONITOR |
850 ODM_BB_CCK_PD |
851 /*ODM_BB_PWR_TRAIN |*/
852 ODM_BB_RATE_ADAPTIVE |
853 ODM_BB_ADAPTIVITY |
854 ODM_BB_CFO_TRACKING |
855 ODM_BB_ENV_MONITOR;
856 break;
857 #endif
858
859 /*@---------------JGR3 Series-------------------*/
860
861 #if (RTL8822C_SUPPORT)
862 case ODM_RTL8822C:
863 support_ability |=
864 ODM_BB_DIG |
865 ODM_BB_RA_MASK |
866 ODM_BB_DYNAMIC_TXPWR |
867 ODM_BB_FA_CNT |
868 ODM_BB_RSSI_MONITOR |
869 ODM_BB_CCK_PD |
870 ODM_BB_RATE_ADAPTIVE |
871 ODM_BB_PATH_DIV |
872 ODM_BB_ADAPTIVITY |
873 ODM_BB_CFO_TRACKING |
874 ODM_BB_ENV_MONITOR;
875 break;
876 #endif
877
878 #if (RTL8814B_SUPPORT)
879 case ODM_RTL8814B:
880 support_ability |=
881 ODM_BB_DIG |
882 ODM_BB_RA_MASK |
883 /*ODM_BB_DYNAMIC_TXPWR |*/
884 ODM_BB_FA_CNT |
885 ODM_BB_RSSI_MONITOR |
886 ODM_BB_CCK_PD |
887 /*ODM_BB_PWR_TRAIN |*/
888 ODM_BB_RATE_ADAPTIVE |
889 ODM_BB_ADAPTIVITY |
890 ODM_BB_CFO_TRACKING;
891 /*ODM_BB_ENV_MONITOR;*/
892 break;
893 #endif
894
895 default:
896 support_ability |=
897 ODM_BB_DIG |
898 ODM_BB_RA_MASK |
899 /*ODM_BB_DYNAMIC_TXPWR |*/
900 ODM_BB_FA_CNT |
901 ODM_BB_RSSI_MONITOR |
902 ODM_BB_CCK_PD |
903 /*ODM_BB_PWR_TRAIN |*/
904 ODM_BB_RATE_ADAPTIVE |
905 ODM_BB_ADAPTIVITY |
906 ODM_BB_CFO_TRACKING |
907 ODM_BB_ENV_MONITOR;
908
909 pr_debug("[Warning] Supportability Init Warning !!!\n");
910 break;
911 }
912
913 return support_ability;
914 }
915 #endif
916
917 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)918 u64 phydm_supportability_init_ce(void *dm_void)
919 {
920 struct dm_struct *dm = (struct dm_struct *)dm_void;
921 u64 support_ability = 0;
922
923 switch (dm->support_ic_type) {
924 /*@---------------N Series--------------------*/
925 #if (RTL8188E_SUPPORT)
926 case ODM_RTL8188E:
927 support_ability |=
928 ODM_BB_DIG |
929 ODM_BB_RA_MASK |
930 /*@ODM_BB_DYNAMIC_TXPWR |*/
931 ODM_BB_FA_CNT |
932 ODM_BB_RSSI_MONITOR |
933 ODM_BB_CCK_PD |
934 /*@ODM_BB_PWR_TRAIN |*/
935 ODM_BB_RATE_ADAPTIVE |
936 ODM_BB_ADAPTIVITY |
937 ODM_BB_CFO_TRACKING |
938 ODM_BB_ENV_MONITOR |
939 ODM_BB_PRIMARY_CCA;
940 break;
941 #endif
942
943 #if (RTL8192E_SUPPORT)
944 case ODM_RTL8192E:
945 support_ability |=
946 ODM_BB_DIG |
947 ODM_BB_RA_MASK |
948 /*@ODM_BB_DYNAMIC_TXPWR |*/
949 ODM_BB_FA_CNT |
950 ODM_BB_RSSI_MONITOR |
951 ODM_BB_CCK_PD |
952 /*@ODM_BB_PWR_TRAIN |*/
953 ODM_BB_RATE_ADAPTIVE |
954 ODM_BB_ADAPTIVITY |
955 ODM_BB_CFO_TRACKING |
956 ODM_BB_ENV_MONITOR |
957 ODM_BB_PRIMARY_CCA;
958 break;
959 #endif
960
961 #if (RTL8723B_SUPPORT)
962 case ODM_RTL8723B:
963 support_ability |=
964 ODM_BB_DIG |
965 ODM_BB_RA_MASK |
966 /*@ODM_BB_DYNAMIC_TXPWR |*/
967 ODM_BB_FA_CNT |
968 ODM_BB_RSSI_MONITOR |
969 ODM_BB_CCK_PD |
970 /*@ODM_BB_PWR_TRAIN |*/
971 ODM_BB_RATE_ADAPTIVE |
972 ODM_BB_ADAPTIVITY |
973 ODM_BB_CFO_TRACKING |
974 ODM_BB_ENV_MONITOR |
975 ODM_BB_PRIMARY_CCA;
976 break;
977 #endif
978
979 #if (RTL8703B_SUPPORT)
980 case ODM_RTL8703B:
981 support_ability |=
982 ODM_BB_DIG |
983 ODM_BB_RA_MASK |
984 /*@ODM_BB_DYNAMIC_TXPWR |*/
985 ODM_BB_FA_CNT |
986 ODM_BB_RSSI_MONITOR |
987 ODM_BB_CCK_PD |
988 /*@ODM_BB_PWR_TRAIN |*/
989 ODM_BB_RATE_ADAPTIVE |
990 ODM_BB_ADAPTIVITY |
991 ODM_BB_CFO_TRACKING |
992 ODM_BB_ENV_MONITOR;
993 break;
994 #endif
995
996 #if (RTL8723D_SUPPORT)
997 case ODM_RTL8723D:
998 support_ability |=
999 ODM_BB_DIG |
1000 ODM_BB_RA_MASK |
1001 /*@ODM_BB_DYNAMIC_TXPWR |*/
1002 ODM_BB_FA_CNT |
1003 ODM_BB_RSSI_MONITOR |
1004 ODM_BB_CCK_PD |
1005 ODM_BB_PWR_TRAIN |
1006 ODM_BB_RATE_ADAPTIVE |
1007 ODM_BB_ADAPTIVITY |
1008 ODM_BB_CFO_TRACKING |
1009 ODM_BB_ENV_MONITOR;
1010 break;
1011 #endif
1012
1013 #if (RTL8710B_SUPPORT)
1014 case ODM_RTL8710B:
1015 support_ability |=
1016 ODM_BB_DIG |
1017 ODM_BB_RA_MASK |
1018 /*@ODM_BB_DYNAMIC_TXPWR |*/
1019 ODM_BB_FA_CNT |
1020 ODM_BB_RSSI_MONITOR |
1021 ODM_BB_CCK_PD |
1022 /*@ODM_BB_PWR_TRAIN |*/
1023 ODM_BB_RATE_ADAPTIVE |
1024 ODM_BB_ADAPTIVITY |
1025 ODM_BB_CFO_TRACKING |
1026 ODM_BB_ENV_MONITOR;
1027 break;
1028 #endif
1029
1030 #if (RTL8188F_SUPPORT)
1031 case ODM_RTL8188F:
1032 support_ability |=
1033 ODM_BB_DIG |
1034 ODM_BB_RA_MASK |
1035 /*@ODM_BB_DYNAMIC_TXPWR |*/
1036 ODM_BB_FA_CNT |
1037 ODM_BB_RSSI_MONITOR |
1038 ODM_BB_CCK_PD |
1039 /*@ODM_BB_PWR_TRAIN |*/
1040 ODM_BB_RATE_ADAPTIVE |
1041 ODM_BB_ADAPTIVITY |
1042 ODM_BB_CFO_TRACKING |
1043 ODM_BB_ENV_MONITOR;
1044 break;
1045 #endif
1046
1047 #if (RTL8192F_SUPPORT)
1048 case ODM_RTL8192F:
1049 support_ability |=
1050 ODM_BB_DIG |
1051 ODM_BB_RA_MASK |
1052 ODM_BB_FA_CNT |
1053 ODM_BB_RSSI_MONITOR |
1054 ODM_BB_CCK_PD |
1055 ODM_BB_PWR_TRAIN |
1056 ODM_BB_RATE_ADAPTIVE |
1057 /*ODM_BB_PATH_DIV |*/
1058 ODM_BB_ADAPTIVITY |
1059 ODM_BB_CFO_TRACKING |
1060 /*@ODM_BB_ADAPTIVE_SOML |*/
1061 ODM_BB_ENV_MONITOR;
1062 /*@ODM_BB_LNA_SAT_CHK |*/
1063 /*@ODM_BB_PRIMARY_CCA*/
1064 break;
1065 #endif
1066 /*@---------------AC Series-------------------*/
1067
1068 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1069 case ODM_RTL8812:
1070 case ODM_RTL8821:
1071 support_ability |=
1072 ODM_BB_DIG |
1073 ODM_BB_RA_MASK |
1074 /*@ODM_BB_DYNAMIC_TXPWR |*/
1075 ODM_BB_FA_CNT |
1076 ODM_BB_RSSI_MONITOR |
1077 ODM_BB_CCK_PD |
1078 /*@ODM_BB_PWR_TRAIN |*/
1079 ODM_BB_RATE_ADAPTIVE |
1080 ODM_BB_ADAPTIVITY |
1081 ODM_BB_CFO_TRACKING |
1082 ODM_BB_ENV_MONITOR;
1083 break;
1084 #endif
1085
1086 #if (RTL8814A_SUPPORT)
1087 case ODM_RTL8814A:
1088 support_ability |=
1089 ODM_BB_DIG |
1090 ODM_BB_RA_MASK |
1091 /*@ODM_BB_DYNAMIC_TXPWR |*/
1092 ODM_BB_FA_CNT |
1093 ODM_BB_RSSI_MONITOR |
1094 ODM_BB_CCK_PD |
1095 /*@ODM_BB_PWR_TRAIN |*/
1096 ODM_BB_RATE_ADAPTIVE |
1097 ODM_BB_ADAPTIVITY |
1098 ODM_BB_CFO_TRACKING |
1099 ODM_BB_ENV_MONITOR;
1100 break;
1101 #endif
1102
1103 #if (RTL8822B_SUPPORT)
1104 case ODM_RTL8822B:
1105 support_ability |=
1106 ODM_BB_DIG |
1107 ODM_BB_RA_MASK |
1108 ODM_BB_DYNAMIC_TXPWR |
1109 ODM_BB_FA_CNT |
1110 ODM_BB_RSSI_MONITOR |
1111 ODM_BB_CCK_PD |
1112 /*@ODM_BB_PWR_TRAIN |*/
1113 ODM_BB_RATE_ADAPTIVE |
1114 /*ODM_BB_PATH_DIV |*/
1115 ODM_BB_ADAPTIVITY |
1116 ODM_BB_CFO_TRACKING |
1117 ODM_BB_ENV_MONITOR;
1118 break;
1119 #endif
1120
1121 #if (RTL8821C_SUPPORT)
1122 case ODM_RTL8821C:
1123 support_ability |=
1124 ODM_BB_DIG |
1125 ODM_BB_RA_MASK |
1126 /*@ODM_BB_DYNAMIC_TXPWR |*/
1127 ODM_BB_FA_CNT |
1128 ODM_BB_RSSI_MONITOR |
1129 ODM_BB_CCK_PD |
1130 /*@ODM_BB_PWR_TRAIN |*/
1131 ODM_BB_RATE_ADAPTIVE |
1132 ODM_BB_ADAPTIVITY |
1133 ODM_BB_CFO_TRACKING |
1134 ODM_BB_ENV_MONITOR;
1135 break;
1136 #endif
1137
1138 /*@---------------JGR3 Series-------------------*/
1139
1140 #if (RTL8822C_SUPPORT)
1141 case ODM_RTL8822C:
1142 support_ability |=
1143 ODM_BB_DIG |
1144 ODM_BB_RA_MASK |
1145 ODM_BB_DYNAMIC_TXPWR |
1146 ODM_BB_FA_CNT |
1147 ODM_BB_RSSI_MONITOR |
1148 ODM_BB_CCK_PD |
1149 ODM_BB_RATE_ADAPTIVE |
1150 /* ODM_BB_PATH_DIV | */
1151 ODM_BB_ADAPTIVITY |
1152 ODM_BB_CFO_TRACKING |
1153 ODM_BB_ENV_MONITOR;
1154 break;
1155 #endif
1156
1157 #if (RTL8814B_SUPPORT)
1158 case ODM_RTL8814B:
1159 support_ability |=
1160 ODM_BB_DIG |
1161 ODM_BB_RA_MASK |
1162 /*@ODM_BB_DYNAMIC_TXPWR |*/
1163 ODM_BB_FA_CNT |
1164 ODM_BB_RSSI_MONITOR |
1165 ODM_BB_CCK_PD |
1166 /*@ODM_BB_PWR_TRAIN |*/
1167 /*ODM_BB_RATE_ADAPTIVE |*/
1168 ODM_BB_ADAPTIVITY |
1169 ODM_BB_CFO_TRACKING;
1170 /*ODM_BB_ENV_MONITOR;*/
1171 break;
1172 #endif
1173
1174 default:
1175 support_ability |=
1176 ODM_BB_DIG |
1177 ODM_BB_RA_MASK |
1178 /*@ODM_BB_DYNAMIC_TXPWR |*/
1179 ODM_BB_FA_CNT |
1180 ODM_BB_RSSI_MONITOR |
1181 ODM_BB_CCK_PD |
1182 /*@ODM_BB_PWR_TRAIN |*/
1183 ODM_BB_RATE_ADAPTIVE |
1184 ODM_BB_ADAPTIVITY |
1185 ODM_BB_CFO_TRACKING |
1186 ODM_BB_ENV_MONITOR;
1187
1188 pr_debug("[Warning] Supportability Init Warning !!!\n");
1189 break;
1190 }
1191
1192 return support_ability;
1193 }
1194 #endif
1195
1196 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1197 u64 phydm_supportability_init_ap(
1198 void *dm_void)
1199 {
1200 struct dm_struct *dm = (struct dm_struct *)dm_void;
1201 u64 support_ability = 0;
1202
1203 switch (dm->support_ic_type) {
1204 /*@---------------N Series--------------------*/
1205 #if (RTL8188E_SUPPORT)
1206 case ODM_RTL8188E:
1207 support_ability |=
1208 ODM_BB_DIG |
1209 ODM_BB_RA_MASK |
1210 ODM_BB_FA_CNT |
1211 ODM_BB_RSSI_MONITOR |
1212 ODM_BB_CCK_PD |
1213 /*ODM_BB_PWR_TRAIN |*/
1214 ODM_BB_RATE_ADAPTIVE |
1215 ODM_BB_ADAPTIVITY |
1216 ODM_BB_CFO_TRACKING |
1217 ODM_BB_ENV_MONITOR |
1218 ODM_BB_PRIMARY_CCA;
1219 break;
1220 #endif
1221
1222 #if (RTL8192E_SUPPORT)
1223 case ODM_RTL8192E:
1224 support_ability |=
1225 ODM_BB_DIG |
1226 ODM_BB_RA_MASK |
1227 ODM_BB_FA_CNT |
1228 ODM_BB_RSSI_MONITOR |
1229 ODM_BB_CCK_PD |
1230 /*ODM_BB_PWR_TRAIN |*/
1231 ODM_BB_RATE_ADAPTIVE |
1232 ODM_BB_ADAPTIVITY |
1233 ODM_BB_CFO_TRACKING |
1234 ODM_BB_ENV_MONITOR |
1235 ODM_BB_PRIMARY_CCA;
1236 break;
1237 #endif
1238
1239 #if (RTL8723B_SUPPORT)
1240 case ODM_RTL8723B:
1241 support_ability |=
1242 ODM_BB_DIG |
1243 ODM_BB_RA_MASK |
1244 ODM_BB_FA_CNT |
1245 ODM_BB_RSSI_MONITOR |
1246 ODM_BB_CCK_PD |
1247 /*ODM_BB_PWR_TRAIN |*/
1248 ODM_BB_RATE_ADAPTIVE |
1249 ODM_BB_ADAPTIVITY |
1250 ODM_BB_CFO_TRACKING |
1251 ODM_BB_ENV_MONITOR;
1252 break;
1253 #endif
1254
1255 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1256 case ODM_RTL8198F:
1257 support_ability |=
1258 ODM_BB_DIG |
1259 ODM_BB_RA_MASK |
1260 ODM_BB_FA_CNT |
1261 ODM_BB_RSSI_MONITOR |
1262 ODM_BB_CCK_PD |
1263 /*ODM_BB_PWR_TRAIN |*/
1264 /*ODM_BB_RATE_ADAPTIVE |*/
1265 ODM_BB_ADAPTIVITY |
1266 ODM_BB_CFO_TRACKING;
1267 /*ODM_BB_ADAPTIVE_SOML |*/
1268 /*ODM_BB_ENV_MONITOR |*/
1269 /*ODM_BB_LNA_SAT_CHK |*/
1270 /*ODM_BB_PRIMARY_CCA;*/
1271 break;
1272 case ODM_RTL8197F:
1273 support_ability |=
1274 ODM_BB_DIG |
1275 ODM_BB_RA_MASK |
1276 ODM_BB_FA_CNT |
1277 ODM_BB_RSSI_MONITOR |
1278 ODM_BB_CCK_PD |
1279 /*ODM_BB_PWR_TRAIN |*/
1280 ODM_BB_RATE_ADAPTIVE |
1281 ODM_BB_ADAPTIVITY |
1282 ODM_BB_CFO_TRACKING |
1283 ODM_BB_ADAPTIVE_SOML |
1284 ODM_BB_ENV_MONITOR |
1285 ODM_BB_LNA_SAT_CHK |
1286 ODM_BB_PRIMARY_CCA;
1287 break;
1288 #endif
1289
1290 #if (RTL8192F_SUPPORT)
1291 case ODM_RTL8192F:
1292 support_ability |=
1293 ODM_BB_DIG |
1294 ODM_BB_RA_MASK |
1295 ODM_BB_FA_CNT |
1296 ODM_BB_RSSI_MONITOR |
1297 ODM_BB_CCK_PD |
1298 /*ODM_BB_PWR_TRAIN |*/
1299 ODM_BB_RATE_ADAPTIVE |
1300 ODM_BB_ADAPTIVITY |
1301 /*ODM_BB_CFO_TRACKING |*/
1302 ODM_BB_ADAPTIVE_SOML |
1303 /*ODM_BB_PATH_DIV |*/
1304 ODM_BB_ENV_MONITOR |
1305 /*ODM_BB_LNA_SAT_CHK |*/
1306 /*ODM_BB_PRIMARY_CCA |*/
1307 0;
1308 break;
1309 #endif
1310
1311 /*@---------------AC Series-------------------*/
1312
1313 #if (RTL8881A_SUPPORT)
1314 case ODM_RTL8881A:
1315 support_ability |=
1316 ODM_BB_DIG |
1317 ODM_BB_RA_MASK |
1318 ODM_BB_FA_CNT |
1319 ODM_BB_RSSI_MONITOR |
1320 ODM_BB_CCK_PD |
1321 /*ODM_BB_PWR_TRAIN |*/
1322 ODM_BB_RATE_ADAPTIVE |
1323 ODM_BB_ADAPTIVITY |
1324 ODM_BB_CFO_TRACKING |
1325 ODM_BB_ENV_MONITOR;
1326 break;
1327 #endif
1328
1329 #if (RTL8814A_SUPPORT)
1330 case ODM_RTL8814A:
1331 support_ability |=
1332 ODM_BB_DIG |
1333 ODM_BB_RA_MASK |
1334 ODM_BB_FA_CNT |
1335 ODM_BB_RSSI_MONITOR |
1336 ODM_BB_CCK_PD |
1337 /*ODM_BB_PWR_TRAIN |*/
1338 ODM_BB_RATE_ADAPTIVE |
1339 ODM_BB_ADAPTIVITY |
1340 ODM_BB_CFO_TRACKING |
1341 ODM_BB_ENV_MONITOR;
1342 break;
1343 #endif
1344
1345 #if (RTL8822B_SUPPORT)
1346 case ODM_RTL8822B:
1347 support_ability |=
1348 ODM_BB_DIG |
1349 ODM_BB_RA_MASK |
1350 ODM_BB_FA_CNT |
1351 ODM_BB_RSSI_MONITOR |
1352 ODM_BB_CCK_PD |
1353 /*ODM_BB_PWR_TRAIN |*/
1354 /*ODM_BB_ADAPTIVE_SOML |*/
1355 ODM_BB_RATE_ADAPTIVE |
1356 ODM_BB_ADAPTIVITY |
1357 ODM_BB_CFO_TRACKING |
1358 ODM_BB_ENV_MONITOR;
1359 break;
1360 #endif
1361
1362 #if (RTL8821C_SUPPORT)
1363 case ODM_RTL8821C:
1364 support_ability |=
1365 ODM_BB_DIG |
1366 ODM_BB_RA_MASK |
1367 ODM_BB_FA_CNT |
1368 ODM_BB_RSSI_MONITOR |
1369 ODM_BB_CCK_PD |
1370 /*ODM_BB_PWR_TRAIN |*/
1371 ODM_BB_RATE_ADAPTIVE |
1372 ODM_BB_ADAPTIVITY |
1373 ODM_BB_CFO_TRACKING |
1374 ODM_BB_ENV_MONITOR;
1375
1376 break;
1377 #endif
1378
1379 /*@---------------JGR3 Series-------------------*/
1380
1381 #if (RTL8814B_SUPPORT)
1382 case ODM_RTL8814B:
1383 support_ability |=
1384 ODM_BB_DIG |
1385 ODM_BB_RA_MASK |
1386 ODM_BB_FA_CNT |
1387 ODM_BB_RSSI_MONITOR |
1388 ODM_BB_CCK_PD |
1389 /*ODM_BB_PWR_TRAIN |*/
1390 /*ODM_BB_RATE_ADAPTIVE |*/
1391 ODM_BB_ADAPTIVITY |
1392 ODM_BB_CFO_TRACKING |
1393 ODM_BB_ENV_MONITOR;
1394 break;
1395 #endif
1396
1397 #if (RTL8197G_SUPPORT)
1398 case ODM_RTL8197G:
1399 support_ability |=
1400 ODM_BB_DIG |
1401 ODM_BB_RA_MASK |
1402 ODM_BB_FA_CNT |
1403 ODM_BB_RSSI_MONITOR |
1404 ODM_BB_CCK_PD |
1405 /*ODM_BB_PWR_TRAIN |*/
1406 ODM_BB_RATE_ADAPTIVE |
1407 ODM_BB_ADAPTIVITY |
1408 ODM_BB_CFO_TRACKING |
1409 ODM_BB_ENV_MONITOR;
1410 break;
1411 #endif
1412
1413 #if (RTL8812F_SUPPORT)
1414 case ODM_RTL8812F:
1415 support_ability |=
1416 ODM_BB_DIG |
1417 ODM_BB_RA_MASK |
1418 ODM_BB_DYNAMIC_TXPWR |
1419 ODM_BB_FA_CNT |
1420 ODM_BB_RSSI_MONITOR |
1421 /*ODM_BB_CCK_PD |*/
1422 /*ODM_BB_PWR_TRAIN |*/
1423 ODM_BB_RATE_ADAPTIVE |
1424 ODM_BB_ADAPTIVITY |
1425 ODM_BB_CFO_TRACKING |
1426 ODM_BB_ENV_MONITOR;
1427 break;
1428 #endif
1429
1430 default:
1431 support_ability |=
1432 ODM_BB_DIG |
1433 ODM_BB_RA_MASK |
1434 ODM_BB_FA_CNT |
1435 ODM_BB_RSSI_MONITOR |
1436 ODM_BB_CCK_PD |
1437 /*ODM_BB_PWR_TRAIN |*/
1438 ODM_BB_RATE_ADAPTIVE |
1439 ODM_BB_ADAPTIVITY |
1440 ODM_BB_CFO_TRACKING |
1441 ODM_BB_ENV_MONITOR;
1442
1443 pr_debug("[Warning] Supportability Init Warning !!!\n");
1444 break;
1445 }
1446
1447 return support_ability;
1448 }
1449 #endif
1450
1451 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1452 u64 phydm_supportability_init_iot(
1453 void *dm_void)
1454 {
1455 struct dm_struct *dm = (struct dm_struct *)dm_void;
1456 u64 support_ability = 0;
1457
1458 switch (dm->support_ic_type) {
1459 #if (RTL8710B_SUPPORT)
1460 case ODM_RTL8710B:
1461 support_ability |=
1462 ODM_BB_DIG |
1463 ODM_BB_RA_MASK |
1464 /*ODM_BB_DYNAMIC_TXPWR |*/
1465 ODM_BB_FA_CNT |
1466 ODM_BB_RSSI_MONITOR |
1467 ODM_BB_CCK_PD |
1468 /*ODM_BB_PWR_TRAIN |*/
1469 ODM_BB_RATE_ADAPTIVE |
1470 ODM_BB_CFO_TRACKING |
1471 ODM_BB_ENV_MONITOR;
1472 break;
1473 #endif
1474
1475 #if (RTL8195A_SUPPORT)
1476 case ODM_RTL8195A:
1477 support_ability |=
1478 ODM_BB_DIG |
1479 ODM_BB_RA_MASK |
1480 /*ODM_BB_DYNAMIC_TXPWR |*/
1481 ODM_BB_FA_CNT |
1482 ODM_BB_RSSI_MONITOR |
1483 ODM_BB_CCK_PD |
1484 /*ODM_BB_PWR_TRAIN |*/
1485 ODM_BB_RATE_ADAPTIVE |
1486 ODM_BB_CFO_TRACKING |
1487 ODM_BB_ENV_MONITOR;
1488 break;
1489 #endif
1490
1491 #if (RTL8195B_SUPPORT)
1492 case ODM_RTL8195B:
1493 support_ability |=
1494 ODM_BB_DIG |
1495 ODM_BB_RA_MASK |
1496 /*ODM_BB_DYNAMIC_TXPWR |*/
1497 ODM_BB_FA_CNT |
1498 ODM_BB_RSSI_MONITOR |
1499 ODM_BB_CCK_PD |
1500 /*ODM_BB_PWR_TRAIN |*/
1501 ODM_BB_RATE_ADAPTIVE |
1502 ODM_BB_ADAPTIVITY |
1503 ODM_BB_CFO_TRACKING;
1504 /*ODM_BB_ENV_MONITOR*/
1505 break;
1506 #endif
1507
1508 #if (RTL8721D_SUPPORT)
1509 case ODM_RTL8721D:
1510 support_ability |=
1511 ODM_BB_DIG |
1512 ODM_BB_RA_MASK |
1513 /*ODM_BB_DYNAMIC_TXPWR |*/
1514 ODM_BB_FA_CNT |
1515 ODM_BB_RSSI_MONITOR |
1516 ODM_BB_CCK_PD |
1517 /*ODM_BB_PWR_TRAIN |*/
1518 ODM_BB_RATE_ADAPTIVE |
1519 ODM_BB_ADAPTIVITY |
1520 ODM_BB_CFO_TRACKING |
1521 ODM_BB_ENV_MONITOR;
1522 break;
1523 #endif
1524
1525 #if (RTL8710C_SUPPORT)
1526 case ODM_RTL8710C:
1527 support_ability |=
1528 ODM_BB_DIG |
1529 ODM_BB_RA_MASK |
1530 /*ODM_BB_DYNAMIC_TXPWR |*/
1531 ODM_BB_FA_CNT |
1532 ODM_BB_RSSI_MONITOR |
1533 ODM_BB_CCK_PD |
1534 /*ODM_BB_PWR_TRAIN |*/
1535 ODM_BB_RATE_ADAPTIVE |
1536 ODM_BB_ADAPTIVITY |
1537 ODM_BB_CFO_TRACKING |
1538 ODM_BB_ENV_MONITOR;
1539 break;
1540 #endif
1541 default:
1542 support_ability |=
1543 ODM_BB_DIG |
1544 ODM_BB_RA_MASK |
1545 /*ODM_BB_DYNAMIC_TXPWR |*/
1546 ODM_BB_FA_CNT |
1547 ODM_BB_RSSI_MONITOR |
1548 ODM_BB_CCK_PD |
1549 /*ODM_BB_PWR_TRAIN |*/
1550 ODM_BB_RATE_ADAPTIVE |
1551 ODM_BB_CFO_TRACKING |
1552 ODM_BB_ENV_MONITOR;
1553
1554 pr_debug("[Warning] Supportability Init Warning !!!\n");
1555 break;
1556 }
1557
1558 return support_ability;
1559 }
1560 #endif
1561
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1562 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1563 enum phydm_offload_ability offload_ability)
1564 {
1565 switch (offload_ability) {
1566 case PHYDM_PHY_PARAM_OFFLOAD:
1567 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1568 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1569 break;
1570
1571 case PHYDM_RF_IQK_OFFLOAD:
1572 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1573 break;
1574
1575 case PHYDM_RF_DPK_OFFLOAD:
1576 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1577 break;
1578
1579 default:
1580 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1581 break;
1582 }
1583
1584 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1585 dm->fw_offload_ability);
1586 }
1587
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1588 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1589 enum phydm_offload_ability offload_ability)
1590 {
1591 switch (offload_ability) {
1592 case PHYDM_PHY_PARAM_OFFLOAD:
1593 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1594 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1595 break;
1596
1597 case PHYDM_RF_IQK_OFFLOAD:
1598 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1599 break;
1600
1601 case PHYDM_RF_DPK_OFFLOAD:
1602 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1603 break;
1604
1605 default:
1606 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1607 break;
1608 }
1609
1610 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1611 dm->fw_offload_ability);
1612 }
1613
phydm_supportability_init(void * dm_void)1614 void phydm_supportability_init(void *dm_void)
1615 {
1616 struct dm_struct *dm = (struct dm_struct *)dm_void;
1617 u64 support_ability;
1618
1619 if (dm->manual_supportability &&
1620 *dm->manual_supportability != 0xffffffff) {
1621 support_ability = *dm->manual_supportability;
1622 } else if (*dm->mp_mode) {
1623 support_ability = 0;
1624 } else {
1625 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1626 support_ability = phydm_supportability_init_win(dm);
1627 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1628 support_ability = phydm_supportability_init_ap(dm);
1629 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1630 support_ability = phydm_supportability_init_ce(dm);
1631 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1632 support_ability = phydm_supportability_init_iot(dm);
1633 #endif
1634
1635 /*@[Config Antenna Diversity]*/
1636 if (IS_FUNC_EN(dm->enable_antdiv))
1637 support_ability |= ODM_BB_ANT_DIV;
1638
1639 /*@[Config TXpath Diversity]*/
1640 if (IS_FUNC_EN(dm->enable_pathdiv))
1641 support_ability |= ODM_BB_PATH_DIV;
1642
1643 /*@[Config Adaptive SOML]*/
1644 if (IS_FUNC_EN(dm->en_adap_soml))
1645 support_ability |= ODM_BB_ADAPTIVE_SOML;
1646
1647 }
1648 dm->support_ability = support_ability;
1649 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1650 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1651 }
1652
phydm_rfe_init(void * dm_void)1653 void phydm_rfe_init(void *dm_void)
1654 {
1655 struct dm_struct *dm = (struct dm_struct *)dm_void;
1656
1657 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1658 #if (RTL8822B_SUPPORT == 1)
1659 if (dm->support_ic_type == ODM_RTL8822B)
1660 phydm_rfe_8822b_init(dm);
1661 #endif
1662 }
1663
phydm_dm_early_init(struct dm_struct * dm)1664 void phydm_dm_early_init(struct dm_struct *dm)
1665 {
1666 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1667 phydm_init_debug_setting(dm);
1668 #endif
1669 }
1670
odm_dm_init(struct dm_struct * dm)1671 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1672 {
1673 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1674
1675 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1676 pr_debug("[Warning][%s] Init fail\n", __func__);
1677 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1678 }
1679
1680 halrf_init(dm);
1681 phydm_supportability_init(dm);
1682 phydm_pause_func_init(dm);
1683 phydm_rfe_init(dm);
1684 phydm_common_info_self_init(dm);
1685 phydm_rx_phy_status_init(dm);
1686 #ifdef PHYDM_AUTO_DEGBUG
1687 phydm_auto_dbg_engine_init(dm);
1688 #endif
1689 phydm_dig_init(dm);
1690 #ifdef PHYDM_SUPPORT_CCKPD
1691 #ifdef PHYDM_DCC_ENHANCE
1692 phydm_dig_cckpd_coex_init(dm);
1693 #endif
1694 phydm_cck_pd_init(dm);
1695 #endif
1696 phydm_env_monitor_init(dm);
1697 phydm_adaptivity_init(dm);
1698 phydm_ra_info_init(dm);
1699 phydm_rssi_monitor_init(dm);
1700 phydm_cfo_tracking_init(dm);
1701 phydm_rf_init(dm);
1702 phydm_dc_cancellation(dm);
1703 #ifdef PHYDM_TXA_CALIBRATION
1704 phydm_txcurrentcalibration(dm);
1705 phydm_get_pa_bias_offset(dm);
1706 #endif
1707 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1708 odm_antenna_diversity_init(dm);
1709 #endif
1710 #ifdef CONFIG_ADAPTIVE_SOML
1711 phydm_adaptive_soml_init(dm);
1712 #endif
1713 #ifdef CONFIG_PATH_DIVERSITY
1714 phydm_tx_path_diversity_init(dm);
1715 #endif
1716 #ifdef CONFIG_DYNAMIC_TX_TWR
1717 phydm_dynamic_tx_power_init(dm);
1718 #endif
1719 #if (PHYDM_LA_MODE_SUPPORT)
1720 phydm_la_init(dm);
1721 #endif
1722
1723 #ifdef PHYDM_BEAMFORMING_VERSION1
1724 phydm_beamforming_init(dm);
1725 #endif
1726
1727 #if (RTL8188E_SUPPORT)
1728 odm_ra_info_init_all(dm);
1729 #endif
1730 #ifdef PHYDM_PRIMARY_CCA
1731 phydm_primary_cca_init(dm);
1732 #endif
1733 #ifdef CONFIG_PSD_TOOL
1734 phydm_psd_init(dm);
1735 #endif
1736
1737 #ifdef CONFIG_SMART_ANTENNA
1738 phydm_smt_ant_init(dm);
1739 #endif
1740 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1741 phydm_lna_sat_check_init(dm);
1742 #endif
1743 #ifdef CONFIG_MCC_DM
1744 phydm_mcc_init(dm);
1745 #endif
1746
1747 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1748 phydm_cck_rx_pathdiv_init(dm);
1749 #endif
1750
1751 #ifdef CONFIG_MU_RSOML
1752 phydm_mu_rsoml_init(dm);
1753 #endif
1754
1755 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1756 phydm_tx_collsion_th_init(dm);
1757 #endif
1758
1759 return result;
1760 }
1761
odm_dm_reset(struct dm_struct * dm)1762 void odm_dm_reset(struct dm_struct *dm)
1763 {
1764 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1765 odm_ant_div_reset(dm);
1766 #endif
1767 phydm_set_edcca_threshold_api(dm);
1768 }
1769
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1770 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1771 char *output, u32 *_out_len)
1772 {
1773 struct dm_struct *dm = (struct dm_struct *)dm_void;
1774 u32 dm_value[10] = {0};
1775 u64 pre_support_ability, one = 1;
1776 u64 comp = 0;
1777 u32 used = *_used;
1778 u32 out_len = *_out_len;
1779 u8 i;
1780
1781 for (i = 0; i < 5; i++) {
1782 if (input[i + 1])
1783 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1784 }
1785
1786 pre_support_ability = dm->support_ability;
1787 comp = dm->support_ability;
1788
1789 PDM_SNPF(out_len, used, output + used, out_len - used,
1790 "\n================================\n");
1791
1792 if (dm_value[0] == 100) {
1793 PDM_SNPF(out_len, used, output + used, out_len - used,
1794 "[Supportability] PhyDM Selection\n");
1795 PDM_SNPF(out_len, used, output + used, out_len - used,
1796 "================================\n");
1797 PDM_SNPF(out_len, used, output + used, out_len - used,
1798 "00. (( %s ))DIG\n",
1799 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1800 PDM_SNPF(out_len, used, output + used, out_len - used,
1801 "01. (( %s ))RA_MASK\n",
1802 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1803 PDM_SNPF(out_len, used, output + used, out_len - used,
1804 "02. (( %s ))DYN_TXPWR\n",
1805 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1806 PDM_SNPF(out_len, used, output + used, out_len - used,
1807 "03. (( %s ))FA_CNT\n",
1808 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1809 PDM_SNPF(out_len, used, output + used, out_len - used,
1810 "04. (( %s ))RSSI_MNTR\n",
1811 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1812 PDM_SNPF(out_len, used, output + used, out_len - used,
1813 "05. (( %s ))CCK_PD\n",
1814 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1815 PDM_SNPF(out_len, used, output + used, out_len - used,
1816 "06. (( %s ))ANT_DIV\n",
1817 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1818 PDM_SNPF(out_len, used, output + used, out_len - used,
1819 "07. (( %s ))SMT_ANT\n",
1820 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1821 PDM_SNPF(out_len, used, output + used, out_len - used,
1822 "08. (( %s ))PWR_TRAIN\n",
1823 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1824 PDM_SNPF(out_len, used, output + used, out_len - used,
1825 "09. (( %s ))RA\n",
1826 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1827 PDM_SNPF(out_len, used, output + used, out_len - used,
1828 "10. (( %s ))PATH_DIV\n",
1829 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1830 PDM_SNPF(out_len, used, output + used, out_len - used,
1831 "11. (( %s ))DFS\n",
1832 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1833 PDM_SNPF(out_len, used, output + used, out_len - used,
1834 "12. (( %s ))DYN_ARFR\n",
1835 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1836 PDM_SNPF(out_len, used, output + used, out_len - used,
1837 "13. (( %s ))ADAPTIVITY\n",
1838 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1839 PDM_SNPF(out_len, used, output + used, out_len - used,
1840 "14. (( %s ))CFO_TRACK\n",
1841 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1842 PDM_SNPF(out_len, used, output + used, out_len - used,
1843 "15. (( %s ))ENV_MONITOR\n",
1844 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1845 PDM_SNPF(out_len, used, output + used, out_len - used,
1846 "16. (( %s ))PRI_CCA\n",
1847 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1848 PDM_SNPF(out_len, used, output + used, out_len - used,
1849 "17. (( %s ))ADPTV_SOML\n",
1850 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1851 PDM_SNPF(out_len, used, output + used, out_len - used,
1852 "18. (( %s ))LNA_SAT_CHK\n",
1853 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1854 PDM_SNPF(out_len, used, output + used, out_len - used,
1855 "================================\n");
1856 PDM_SNPF(out_len, used, output + used, out_len - used,
1857 "[Supportability] PhyDM offload ability\n");
1858 PDM_SNPF(out_len, used, output + used, out_len - used,
1859 "================================\n");
1860
1861 PDM_SNPF(out_len, used, output + used, out_len - used,
1862 "00. (( %s ))PHY PARAM OFFLOAD\n",
1863 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1864 ("V") : (".")));
1865 PDM_SNPF(out_len, used, output + used, out_len - used,
1866 "01. (( %s ))RF IQK OFFLOAD\n",
1867 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1868 ("V") : (".")));
1869 PDM_SNPF(out_len, used, output + used, out_len - used,
1870 "================================\n");
1871
1872 } else if (dm_value[0] == 101) {
1873 dm->support_ability = 0;
1874 PDM_SNPF(out_len, used, output + used, out_len - used,
1875 "Disable all support_ability components\n");
1876 } else {
1877 if (dm_value[1] == 1) { /* @enable */
1878 dm->support_ability |= (one << dm_value[0]);
1879 } else if (dm_value[1] == 2) {/* @disable */
1880 dm->support_ability &= ~(one << dm_value[0]);
1881 } else {
1882 PDM_SNPF(out_len, used, output + used, out_len - used,
1883 "[Warning!!!] 1:enable, 2:disable\n");
1884 }
1885 }
1886 PDM_SNPF(out_len, used, output + used, out_len - used,
1887 "pre-supportability = 0x%llx\n", pre_support_ability);
1888 PDM_SNPF(out_len, used, output + used, out_len - used,
1889 "Cur-supportability = 0x%llx\n", dm->support_ability);
1890 PDM_SNPF(out_len, used, output + used, out_len - used,
1891 "================================\n");
1892
1893 *_used = used;
1894 *_out_len = out_len;
1895 }
1896
phydm_watchdog_lps_32k(struct dm_struct * dm)1897 void phydm_watchdog_lps_32k(struct dm_struct *dm)
1898 {
1899 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1900
1901 phydm_common_info_self_update(dm);
1902 phydm_rssi_monitor_check(dm);
1903 phydm_dig_lps_32k(dm);
1904 phydm_common_info_self_reset(dm);
1905 }
1906
phydm_watchdog_lps(struct dm_struct * dm)1907 void phydm_watchdog_lps(struct dm_struct *dm)
1908 {
1909 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1910 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1911
1912 phydm_common_info_self_update(dm);
1913 phydm_rssi_monitor_check(dm);
1914 phydm_basic_dbg_message(dm);
1915 phydm_receiver_blocking(dm);
1916 phydm_false_alarm_counter_statistics(dm);
1917 phydm_dig_by_rssi_lps(dm);
1918 #ifdef PHYDM_SUPPORT_CCKPD
1919 phydm_cck_pd_th(dm);
1920 #endif
1921 phydm_adaptivity(dm);
1922 #ifdef CONFIG_BW_INDICATION
1923 phydm_dyn_bw_indication(dm);
1924 #endif
1925 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1926 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1927 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
1928 odm_antenna_diversity(dm);
1929 #endif
1930 #endif
1931 phydm_common_info_self_reset(dm);
1932 #endif
1933 }
1934
phydm_watchdog_mp(struct dm_struct * dm)1935 void phydm_watchdog_mp(struct dm_struct *dm)
1936 {
1937 }
1938
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)1939 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
1940 {
1941 struct dm_struct *dm = (struct dm_struct *)dm_void;
1942
1943 if (pause_type == PHYDM_PAUSE) {
1944 dm->disable_phydm_watchdog = 1;
1945 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
1946 } else {
1947 dm->disable_phydm_watchdog = 0;
1948 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
1949 }
1950 }
1951
phydm_pause_func_init(void * dm_void)1952 void phydm_pause_func_init(void *dm_void)
1953 {
1954 struct dm_struct *dm = (struct dm_struct *)dm_void;
1955
1956 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
1957 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
1958 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
1959 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
1960 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
1961 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
1962 }
1963
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)1964 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
1965 enum phydm_pause_type pause_type,
1966 enum phydm_pause_level pause_lv, u8 val_lehgth,
1967 u32 *val_buf)
1968 {
1969 struct dm_struct *dm = (struct dm_struct *)dm_void;
1970 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
1971 s8 *pause_lv_pre = &dm->s8_dummy;
1972 u32 *bkp_val = &dm->u32_dummy;
1973 u32 ori_val[5] = {0};
1974 u64 pause_func_bitmap = (u64)BIT(pause_func);
1975 u8 i = 0;
1976 u8 en_2rcca = 0;
1977 u8 en_bw40m = 0;
1978 u8 pause_result = PAUSE_FAIL;
1979
1980 PHYDM_DBG(dm, ODM_COMP_API, "\n");
1981 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
1982 ((pause_type == PHYDM_PAUSE) ? "Pause" :
1983 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
1984 pause_lv, val_lehgth);
1985
1986 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
1987 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
1988 return PAUSE_FAIL;
1989 }
1990
1991 if (pause_func == F00_DIG) {
1992 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
1993
1994 if (val_lehgth != 1) {
1995 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1996 return PAUSE_FAIL;
1997 }
1998
1999 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2000 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2001 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2002 /*@function pointer hook*/
2003 func_t->pause_phydm_handler = phydm_set_dig_val;
2004
2005 #ifdef PHYDM_SUPPORT_CCKPD
2006 } else if (pause_func == F05_CCK_PD) {
2007 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2008
2009 if (val_lehgth != 1) {
2010 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2011 return PAUSE_FAIL;
2012 }
2013
2014 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2015 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2016 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2017 /*@function pointer hook*/
2018 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2019 #endif
2020
2021 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2022 } else if (pause_func == F06_ANT_DIV) {
2023 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2024
2025 if (val_lehgth != 1) {
2026 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2027 return PAUSE_FAIL;
2028 }
2029 /*@default antenna*/
2030 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2031 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2032 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2033 /*@function pointer hook*/
2034 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2035
2036 #endif
2037 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2038 } else if (pause_func == F13_ADPTVTY) {
2039 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2040
2041 if (val_lehgth != 2) {
2042 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2043 return PAUSE_FAIL;
2044 }
2045
2046 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2047 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2048 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2049 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2050 /*@function pointer hook*/
2051 func_t->pause_phydm_handler = phydm_set_edcca_val;
2052
2053 #endif
2054 #ifdef CONFIG_ADAPTIVE_SOML
2055 } else if (pause_func == F17_ADPTV_SOML) {
2056 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2057
2058 if (val_lehgth != 1) {
2059 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2060 return PAUSE_FAIL;
2061 }
2062 /*SOML_ON/OFF*/
2063 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2064
2065 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2066 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2067 /*@function pointer hook*/
2068 func_t->pause_phydm_handler = phydm_set_adsl_val;
2069
2070 #endif
2071 } else {
2072 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2073 return PAUSE_FAIL;
2074 }
2075
2076 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2077 pause_lv, *pause_lv_pre);
2078
2079 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2080 if (pause_lv <= *pause_lv_pre) {
2081 PHYDM_DBG(dm, ODM_COMP_API,
2082 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2083 return PAUSE_FAIL;
2084 }
2085
2086 if (!(dm->pause_ability & pause_func_bitmap)) {
2087 for (i = 0; i < val_lehgth; i++)
2088 bkp_val[i] = ori_val[i];
2089 }
2090
2091 dm->pause_ability |= pause_func_bitmap;
2092 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2093 dm->pause_ability);
2094
2095 if (pause_type == PHYDM_PAUSE) {
2096 for (i = 0; i < val_lehgth; i++)
2097 PHYDM_DBG(dm, ODM_COMP_API,
2098 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2099 i, val_buf[i], bkp_val[i]);
2100 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2101 } else {
2102 for (i = 0; i < val_lehgth; i++)
2103 PHYDM_DBG(dm, ODM_COMP_API,
2104 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2105 i, bkp_val[i]);
2106 }
2107
2108 *pause_lv_pre = pause_lv;
2109 pause_result = PAUSE_SUCCESS;
2110
2111 } else if (pause_type == PHYDM_RESUME) {
2112 if (pause_lv < *pause_lv_pre) {
2113 PHYDM_DBG(dm, ODM_COMP_API,
2114 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2115 return PAUSE_FAIL;
2116 }
2117
2118 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2119 PHYDM_DBG(dm, ODM_COMP_API,
2120 "[RESUME] No Need to Revert\n");
2121 return PAUSE_SUCCESS;
2122 }
2123
2124 dm->pause_ability &= ~pause_func_bitmap;
2125 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2126 dm->pause_ability);
2127
2128 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2129
2130 for (i = 0; i < val_lehgth; i++) {
2131 PHYDM_DBG(dm, ODM_COMP_API,
2132 "[RESUME] val_idx[%d]={0x%x}\n", i,
2133 bkp_val[i]);
2134 }
2135
2136 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2137
2138 pause_result = PAUSE_SUCCESS;
2139 } else {
2140 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2141 pause_result = PAUSE_FAIL;
2142 }
2143 return pause_result;
2144 }
2145
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2146 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2147 char *output, u32 *_out_len)
2148 {
2149 struct dm_struct *dm = (struct dm_struct *)dm_void;
2150 char help[] = "-h";
2151 u32 var1[10] = {0};
2152 u32 used = *_used;
2153 u32 out_len = *_out_len;
2154 u32 i;
2155 u8 length = 0;
2156 u32 buf[5] = {0};
2157 u8 set_result = 0;
2158 enum phydm_func_idx func = 0;
2159 enum phydm_pause_type type = 0;
2160 enum phydm_pause_level lv = 0;
2161
2162 if ((strcmp(input[1], help) == 0)) {
2163 PDM_SNPF(out_len, used, output + used, out_len - used,
2164 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2165
2166 goto out;
2167 }
2168
2169 for (i = 0; i < 10; i++) {
2170 if (input[i + 1])
2171 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2172 }
2173
2174 func = (enum phydm_func_idx)var1[0];
2175 type = (enum phydm_pause_type)var1[1];
2176 lv = (enum phydm_pause_level)var1[2];
2177
2178 for (i = 0; i < 5; i++)
2179 buf[i] = var1[3 + i];
2180
2181 if (func == F00_DIG) {
2182 PDM_SNPF(out_len, used, output + used, out_len - used,
2183 "[DIG]\n");
2184 length = 1;
2185
2186 } else if (func == F05_CCK_PD) {
2187 PDM_SNPF(out_len, used, output + used, out_len - used,
2188 "[CCK_PD]\n");
2189 length = 1;
2190 } else if (func == F06_ANT_DIV) {
2191 PDM_SNPF(out_len, used, output + used, out_len - used,
2192 "[Ant_Div]\n");
2193 length = 1;
2194 } else if (func == F13_ADPTVTY) {
2195 PDM_SNPF(out_len, used, output + used, out_len - used,
2196 "[Adaptivity]\n");
2197 length = 2;
2198 } else if (func == F17_ADPTV_SOML) {
2199 PDM_SNPF(out_len, used, output + used, out_len - used,
2200 "[ADSL]\n");
2201 length = 1;
2202 } else {
2203 PDM_SNPF(out_len, used, output + used, out_len - used,
2204 "[Set Function Error]\n");
2205 length = 0;
2206 }
2207
2208 if (length != 0) {
2209 PDM_SNPF(out_len, used, output + used, out_len - used,
2210 "{%s, lv=%d} val = %d, %d}\n",
2211 ((type == PHYDM_PAUSE) ? "Pause" :
2212 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2213 lv, var1[3], var1[4]);
2214
2215 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2216 }
2217
2218 PDM_SNPF(out_len, used, output + used, out_len - used,
2219 "set_result = %d\n", set_result);
2220
2221 out:
2222 *_used = used;
2223 *_out_len = out_len;
2224 }
2225
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2226 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2227 enum phydm_pause_type pause_type, u8 rssi)
2228 {
2229 u32 igi_val = rssi + 10;
2230 u32 th_buf[2];
2231
2232 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2233 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2234 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2235 rssi);
2236
2237 if (pause_type == PHYDM_RESUME) {
2238 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2239 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2240
2241 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2242 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2243 } else {
2244 odm_write_dig(dm, (u8)igi_val);
2245 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2246 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2247
2248 th_buf[0] = 0xff;
2249 th_buf[1] = 0xff;
2250
2251 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2252 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2253 }
2254 }
2255
phydm_stop_dm_watchdog_check(void * dm_void)2256 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2257 {
2258 struct dm_struct *dm = (struct dm_struct *)dm_void;
2259
2260 if (dm->disable_phydm_watchdog == 1) {
2261 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2262 return true;
2263 } else {
2264 return false;
2265 }
2266 }
2267
phydm_watchdog(struct dm_struct * dm)2268 void phydm_watchdog(struct dm_struct *dm)
2269 {
2270 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2271
2272 phydm_common_info_self_update(dm);
2273 phydm_phy_info_update(dm);
2274 phydm_rssi_monitor_check(dm);
2275 phydm_basic_dbg_message(dm);
2276 phydm_dm_summary(dm, FIRST_MACID);
2277 #ifdef PHYDM_AUTO_DEGBUG
2278 phydm_auto_dbg_engine(dm);
2279 #endif
2280 phydm_receiver_blocking(dm);
2281
2282 if (phydm_stop_dm_watchdog_check(dm) == true)
2283 return;
2284
2285 phydm_hw_setting(dm);
2286
2287 #ifdef PHYDM_TDMA_DIG_SUPPORT
2288 if (dm->original_dig_restore == 0) {
2289 phydm_tdma_dig_timer_check(dm);
2290 } else
2291 #endif
2292 {
2293 phydm_false_alarm_counter_statistics(dm);
2294 phydm_noisy_detection(dm);
2295
2296 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2297 phydm_dig_cckpd_coex(dm);
2298 #else
2299 phydm_dig(dm);
2300 #ifdef PHYDM_SUPPORT_CCKPD
2301 phydm_cck_pd_th(dm);
2302 #endif
2303 #endif
2304 }
2305
2306 #ifdef PHYDM_HW_IGI
2307 phydm_hwigi(dm);
2308 #endif
2309 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2310 phydm_update_power_training_state(dm);
2311 #endif
2312 phydm_adaptivity(dm);
2313 phydm_ra_info_watchdog(dm);
2314 #ifdef CONFIG_PATH_DIVERSITY
2315 phydm_tx_path_diversity(dm);
2316 #endif
2317 phydm_cfo_tracking(dm);
2318 #ifdef CONFIG_DYNAMIC_TX_TWR
2319 phydm_dynamic_tx_power(dm);
2320 #endif
2321 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2322 odm_antenna_diversity(dm);
2323 #endif
2324 #ifdef CONFIG_ADAPTIVE_SOML
2325 phydm_adaptive_soml(dm);
2326 #endif
2327
2328 #ifdef PHYDM_BEAMFORMING_VERSION1
2329 phydm_beamforming_watchdog(dm);
2330 #endif
2331
2332 halrf_watchdog(dm);
2333 #ifdef PHYDM_PRIMARY_CCA
2334 phydm_primary_cca(dm);
2335 #endif
2336 #ifdef CONFIG_BW_INDICATION
2337 phydm_dyn_bw_indication(dm);
2338 #endif
2339 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2340 odm_dtc(dm);
2341 #endif
2342
2343 phydm_env_mntr_watchdog(dm);
2344
2345 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2346 phydm_lna_sat_chk_watchdog(dm);
2347 #endif
2348
2349 #ifdef CONFIG_MCC_DM
2350 phydm_mcc_switch(dm);
2351 #endif
2352
2353 #ifdef CONFIG_MU_RSOML
2354 phydm_mu_rsoml_decision(dm);
2355 #endif
2356
2357 phydm_common_info_self_reset(dm);
2358 }
2359
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2360 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2361 boolean enable)
2362 {
2363 struct dm_struct *dm = (struct dm_struct *)dm_void;
2364 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2365 u8 para4[4]; /*4 bit*/
2366 u8 para8[4]; /*8 bit*/
2367 u8 i = 0;
2368
2369 for (i = 0; i < 4; i++) {
2370 para4[i] = 0;
2371 para8[i] = 0;
2372 }
2373
2374 switch (fun_idx) {
2375 case F00_DIG:
2376 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2377 break;
2378 default:
2379 pr_debug("[Warning] %s\n", __func__);
2380 return;
2381 }
2382
2383 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2384 h2c_val[1] = para8[0];
2385 h2c_val[2] = para8[1];
2386 h2c_val[3] = para8[2];
2387 h2c_val[4] = para8[3];
2388 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2389 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2390
2391 PHYDM_DBG(dm, DBG_FW_DM,
2392 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2393 fun_idx, enable,
2394 para8[0], para8[1], para8[2], para8[3],
2395 para4[0], para4[1], para4[2], para4[3]);
2396
2397 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2398 }
2399
2400 /*@
2401 * Init /.. Fixed HW value. Only init time.
2402 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2403 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2404 u64 value)
2405 {
2406 /* This section is used for init value */
2407 switch (cmn_info) {
2408 /* @Fixed ODM value. */
2409 case ODM_CMNINFO_ABILITY:
2410 dm->support_ability = (u64)value;
2411 break;
2412
2413 case ODM_CMNINFO_RF_TYPE:
2414 dm->rf_type = (u8)value;
2415 break;
2416
2417 case ODM_CMNINFO_PLATFORM:
2418 dm->support_platform = (u8)value;
2419 break;
2420
2421 case ODM_CMNINFO_INTERFACE:
2422 dm->support_interface = (u8)value;
2423 break;
2424
2425 case ODM_CMNINFO_MP_TEST_CHIP:
2426 dm->is_mp_chip = (u8)value;
2427 break;
2428
2429 case ODM_CMNINFO_IC_TYPE:
2430 dm->support_ic_type = (u32)value;
2431 break;
2432
2433 case ODM_CMNINFO_CUT_VER:
2434 dm->cut_version = (u8)value;
2435 break;
2436
2437 case ODM_CMNINFO_FAB_VER:
2438 dm->fab_version = (u8)value;
2439 break;
2440 case ODM_CMNINFO_FW_VER:
2441 dm->fw_version = (u8)value;
2442 break;
2443 case ODM_CMNINFO_FW_SUB_VER:
2444 dm->fw_sub_version = (u8)value;
2445 break;
2446 case ODM_CMNINFO_RFE_TYPE:
2447 #if (RTL8821C_SUPPORT)
2448 if (dm->support_ic_type & ODM_RTL8821C)
2449 dm->rfe_type_expand = (u8)value;
2450 else
2451 #endif
2452 dm->rfe_type = (u8)value;
2453
2454 #ifdef CONFIG_RFE_BY_HW_INFO
2455 phydm_init_hw_info_by_rfe(dm);
2456 #endif
2457 break;
2458
2459 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2460 dm->ant_div_type = (u8)value;
2461 break;
2462
2463 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2464 dm->with_extenal_ant_switch = (u8)value;
2465 break;
2466
2467 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2468 case ODM_CMNINFO_BE_FIX_TX_ANT:
2469 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2470 break;
2471 #endif
2472
2473 case ODM_CMNINFO_BOARD_TYPE:
2474 if (!dm->is_init_hw_info_by_rfe)
2475 dm->board_type = (u8)value;
2476 break;
2477
2478 case ODM_CMNINFO_PACKAGE_TYPE:
2479 if (!dm->is_init_hw_info_by_rfe)
2480 dm->package_type = (u8)value;
2481 break;
2482
2483 case ODM_CMNINFO_EXT_LNA:
2484 if (!dm->is_init_hw_info_by_rfe)
2485 dm->ext_lna = (u8)value;
2486 break;
2487
2488 case ODM_CMNINFO_5G_EXT_LNA:
2489 if (!dm->is_init_hw_info_by_rfe)
2490 dm->ext_lna_5g = (u8)value;
2491 break;
2492
2493 case ODM_CMNINFO_EXT_PA:
2494 if (!dm->is_init_hw_info_by_rfe)
2495 dm->ext_pa = (u8)value;
2496 break;
2497
2498 case ODM_CMNINFO_5G_EXT_PA:
2499 if (!dm->is_init_hw_info_by_rfe)
2500 dm->ext_pa_5g = (u8)value;
2501 break;
2502
2503 case ODM_CMNINFO_GPA:
2504 if (!dm->is_init_hw_info_by_rfe)
2505 dm->type_gpa = (u16)value;
2506 break;
2507
2508 case ODM_CMNINFO_APA:
2509 if (!dm->is_init_hw_info_by_rfe)
2510 dm->type_apa = (u16)value;
2511 break;
2512
2513 case ODM_CMNINFO_GLNA:
2514 if (!dm->is_init_hw_info_by_rfe)
2515 dm->type_glna = (u16)value;
2516 break;
2517
2518 case ODM_CMNINFO_ALNA:
2519 if (!dm->is_init_hw_info_by_rfe)
2520 dm->type_alna = (u16)value;
2521 break;
2522
2523 case ODM_CMNINFO_EXT_TRSW:
2524 if (!dm->is_init_hw_info_by_rfe)
2525 dm->ext_trsw = (u8)value;
2526 break;
2527 case ODM_CMNINFO_EXT_LNA_GAIN:
2528 dm->ext_lna_gain = (u8)value;
2529 break;
2530 case ODM_CMNINFO_PATCH_ID:
2531 dm->iot_table.win_patch_id = (u8)value;
2532 break;
2533 case ODM_CMNINFO_BINHCT_TEST:
2534 dm->is_in_hct_test = (boolean)value;
2535 break;
2536 case ODM_CMNINFO_BWIFI_TEST:
2537 dm->wifi_test = (u8)value;
2538 break;
2539 case ODM_CMNINFO_SMART_CONCURRENT:
2540 dm->is_dual_mac_smart_concurrent = (boolean)value;
2541 break;
2542 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2543 case ODM_CMNINFO_CONFIG_BB_RF:
2544 dm->config_bbrf = (boolean)value;
2545 break;
2546 #endif
2547 case ODM_CMNINFO_IQKPAOFF:
2548 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2549 break;
2550 case ODM_CMNINFO_REGRFKFREEENABLE:
2551 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2552 break;
2553 case ODM_CMNINFO_RFKFREEENABLE:
2554 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2555 break;
2556 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2557 dm->normal_rx_path = (u8)value;
2558 break;
2559 case ODM_CMNINFO_VALID_PATH_SET:
2560 dm->valid_path_set = (u8)value;
2561 break;
2562 case ODM_CMNINFO_EFUSE0X3D8:
2563 dm->efuse0x3d8 = (u8)value;
2564 break;
2565 case ODM_CMNINFO_EFUSE0X3D7:
2566 dm->efuse0x3d7 = (u8)value;
2567 break;
2568 case ODM_CMNINFO_ADVANCE_OTA:
2569 dm->p_advance_ota = (u8)value;
2570 break;
2571
2572 #ifdef CONFIG_PHYDM_DFS_MASTER
2573 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2574 dm->dfs_region_domain = (u8)value;
2575 break;
2576 #endif
2577 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2578 dm->soft_ap_special_setting = (u32)value;
2579 break;
2580
2581 case ODM_CMNINFO_X_CAP_SETTING:
2582 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2583 break;
2584
2585 case ODM_CMNINFO_DPK_EN:
2586 /*@dm->dpk_en = (u1Byte)value;*/
2587 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2588 break;
2589
2590 case ODM_CMNINFO_HP_HWID:
2591 dm->hp_hw_id = (boolean)value;
2592 break;
2593 case ODM_CMNINFO_TSSI_ENABLE:
2594 dm->en_tssi_mode = (u8)value;
2595 break;
2596 case ODM_CMNINFO_DIS_DPD:
2597 dm->en_dis_dpd = (boolean)value;
2598 break;
2599 case ODM_CMNINFO_EN_AUTO_BW_TH:
2600 dm->en_auto_bw_th = (u8)value;
2601 break;
2602 #if (RTL8721D_SUPPORT)
2603 case ODM_CMNINFO_POWER_VOLTAGE:
2604 dm->power_voltage = (u8)value;
2605 break;
2606 case ODM_CMNINFO_ANTDIV_GPIO:
2607 dm->antdiv_gpio = (u8)value;
2608 break;
2609 case ODM_CMNINFO_PEAK_DETECT_MODE:
2610 dm->peak_detect_mode = (u8)value;
2611 break;
2612 #endif
2613 default:
2614 break;
2615 }
2616 }
2617
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2618 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2619 void *value)
2620 {
2621 /* @Hook call by reference pointer. */
2622 switch (cmn_info) {
2623 /* @Dynamic call by reference pointer. */
2624 case ODM_CMNINFO_TX_UNI:
2625 dm->num_tx_bytes_unicast = (u64 *)value;
2626 break;
2627
2628 case ODM_CMNINFO_RX_UNI:
2629 dm->num_rx_bytes_unicast = (u64 *)value;
2630 break;
2631
2632 case ODM_CMNINFO_BAND:
2633 dm->band_type = (u8 *)value;
2634 break;
2635
2636 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2637 dm->sec_ch_offset = (u8 *)value;
2638 break;
2639
2640 case ODM_CMNINFO_SEC_MODE:
2641 dm->security = (u8 *)value;
2642 break;
2643
2644 case ODM_CMNINFO_BW:
2645 dm->band_width = (u8 *)value;
2646 break;
2647
2648 case ODM_CMNINFO_CHNL:
2649 dm->channel = (u8 *)value;
2650 break;
2651
2652 case ODM_CMNINFO_SCAN:
2653 dm->is_scan_in_process = (boolean *)value;
2654 break;
2655
2656 case ODM_CMNINFO_POWER_SAVING:
2657 dm->is_power_saving = (boolean *)value;
2658 break;
2659
2660 case ODM_CMNINFO_TDMA:
2661 dm->is_tdma = (boolean *)value;
2662 break;
2663
2664 case ODM_CMNINFO_ONE_PATH_CCA:
2665 dm->one_path_cca = (u8 *)value;
2666 break;
2667
2668 case ODM_CMNINFO_DRV_STOP:
2669 dm->is_driver_stopped = (boolean *)value;
2670 break;
2671 case ODM_CMNINFO_INIT_ON:
2672 dm->pinit_adpt_in_progress = (boolean *)value;
2673 break;
2674
2675 case ODM_CMNINFO_ANT_TEST:
2676 dm->antenna_test = (u8 *)value;
2677 break;
2678
2679 case ODM_CMNINFO_NET_CLOSED:
2680 dm->is_net_closed = (boolean *)value;
2681 break;
2682
2683 case ODM_CMNINFO_FORCED_RATE:
2684 dm->forced_data_rate = (u16 *)value;
2685 break;
2686 case ODM_CMNINFO_ANT_DIV:
2687 dm->enable_antdiv = (u8 *)value;
2688 break;
2689 case ODM_CMNINFO_PATH_DIV:
2690 dm->enable_pathdiv = (u8 *)value;
2691 break;
2692 case ODM_CMNINFO_ADAPTIVE_SOML:
2693 dm->en_adap_soml = (u8 *)value;
2694 break;
2695 case ODM_CMNINFO_ADAPTIVITY:
2696 dm->edcca_mode = (u8 *)value;
2697 break;
2698
2699 case ODM_CMNINFO_P2P_LINK:
2700 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2701 break;
2702
2703 case ODM_CMNINFO_IS1ANTENNA:
2704 dm->is_1_antenna = (boolean *)value;
2705 break;
2706
2707 case ODM_CMNINFO_RFDEFAULTPATH:
2708 dm->rf_default_path = (u8 *)value;
2709 break;
2710
2711 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2712 dm->is_fcs_mode_enable = (boolean *)value;
2713 break;
2714
2715 case ODM_CMNINFO_HUBUSBMODE:
2716 dm->hub_usb_mode = (u8 *)value;
2717 break;
2718 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2719 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2720 break;
2721 case ODM_CMNINFO_TX_TP:
2722 dm->current_tx_tp = (u32 *)value;
2723 break;
2724 case ODM_CMNINFO_RX_TP:
2725 dm->current_rx_tp = (u32 *)value;
2726 break;
2727 case ODM_CMNINFO_SOUNDING_SEQ:
2728 dm->sounding_seq = (u8 *)value;
2729 break;
2730 #ifdef CONFIG_PHYDM_DFS_MASTER
2731 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2732 dm->dfs_master_enabled = (u8 *)value;
2733 break;
2734 #endif
2735
2736 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2737 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2738 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2739 break;
2740 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2741 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2742 break;
2743 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2744 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2745 break;
2746 #endif
2747
2748 case ODM_CMNINFO_SOFT_AP_MODE:
2749 dm->soft_ap_mode = (u32 *)value;
2750 break;
2751 case ODM_CMNINFO_MP_MODE:
2752 dm->mp_mode = (u8 *)value;
2753 break;
2754 case ODM_CMNINFO_INTERRUPT_MASK:
2755 dm->interrupt_mask = (u32 *)value;
2756 break;
2757 case ODM_CMNINFO_BB_OPERATION_MODE:
2758 dm->bb_op_mode = (u8 *)value;
2759 break;
2760 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2761 dm->manual_supportability = (u32 *)value;
2762 break;
2763 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2764 dm->dis_dym_bw_indication = (u8 *)value;
2765 default:
2766 /*do nothing*/
2767 break;
2768 }
2769 }
2770
2771 /*@
2772 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2773 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2774 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2775 {
2776 /* This init variable may be changed in run time. */
2777 switch (cmn_info) {
2778 case ODM_CMNINFO_LINK_IN_PROGRESS:
2779 dm->is_link_in_process = (boolean)value;
2780 break;
2781
2782 case ODM_CMNINFO_ABILITY:
2783 dm->support_ability = (u64)value;
2784 break;
2785
2786 case ODM_CMNINFO_RF_TYPE:
2787 dm->rf_type = (u8)value;
2788 break;
2789
2790 case ODM_CMNINFO_WIFI_DIRECT:
2791 dm->is_wifi_direct = (boolean)value;
2792 break;
2793
2794 case ODM_CMNINFO_WIFI_DISPLAY:
2795 dm->is_wifi_display = (boolean)value;
2796 break;
2797
2798 case ODM_CMNINFO_LINK:
2799 dm->is_linked = (boolean)value;
2800 break;
2801
2802 case ODM_CMNINFO_CMW500LINK:
2803 dm->iot_table.is_linked_cmw500 = (boolean)value;
2804 break;
2805
2806 case ODM_CMNINFO_STATION_STATE:
2807 dm->bsta_state = (boolean)value;
2808 break;
2809
2810 case ODM_CMNINFO_RSSI_MIN:
2811 #if 0
2812 dm->rssi_min = (u8)value;
2813 #endif
2814 break;
2815
2816 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2817 dm->rssi_min_by_path = (u8)value;
2818 break;
2819
2820 case ODM_CMNINFO_DBG_COMP:
2821 dm->debug_components = (u64)value;
2822 break;
2823
2824 #ifdef ODM_CONFIG_BT_COEXIST
2825 /* The following is for BT HS mode and BT coexist mechanism. */
2826 case ODM_CMNINFO_BT_ENABLED:
2827 dm->bt_info_table.is_bt_enabled = (boolean)value;
2828 break;
2829
2830 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2831 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2832 break;
2833
2834 case ODM_CMNINFO_BT_HS_RSSI:
2835 dm->bt_info_table.bt_hs_rssi = (u8)value;
2836 break;
2837
2838 case ODM_CMNINFO_BT_OPERATION:
2839 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2840 break;
2841
2842 case ODM_CMNINFO_BT_LIMITED_DIG:
2843 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2844 break;
2845 #endif
2846
2847 case ODM_CMNINFO_AP_TOTAL_NUM:
2848 dm->ap_total_num = (u8)value;
2849 break;
2850
2851 #ifdef CONFIG_PHYDM_DFS_MASTER
2852 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2853 dm->dfs_region_domain = (u8)value;
2854 break;
2855 #endif
2856
2857 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2858 dm->is_bt_continuous_turn = (boolean)value;
2859 break;
2860 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2861 dm->is_download_fw = (boolean)value;
2862 break;
2863 case ODM_CMNINFO_PHYDM_PATCH_ID:
2864 dm->iot_table.phydm_patch_id = (u32)value;
2865 break;
2866 case ODM_CMNINFO_RRSR_VAL:
2867 dm->dm_ra_table.rrsr_val_init = (u32)value;
2868 break;
2869 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2870 dm->linked_bf_support = (u8)value;
2871 break;
2872 case ODM_CMNINFO_FLATNESS_TYPE:
2873 dm->flatness_type = (u8)value;
2874 break;
2875 default:
2876 break;
2877 }
2878 }
2879
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)2880 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
2881 {
2882 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2883 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2884 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2885
2886 switch (info_type) {
2887 /*@=== [FA Relative] ===========================================*/
2888 case PHYDM_INFO_FA_OFDM:
2889 return fa_t->cnt_ofdm_fail;
2890
2891 case PHYDM_INFO_FA_CCK:
2892 return fa_t->cnt_cck_fail;
2893
2894 case PHYDM_INFO_FA_TOTAL:
2895 return fa_t->cnt_all;
2896
2897 case PHYDM_INFO_CCA_OFDM:
2898 return fa_t->cnt_ofdm_cca;
2899
2900 case PHYDM_INFO_CCA_CCK:
2901 return fa_t->cnt_cck_cca;
2902
2903 case PHYDM_INFO_CCA_ALL:
2904 return fa_t->cnt_cca_all;
2905
2906 case PHYDM_INFO_CRC32_OK_VHT:
2907 return fa_t->cnt_vht_crc32_ok;
2908
2909 case PHYDM_INFO_CRC32_OK_HT:
2910 return fa_t->cnt_ht_crc32_ok;
2911
2912 case PHYDM_INFO_CRC32_OK_LEGACY:
2913 return fa_t->cnt_ofdm_crc32_ok;
2914
2915 case PHYDM_INFO_CRC32_OK_CCK:
2916 return fa_t->cnt_cck_crc32_ok;
2917
2918 case PHYDM_INFO_CRC32_ERROR_VHT:
2919 return fa_t->cnt_vht_crc32_error;
2920
2921 case PHYDM_INFO_CRC32_ERROR_HT:
2922 return fa_t->cnt_ht_crc32_error;
2923
2924 case PHYDM_INFO_CRC32_ERROR_LEGACY:
2925 return fa_t->cnt_ofdm_crc32_error;
2926
2927 case PHYDM_INFO_CRC32_ERROR_CCK:
2928 return fa_t->cnt_cck_crc32_error;
2929
2930 case PHYDM_INFO_EDCCA_FLAG:
2931 return fa_t->edcca_flag;
2932
2933 case PHYDM_INFO_OFDM_ENABLE:
2934 return fa_t->ofdm_block_enable;
2935
2936 case PHYDM_INFO_CCK_ENABLE:
2937 return fa_t->cck_block_enable;
2938
2939 case PHYDM_INFO_DBG_PORT_0:
2940 return fa_t->dbg_port0;
2941
2942 case PHYDM_INFO_CRC32_OK_HT_AGG:
2943 return fa_t->cnt_ht_crc32_ok_agg;
2944
2945 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
2946 return fa_t->cnt_ht_crc32_error_agg;
2947
2948 /*@=== [DIG] ================================================*/
2949
2950 case PHYDM_INFO_CURR_IGI:
2951 return dig_t->cur_ig_value;
2952
2953 /*@=== [RSSI] ===============================================*/
2954 case PHYDM_INFO_RSSI_MIN:
2955 return (u32)dm->rssi_min;
2956
2957 case PHYDM_INFO_RSSI_MAX:
2958 return (u32)dm->rssi_max;
2959
2960 case PHYDM_INFO_CLM_RATIO:
2961 return (u32)ccx_info->clm_ratio;
2962 case PHYDM_INFO_NHM_RATIO:
2963 return (u32)ccx_info->nhm_ratio;
2964 case PHYDM_INFO_NHM_NOISE_PWR:
2965 return (u32)ccx_info->nhm_level;
2966 default:
2967 return 0xffffffff;
2968 }
2969 }
2970
2971 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)2972 void odm_init_all_work_items(struct dm_struct *dm)
2973 {
2974 void *adapter = dm->adapter;
2975 #if USE_WORKITEM
2976
2977 #ifdef CONFIG_ADAPTIVE_SOML
2978 odm_initialize_work_item(dm,
2979 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
2980 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
2981 (void *)adapter,
2982 "AdaptiveSOMLWorkitem");
2983 #endif
2984
2985 #ifdef ODM_EVM_ENHANCE_ANTDIV
2986 odm_initialize_work_item(dm,
2987 &dm->phydm_evm_antdiv_workitem,
2988 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
2989 (void *)adapter,
2990 "EvmAntdivWorkitem");
2991 #endif
2992
2993 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2994 odm_initialize_work_item(dm,
2995 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2996 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2997 (void *)adapter,
2998 "AntennaSwitchWorkitem");
2999 #endif
3000 #if (defined(CONFIG_HL_SMART_ANTENNA))
3001 odm_initialize_work_item(dm,
3002 &dm->dm_sat_table.hl_smart_antenna_workitem,
3003 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3004 (void *)adapter,
3005 "hl_smart_ant_workitem");
3006
3007 odm_initialize_work_item(dm,
3008 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3009 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3010 (void *)adapter,
3011 "hl_smart_ant_decision_workitem");
3012 #endif
3013
3014 odm_initialize_work_item(
3015 dm,
3016 &dm->ra_rpt_workitem,
3017 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3018 (void *)adapter,
3019 "ra_rpt_workitem");
3020
3021 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3022 odm_initialize_work_item(
3023 dm,
3024 &dm->fast_ant_training_workitem,
3025 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3026 (void *)adapter,
3027 "fast_ant_training_workitem");
3028 #endif
3029
3030 #endif /*#if USE_WORKITEM*/
3031
3032 #ifdef PHYDM_BEAMFORMING_SUPPORT
3033 odm_initialize_work_item(
3034 dm,
3035 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3036 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3037 (void *)adapter,
3038 "txbf_enter_work_item");
3039
3040 odm_initialize_work_item(
3041 dm,
3042 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3043 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3044 (void *)adapter,
3045 "txbf_leave_work_item");
3046
3047 odm_initialize_work_item(
3048 dm,
3049 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3050 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3051 (void *)adapter,
3052 "txbf_fw_ndpa_work_item");
3053
3054 odm_initialize_work_item(
3055 dm,
3056 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3057 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3058 (void *)adapter,
3059 "txbf_clk_work_item");
3060
3061 odm_initialize_work_item(
3062 dm,
3063 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3064 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3065 (void *)adapter,
3066 "txbf_rate_work_item");
3067
3068 odm_initialize_work_item(
3069 dm,
3070 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3071 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3072 (void *)adapter,
3073 "txbf_status_work_item");
3074
3075 odm_initialize_work_item(
3076 dm,
3077 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3078 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3079 (void *)adapter,
3080 "txbf_reset_tx_path_work_item");
3081
3082 odm_initialize_work_item(
3083 dm,
3084 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3085 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3086 (void *)adapter,
3087 "txbf_get_tx_rate_work_item");
3088 #endif
3089
3090 #if (PHYDM_LA_MODE_SUPPORT == 1)
3091 odm_initialize_work_item(
3092 dm,
3093 &dm->adcsmp.adc_smp_work_item,
3094 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3095 (void *)adapter,
3096 "adc_smp_work_item");
3097
3098 odm_initialize_work_item(
3099 dm,
3100 &dm->adcsmp.adc_smp_work_item_1,
3101 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3102 (void *)adapter,
3103 "adc_smp_work_item_1");
3104 #endif
3105 }
3106
odm_free_all_work_items(struct dm_struct * dm)3107 void odm_free_all_work_items(struct dm_struct *dm)
3108 {
3109 #if USE_WORKITEM
3110
3111 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3112 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3113 #endif
3114
3115 #ifdef CONFIG_ADAPTIVE_SOML
3116 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3117 #endif
3118
3119 #ifdef ODM_EVM_ENHANCE_ANTDIV
3120 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3121 #endif
3122
3123 #if (defined(CONFIG_HL_SMART_ANTENNA))
3124 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3125 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3126 #endif
3127
3128 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3129 odm_free_work_item(&dm->fast_ant_training_workitem);
3130 #endif
3131 odm_free_work_item(&dm->ra_rpt_workitem);
3132 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3133 #endif
3134
3135 #ifdef PHYDM_BEAMFORMING_SUPPORT
3136 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3137 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3138 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3139 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3140 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3141 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3142 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3143 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3144 #endif
3145
3146 #if (PHYDM_LA_MODE_SUPPORT == 1)
3147 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3148 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3149 #endif
3150 }
3151 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3152
odm_init_all_timers(struct dm_struct * dm)3153 void odm_init_all_timers(struct dm_struct *dm)
3154 {
3155 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3156 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3157 #endif
3158 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3159 #ifdef IS_USE_NEW_TDMA
3160 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3161 #endif
3162 #endif
3163 #ifdef CONFIG_ADAPTIVE_SOML
3164 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3165 #endif
3166 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3167 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3168 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3169 #endif
3170 #endif
3171
3172 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3173 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3174 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3175 #ifdef PHYDM_BEAMFORMING_SUPPORT
3176 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3177 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3178 "txbf_fw_ndpa_timer");
3179 #endif
3180 #endif
3181
3182 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3183 #ifdef PHYDM_BEAMFORMING_SUPPORT
3184 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3185 (void *)beamforming_sw_timer_callback, NULL,
3186 "beamforming_timer");
3187 #endif
3188 #endif
3189 }
3190
odm_cancel_all_timers(struct dm_struct * dm)3191 void odm_cancel_all_timers(struct dm_struct *dm)
3192 {
3193 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3194 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3195 if (dm->adapter == NULL)
3196 return;
3197 #endif
3198
3199 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3200 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3201 #endif
3202 #ifdef PHYDM_TDMA_DIG_SUPPORT
3203 #ifdef IS_USE_NEW_TDMA
3204 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3205 #endif
3206 #endif
3207 #ifdef CONFIG_ADAPTIVE_SOML
3208 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3209 #endif
3210 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3211 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3212 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3213 #endif
3214 #endif
3215
3216 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3217 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3218 #ifdef PHYDM_BEAMFORMING_SUPPORT
3219 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3220 #endif
3221 #endif
3222
3223 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3224 #ifdef PHYDM_BEAMFORMING_SUPPORT
3225 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3226 #endif
3227 #endif
3228 }
3229
odm_release_all_timers(struct dm_struct * dm)3230 void odm_release_all_timers(struct dm_struct *dm)
3231 {
3232 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3233 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3234 #endif
3235 #ifdef PHYDM_TDMA_DIG_SUPPORT
3236 #ifdef IS_USE_NEW_TDMA
3237 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3238 #endif
3239 #endif
3240 #ifdef CONFIG_ADAPTIVE_SOML
3241 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3242 #endif
3243 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3244 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3245 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3246 #endif
3247 #endif
3248
3249 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3250 odm_release_timer(dm, &dm->sbdcnt_timer);
3251 #ifdef PHYDM_BEAMFORMING_SUPPORT
3252 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3253 #endif
3254 #endif
3255
3256 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3257 #ifdef PHYDM_BEAMFORMING_SUPPORT
3258 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3259 #endif
3260 #endif
3261 }
3262
3263 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3264 void odm_init_all_threads(
3265 struct dm_struct *dm)
3266 {
3267 #ifdef TPT_THREAD
3268 k_tpt_task_init(dm->priv);
3269 #endif
3270 }
3271
odm_stop_all_threads(struct dm_struct * dm)3272 void odm_stop_all_threads(
3273 struct dm_struct *dm)
3274 {
3275 #ifdef TPT_THREAD
3276 k_tpt_task_stop(dm->priv);
3277 #endif
3278 }
3279 #endif
3280
3281 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3282 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3283 * 2012/11/05
3284 */
odm_dtc(struct dm_struct * dm)3285 void odm_dtc(struct dm_struct *dm)
3286 {
3287 #ifdef CONFIG_DM_RESP_TXAGC
3288 /* RSSI higher than this value, start to decade TX power */
3289 #define DTC_BASE 35
3290
3291 /* RSSI lower than this value, start to increase TX power */
3292 #define DTC_DWN_BASE (DTC_BASE - 5)
3293
3294 /* RSSI vs TX power step mapping: decade TX power */
3295 static const u8 dtc_table_down[] = {
3296 DTC_BASE,
3297 (DTC_BASE + 5),
3298 (DTC_BASE + 10),
3299 (DTC_BASE + 15),
3300 (DTC_BASE + 20),
3301 (DTC_BASE + 25)};
3302
3303 /* RSSI vs TX power step mapping: increase TX power */
3304 static const u8 dtc_table_up[] = {
3305 DTC_DWN_BASE,
3306 (DTC_DWN_BASE - 5),
3307 (DTC_DWN_BASE - 10),
3308 (DTC_DWN_BASE - 15),
3309 (DTC_DWN_BASE - 15),
3310 (DTC_DWN_BASE - 20),
3311 (DTC_DWN_BASE - 20),
3312 (DTC_DWN_BASE - 25),
3313 (DTC_DWN_BASE - 25),
3314 (DTC_DWN_BASE - 30),
3315 (DTC_DWN_BASE - 35)};
3316
3317 u8 i;
3318 u8 dtc_steps = 0;
3319 u8 sign;
3320 u8 resp_txagc = 0;
3321
3322 if (dm->rssi_min > DTC_BASE) {
3323 /* need to decade the CTS TX power */
3324 sign = 1;
3325 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3326 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3327 break;
3328 else
3329 dtc_steps++;
3330 }
3331 }
3332 #if 0
3333 else if (dm->rssi_min > DTC_DWN_BASE) {
3334 /* needs to increase the CTS TX power */
3335 sign = 0;
3336 dtc_steps = 1;
3337 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3338 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3339 break;
3340 else
3341 dtc_steps++;
3342 }
3343 }
3344 #endif
3345 else {
3346 sign = 0;
3347 dtc_steps = 0;
3348 }
3349
3350 resp_txagc = dtc_steps | (sign << 4);
3351 resp_txagc = resp_txagc | (resp_txagc << 5);
3352 odm_write_1byte(dm, 0x06d9, resp_txagc);
3353
3354 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3355 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3356 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3357 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3358 }
3359
3360 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3361
3362 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3363 void phydm_dc_cancellation(struct dm_struct *dm)
3364 {
3365 #ifdef PHYDM_DC_CANCELLATION
3366 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3367 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3368 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3369 u8 path = RF_PATH_A;
3370 u8 set_result;
3371
3372 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3373 return;
3374 if ((dm->support_ic_type & ODM_RTL8188F) &&
3375 dm->cut_version < ODM_CUT_D)
3376 return;
3377 if ((dm->support_ic_type & ODM_RTL8192F) &&
3378 dm->cut_version == ODM_CUT_A)
3379 return;
3380 if (*dm->band_width == CHANNEL_WIDTH_5)
3381 return;
3382 if (*dm->band_width == CHANNEL_WIDTH_10)
3383 return;
3384
3385 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3386
3387 /*@DC_Estimation (only for 2x2 ic now) */
3388
3389 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3390 if (path > RF_PATH_A &&
3391 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3392 ODM_RTL8710B | ODM_RTL8721D |
3393 ODM_RTL8710C | ODM_RTL8723D))
3394 break;
3395 else if (path > RF_PATH_B &&
3396 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3397 break;
3398 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3399 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3400 return;
3401 }
3402 odm_write_dig(dm, 0x7e);
3403 /*@Disable LNA*/
3404 if (dm->support_ic_type & ODM_RTL8821C)
3405 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3406 /*Turn off 3-wire*/
3407 phydm_stop_3_wire(dm, PHYDM_SET);
3408 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3409 ODM_RTL8710B)) {
3410 /*set debug port to 0x235*/
3411 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3412 PHYDM_DBG(dm, ODM_COMP_API,
3413 "Set Debug port Fail\n");
3414 return;
3415 }
3416 } else if (dm->support_ic_type & (ODM_RTL8721D |
3417 ODM_RTL8710C)) {
3418 /*set debug port to 0x200*/
3419 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3420 PHYDM_DBG(dm, ODM_COMP_API,
3421 "Set Debug port Fail\n");
3422 return;
3423 }
3424 } else if (dm->support_ic_type & ODM_RTL8821C) {
3425 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3426 /*set debug port to 0x200*/
3427 PHYDM_DBG(dm, ODM_COMP_API,
3428 "Set Debug port Fail\n");
3429 return;
3430 }
3431 phydm_bb_dbg_port_header_sel(dm, 0x0);
3432 } else if (dm->support_ic_type & ODM_RTL8822B) {
3433 if (path == RF_PATH_A &&
3434 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3435 /*set debug port to 0x200*/
3436 PHYDM_DBG(dm, ODM_COMP_API,
3437 "Set Debug port Fail\n");
3438 return;
3439 }
3440 if (path == RF_PATH_B &&
3441 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3442 /*set debug port to 0x200*/
3443 PHYDM_DBG(dm, ODM_COMP_API,
3444 "Set Debug port Fail\n");
3445 return;
3446 }
3447 phydm_bb_dbg_port_header_sel(dm, 0x0);
3448 } else if (dm->support_ic_type & ODM_RTL8192F) {
3449 if (path == RF_PATH_A &&
3450 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3451 /*set debug port to 0x235*/
3452 PHYDM_DBG(dm, ODM_COMP_API,
3453 "Set Debug port Fail\n");
3454 return;
3455 }
3456 if (path == RF_PATH_B &&
3457 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3458 /*set debug port to 0x23d*/
3459 PHYDM_DBG(dm, ODM_COMP_API,
3460 "Set Debug port Fail\n");
3461 return;
3462 }
3463 }
3464
3465 /*@disable CCK DCNF*/
3466 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3467
3468 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3469
3470 phydm_stop_ck320(dm, true); /*stop ck320*/
3471
3472 /* the same debug port both for path-a and path-b*/
3473 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3474
3475 phydm_stop_ck320(dm, false); /*start ck320*/
3476
3477 phydm_release_bb_dbg_port(dm);
3478 /* @Turn on 3-wire*/
3479 phydm_stop_3_wire(dm, PHYDM_REVERT);
3480 /* @Enable LNA*/
3481 if (dm->support_ic_type & ODM_RTL8821C)
3482 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3483
3484 odm_write_dig(dm, 0x20);
3485
3486 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3487
3488 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3489 }
3490
3491 /*@DC_Cancellation*/
3492 /*@DC compensation to CCK data path*/
3493 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3494 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3495 ODM_RTL8710B)) {
3496 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3497 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3498
3499 /*@Before filling into registers,
3500 *offset should be multiplexed (-1)
3501 */
3502 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3503 (0x400 - offset_i_hex[0]) :
3504 (0x1ff - offset_i_hex[0]);
3505 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3506 (0x400 - offset_q_hex[0]) :
3507 (0x1ff - offset_q_hex[0]);
3508
3509 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3510 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3511 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3512 /* Path-a */
3513 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3514 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3515
3516 /*@Before filling into registers,
3517 *offset should be multiplexed (-1)
3518 */
3519 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3520 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3521
3522 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3523 (0x3c0 & offset_i_hex[0]) >> 6);
3524 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3525 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3526 (0x3c0 & offset_q_hex[0]) >> 6);
3527 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3528
3529 /* Path-b */
3530 if (dm->rf_type > RF_1T1R) {
3531 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3532 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3533
3534 /*@Before filling into registers,
3535 *offset should be multiplexed (-1)
3536 */
3537 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3538 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3539
3540 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3541 (0x3c0 & offset_i_hex[1]) >> 6);
3542 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3543 0x3f & offset_i_hex[1]);
3544 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3545 (0x3c0 & offset_q_hex[1]) >> 6);
3546 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3547 0x3f & offset_q_hex[1]);
3548 }
3549 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3550 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3551 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3552 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3553
3554 /*@Before filling into registers,
3555 *offset should be multiplexed (-1)
3556 */
3557 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3558 (0x400 - offset_i_hex[0]) :
3559 (0xff - offset_i_hex[0]);
3560 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3561 (0x400 - offset_q_hex[0]) :
3562 (0xff - offset_q_hex[0]);
3563 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3564 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3565 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3566
3567 /* Path-b */
3568 if (dm->rf_type > RF_1T1R) {
3569 /* @I:df4[27:18],Q:df4[17:8]*/
3570 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3571 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3572
3573 /*@Before filling into registers,
3574 *offset should be multiplexed (-1)
3575 */
3576 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3577 (0x400 - offset_i_hex[1]) :
3578 (0xff - offset_i_hex[1]);
3579 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3580 (0x400 - offset_q_hex[1]) :
3581 (0xff - offset_q_hex[1]);
3582 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3583 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3584 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3585 }
3586 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3587 /*judy modified 20180517*/
3588 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3589 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3590
3591 /*@Before filling into registers,
3592 *offset should be multiplexed (-1)
3593 */
3594 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3595 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3596
3597 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3598 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3599 }
3600 #endif
3601 }
3602
phydm_receiver_blocking(void * dm_void)3603 void phydm_receiver_blocking(void *dm_void)
3604 {
3605 #ifdef CONFIG_RECEIVER_BLOCKING
3606 struct dm_struct *dm = (struct dm_struct *)dm_void;
3607 u32 chnl = *dm->channel;
3608 u8 bw = *dm->band_width;
3609 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3610
3611 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3612 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3613 return;
3614
3615 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3616 dm->support_ic_type & ODM_RTL8192E) {
3617 /*@8188E_T version*/
3618 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3619 goto end;
3620
3621 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3622 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3623 PHYDM_DONT_CARE);
3624 dm->is_rx_blocking_en = true;
3625 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3626 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3627 PHYDM_DONT_CARE);
3628 dm->is_rx_blocking_en = true;
3629 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3630 phydm_nbi_enable(dm, FUNC_DISABLE);
3631 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3632 dm->is_rx_blocking_en = false;
3633 }
3634 return;
3635 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3636 /*@8188E_S version*/
3637 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3638 goto end;
3639
3640 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3641 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3642 PHYDM_DONT_CARE);
3643 dm->is_rx_blocking_en = true;
3644 } else if (dm->is_rx_blocking_en && chnl != 13) {
3645 phydm_nbi_enable(dm, FUNC_DISABLE);
3646 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3647 dm->is_rx_blocking_en = false;
3648 }
3649 return;
3650 }
3651
3652 end:
3653 if (dm->is_rx_blocking_en) {
3654 phydm_nbi_enable(dm, FUNC_DISABLE);
3655 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3656 dm->is_rx_blocking_en = false;
3657 }
3658 #endif
3659 }
3660
phydm_dyn_bw_indication(void * dm_void)3661 void phydm_dyn_bw_indication(void *dm_void)
3662 {
3663 #ifdef CONFIG_BW_INDICATION
3664 struct dm_struct *dm = (struct dm_struct *)dm_void;
3665 u8 en_auto_bw_th = dm->en_auto_bw_th;
3666
3667 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3668 return;
3669
3670 /*driver decide bw cobime timing*/
3671 if (dm->dis_dym_bw_indication) {
3672 if (*dm->dis_dym_bw_indication)
3673 return;
3674 }
3675
3676 /*check for auto bw*/
3677 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3678 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3679 return;
3680 }
3681
3682 phydm_bw_fixed_setting(dm);
3683 #endif
3684 }
3685
3686