1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19 #ifndef __RTL8814A_SPEC_H__ 20 #define __RTL8814A_SPEC_H__ 21 22 #include <drv_conf.h> 23 24 25 //============================================================ 26 // 27 //============================================================ 28 29 //----------------------------------------------------- 30 // 31 // 0x0000h ~ 0x00FFh System Configuration 32 // 33 //----------------------------------------------------- 34 #define REG_SYS_ISO_CTRL_8814A 0x0000 // 2 Byte 35 #define REG_SYS_FUNC_EN_8814A 0x0002 // 2 Byte 36 #define REG_SYS_PW_CTRL_8814A 0x0004 // 4 Byte 37 #define REG_SYS_CLKR_8814A 0x0008 // 2 Byte 38 #define REG_SYS_EEPROM_CTRL_8814A 0x000A // 2 Byte 39 #define REG_EE_VPD_8814A 0x000C // 2 Byte 40 #define REG_SYS_SWR_CTRL1_8814A 0x0010 // 1 Byte 41 #define REG_SPS0_CTRL_8814A 0x0011 // 7 Byte 42 #define REG_SYS_SWR_CTRL3_8814A 0x0018 // 4 Byte 43 #define REG_RSV_CTRL_8814A 0x001C // 3 Byte 44 #define REG_RF_CTRL0_8814A 0x001F // 1 Byte 45 #define REG_RF_CTRL1_8814A 0x0020 // 1 Byte 46 #define REG_RF_CTRL2_8814A 0x0021 // 1 Byte 47 #define REG_LPLDO_CTRL_8814A 0x0023 // 1 Byte 48 #define REG_AFE_CTRL1_8814A 0x0024 // 4 Byte 49 #define REG_AFE_CTRL2_8814A 0x0028 // 4 Byte 50 #define REG_AFE_CTRL3_8814A 0x002c // 4 Byte 51 #define REG_EFUSE_CTRL_8814A 0x0030 52 #define REG_LDO_EFUSE_CTRL_8814A 0x0034 53 #define REG_PWR_DATA_8814A 0x0038 54 #define REG_CAL_TIMER_8814A 0x003C 55 #define REG_ACLK_MON_8814A 0x003E 56 #define REG_GPIO_MUXCFG_8814A 0x0040 57 #define REG_GPIO_IO_SEL_8814A 0x0042 58 #define REG_MAC_PINMUX_CFG_8814A 0x0043 59 #define REG_GPIO_PIN_CTRL_8814A 0x0044 60 #define REG_GPIO_INTM_8814A 0x0048 61 #define REG_LEDCFG0_8814A 0x004C 62 #define REG_LEDCFG1_8814A 0x004D 63 #define REG_LEDCFG2_8814A 0x004E 64 #define REG_LEDCFG3_8814A 0x004F 65 #define REG_FSIMR_8814A 0x0050 66 #define REG_FSISR_8814A 0x0054 67 #define REG_HSIMR_8814A 0x0058 68 #define REG_HSISR_8814A 0x005c 69 #define REG_GPIO_EXT_CTRL_8814A 0x0060 70 #define REG_GPIO_STATUS_8814A 0x006C 71 #define REG_SDIO_CTRL_8814A 0x0070 72 #define REG_HCI_OPT_CTRL_8814A 0x0074 73 #define REG_RF_CTRL3_8814A 0x0076 // 1 Byte 74 #define REG_AFE_CTRL4_8814A 0x0078 75 #define REG_8051FW_CTRL_8814A 0x0080 76 #define REG_HIMR0_8814A 0x00B0 77 #define REG_HISR0_8814A 0x00B4 78 #define REG_HIMR1_8814A 0x00B8 79 #define REG_HISR1_8814A 0x00BC 80 #define REG_SYS_CFG1_8814A 0x00F0 81 #define REG_SYS_CFG2_8814A 0x00FC 82 #define REG_SYS_CFG3_8814A 0x1000 83 84 //----------------------------------------------------- 85 // 86 // 0x0100h ~ 0x01FFh MACTOP General Configuration 87 // 88 //----------------------------------------------------- 89 #define REG_CR_8814A 0x0100 90 #define REG_PBP_8814A 0x0104 91 #define REG_PKT_BUFF_ACCESS_CTRL_8814A 0x0106 92 #define REG_TRXDMA_CTRL_8814A 0x010C 93 #define REG_TRXFF_BNDY_8814A 0x0114 94 #define REG_TRXFF_STATUS_8814A 0x0118 95 #define REG_RXFF_PTR_8814A 0x011C 96 #define REG_CPWM_8814A 0x012F 97 #define REG_FWIMR_8814A 0x0130 98 #define REG_FWISR_8814A 0x0134 99 #define REG_FTIMR_8814A 0x0138 100 #define REG_PKTBUF_DBG_CTRL_8814A 0x0140 101 #define REG_RXPKTBUF_CTRL_8814A 0x0142 102 #define REG_PKTBUF_DBG_DATA_L_8814A 0x0144 103 #define REG_PKTBUF_DBG_DATA_H_8814A 0x0148 104 105 #define REG_TC0_CTRL_8814A 0x0150 106 #define REG_TC1_CTRL_8814A 0x0154 107 #define REG_TC2_CTRL_8814A 0x0158 108 #define REG_TC3_CTRL_8814A 0x015C 109 #define REG_TC4_CTRL_8814A 0x0160 110 #define REG_TCUNIT_BASE_8814A 0x0164 111 #define REG_RSVD3_8814A 0x0168 112 #define REG_C2HEVT_MSG_NORMAL_8814A 0x01A0 113 #define REG_C2HEVT_CLEAR_8814A 0x01AF 114 #define REG_MCUTST_1_8814A 0x01C0 115 #define REG_MCUTST_WOWLAN_8814A 0x01C7 116 #define REG_FMETHR_8814A 0x01C8 117 #define REG_HMETFR_8814A 0x01CC 118 #define REG_HMEBOX_0_8814A 0x01D0 119 #define REG_HMEBOX_1_8814A 0x01D4 120 #define REG_HMEBOX_2_8814A 0x01D8 121 #define REG_HMEBOX_3_8814A 0x01DC 122 #define REG_LLT_INIT_8814A 0x01E0 123 #define REG_LLT_ADDR_8814A 0x01E4 //20130415 KaiYuan add for 8814 124 #define REG_HMEBOX_EXT0_8814A 0x01F0 125 #define REG_HMEBOX_EXT1_8814A 0x01F4 126 #define REG_HMEBOX_EXT2_8814A 0x01F8 127 #define REG_HMEBOX_EXT3_8814A 0x01FC 128 129 //----------------------------------------------------- 130 // 131 // 0x0200h ~ 0x027Fh TXDMA Configuration 132 // 133 //----------------------------------------------------- 134 #define REG_FIFOPAGE_CTRL_1_8814A 0x0200 135 #define REG_FIFOPAGE_CTRL_2_8814A 0x0204 136 #define REG_AUTO_LLT_8814A 0x0208 137 #define REG_TXDMA_OFFSET_CHK_8814A 0x020C 138 #define REG_TXDMA_STATUS_8814A 0x0210 139 #define REG_RQPN_NPQ_8814A 0x0214 140 #define REG_TQPNT1_8814A 0x0218 141 #define REG_TQPNT2_8814A 0x021C 142 #define REG_TQPNT3_8814A 0x0220 143 #define REG_TQPNT4_8814A 0x0224 144 #define REG_RQPN_CTRL_1_8814A 0x0228 145 #define REG_RQPN_CTRL_2_8814A 0x022C 146 #define REG_FIFOPAGE_INFO_1_8814A 0x0230 147 #define REG_FIFOPAGE_INFO_2_8814A 0x0234 148 #define REG_FIFOPAGE_INFO_3_8814A 0x0238 149 #define REG_FIFOPAGE_INFO_4_8814A 0x023C 150 #define REG_FIFOPAGE_INFO_5_8814A 0x0240 151 152 153 //----------------------------------------------------- 154 // 155 // 0x0280h ~ 0x02FFh RXDMA Configuration 156 // 157 //----------------------------------------------------- 158 #define REG_RXDMA_AGG_PG_TH_8814A 0x0280 159 #define REG_RXPKT_NUM_8814A 0x0284 // The number of packets in RXPKTBUF. 160 #define REG_RXDMA_CONTROL_8814A 0x0286 // ?????? Control the RX DMA. 161 #define REG_RXDMA_STATUS_8814A 0x0288 162 #define REG_RXDMA_MODE_8814A 0x0290 // ?????? 163 #define REG_EARLY_MODE_CONTROL_8814A 0x02BC // ?????? 164 #define REG_RSVD5_8814A 0x02F0 // ?????? 165 166 167 //----------------------------------------------------- 168 // 169 // 0x0300h ~ 0x03FFh PCIe 170 // 171 //----------------------------------------------------- 172 #define REG_PCIE_CTRL_REG_8814A 0x0300 173 #define REG_INT_MIG_8814A 0x0304 // Interrupt Migration 174 #define REG_BCNQ_TXBD_DESA_8814A 0x0308 // TX Beacon Descriptor Address 175 #define REG_MGQ_TXBD_DESA_8814A 0x0310 // TX Manage Queue Descriptor Address 176 #define REG_VOQ_TXBD_DESA_8814A 0x0318 // TX VO Queue Descriptor Address 177 #define REG_VIQ_TXBD_DESA_8814A 0x0320 // TX VI Queue Descriptor Address 178 #define REG_BEQ_TXBD_DESA_8814A 0x0328 // TX BE Queue Descriptor Address 179 #define REG_BKQ_TXBD_DESA_8814A 0x0330 // TX BK Queue Descriptor Address 180 #define REG_RXQ_RXBD_DESA_8814A 0x0338 // RX Queue Descriptor Address 181 #define REG_HI0Q_TXBD_DESA_8814A 0x0340 182 #define REG_HI1Q_TXBD_DESA_8814A 0x0348 183 #define REG_HI2Q_TXBD_DESA_8814A 0x0350 184 #define REG_HI3Q_TXBD_DESA_8814A 0x0358 185 #define REG_HI4Q_TXBD_DESA_8814A 0x0360 186 #define REG_HI5Q_TXBD_DESA_8814A 0x0368 187 #define REG_HI6Q_TXBD_DESA_8814A 0x0370 188 #define REG_HI7Q_TXBD_DESA_8814A 0x0378 189 #define REG_MGQ_TXBD_NUM_8814A 0x0380 190 #define REG_RX_RXBD_NUM_8814A 0x0382 191 #define REG_VOQ_TXBD_NUM_8814A 0x0384 192 #define REG_VIQ_TXBD_NUM_8814A 0x0386 193 #define REG_BEQ_TXBD_NUM_8814A 0x0388 194 #define REG_BKQ_TXBD_NUM_8814A 0x038A 195 #define REG_HI0Q_TXBD_NUM_8814A 0x038C 196 #define REG_HI1Q_TXBD_NUM_8814A 0x038E 197 #define REG_HI2Q_TXBD_NUM_8814A 0x0390 198 #define REG_HI3Q_TXBD_NUM_8814A 0x0392 199 #define REG_HI4Q_TXBD_NUM_8814A 0x0394 200 #define REG_HI5Q_TXBD_NUM_8814A 0x0396 201 #define REG_HI6Q_TXBD_NUM_8814A 0x0398 202 #define REG_HI7Q_TXBD_NUM_8814A 0x039A 203 #define REG_TSFTIMER_HCI_8814A 0x039C 204 205 //Read Write Point 206 #define REG_VOQ_TXBD_IDX_8814A 0x03A0 207 #define REG_VIQ_TXBD_IDX_8814A 0x03A4 208 #define REG_BEQ_TXBD_IDX_8814A 0x03A8 209 #define REG_BKQ_TXBD_IDX_8814A 0x03AC 210 #define REG_MGQ_TXBD_IDX_8814A 0x03B0 211 #define REG_RXQ_TXBD_IDX_8814A 0x03B4 212 #define REG_HI0Q_TXBD_IDX_8814A 0x03B8 213 #define REG_HI1Q_TXBD_IDX_8814A 0x03BC 214 #define REG_HI2Q_TXBD_IDX_8814A 0x03C0 215 #define REG_HI3Q_TXBD_IDX_8814A 0x03C4 216 #define REG_HI4Q_TXBD_IDX_8814A 0x03C8 217 #define REG_HI5Q_TXBD_IDX_8814A 0x03CC 218 #define REG_HI6Q_TXBD_IDX_8814A 0x03D0 219 #define REG_HI7Q_TXBD_IDX_8814A 0x03D4 220 #define REG_DBG_SEL_V1_8814A 0x03D8 221 #define REG_PCIE_HRPWM1_V1_8814A 0x03D9 222 #define REG_PCIE_HCPWM1_V1_8814A 0x03DA 223 #define REG_PCIE_CTRL2_8814A 0x03DB 224 #define REG_PCIE_HRPWM2_V1_8814A 0x03DC 225 #define REG_PCIE_HCPWM2_V1_8814A 0x03DE 226 #define REG_PCIE_H2C_MSG_V1_8814A 0x03E0 227 #define REG_PCIE_C2H_MSG_V1_8814A 0x03E4 228 #define REG_DBI_WDATA_V1_8814A 0x03E8 229 #define REG_DBI_RDATA_V1_8814A 0x03EC 230 #define REG_DBI_FLAG_V1_8814A 0x03F0 231 #define REG_MDIO_V1_8814A 0x03F4 232 #define REG_PCIE_MIX_CFG_8814A 0x03F8 233 #define REG_DBG_8814A 0x03FC 234 //----------------------------------------------------- 235 // 236 // 0x0400h ~ 0x047Fh Protocol Configuration 237 // 238 //----------------------------------------------------- 239 #define REG_VOQ_INFORMATION_8814A 0x0400 240 #define REG_VIQ_INFORMATION_8814A 0x0404 241 #define REG_BEQ_INFORMATION_8814A 0x0408 242 #define REG_BKQ_INFORMATION_8814A 0x040C 243 #define REG_MGQ_INFORMATION_8814A 0x0410 244 #define REG_HGQ_INFORMATION_8814A 0x0414 245 #define REG_BCNQ_INFORMATION_8814A 0x0418 246 #define REG_TXPKT_EMPTY_8814A 0x041A 247 #define REG_CPU_MGQ_INFORMATION_8814A 0x041C 248 #define REG_FWHW_TXQ_CTRL_8814A 0x0420 249 #define REG_HWSEQ_CTRL_8814A 0x0423 250 #define REG_TXPKTBUF_BCNQ_BDNY_8814A 0x0424 251 //#define REG_MGQ_BDNY_8814A 0x0425 252 #define REG_LIFETIME_EN_8814A 0x0426 253 //#define REG_FW_FREE_TAIL_8814A 0x0427 254 #define REG_SPEC_SIFS_8814A 0x0428 255 #define REG_RETRY_LIMIT_8814A 0x042A 256 #define REG_TXBF_CTRL_8814A 0x042C 257 #define REG_DARFRC_8814A 0x0430 258 #define REG_RARFRC_8814A 0x0438 259 #define REG_RRSR_8814A 0x0440 260 #define REG_ARFR0_8814A 0x0444 261 #define REG_ARFR1_8814A 0x044C 262 #define REG_CCK_CHECK_8814A 0x0454 263 #define REG_AMPDU_MAX_TIME_8814A 0x0455 264 #define REG_TXPKTBUF_BCNQ1_BDNY_8814A 0x0456 265 #define REG_AMPDU_MAX_LENGTH_8814A 0x0458 266 #define REG_ACQ_STOP_8814A 0x045C 267 #define REG_NDPA_RATE_8814A 0x045D 268 #define REG_TX_HANG_CTRL_8814A 0x045E 269 #define REG_NDPA_OPT_CTRL_8814A 0x045F 270 #define REG_FAST_EDCA_CTRL_8814A 0x0460 271 #define REG_RD_RESP_PKT_TH_8814A 0x0463 272 #define REG_CMDQ_INFO_8814A 0x0464 273 #define REG_Q4_INFO_8814A 0x0468 274 #define REG_Q5_INFO_8814A 0x046C 275 #define REG_Q6_INFO_8814A 0x0470 276 #define REG_Q7_INFO_8814A 0x0474 277 #define REG_WMAC_LBK_BUF_HD_8814A 0x0478 278 #define REG_MGQ_PGBNDY_8814A 0x047A 279 #define REG_INIRTS_RATE_SEL_8814A 0x0480 280 #define REG_BASIC_CFEND_RATE_8814A 0x0481 281 #define REG_STBC_CFEND_RATE_8814A 0x0482 282 #define REG_DATA_SC_8814A 0x0483 283 #define REG_MACID_SLEEP3_8814A 0x0484 284 #define REG_MACID_SLEEP1_8814A 0x0488 285 #define REG_ARFR2_8814A 0x048C 286 #define REG_ARFR3_8814A 0x0494 287 #define REG_ARFR4_8814A 0x049C 288 #define REG_ARFR5_8814A 0x04A4 289 #define REG_TXRPT_START_OFFSET_8814A 0x04AC 290 #define REG_TRYING_CNT_TH_8814A 0x04B0 291 #define REG_POWER_STAGE1_8814A 0x04B4 292 #define REG_POWER_STAGE2_8814A 0x04B8 293 #define REG_SW_AMPDU_BURST_MODE_CTRL_8814A 0x04BC 294 #define REG_PKT_LIFE_TIME_8814A 0x04C0 295 #define REG_PKT_BE_BK_LIFE_TIME_8814A 0x04C2 // ?????? 296 #define REG_STBC_SETTING_8814A 0x04C4 297 #define REG_STBC_8814A 0x04C5 298 #define REG_QUEUE_CTRL_8814A 0x04C6 299 #define REG_SINGLE_AMPDU_CTRL_8814A 0x04C7 300 #define REG_PROT_MODE_CTRL_8814A 0x04C8 301 #define REG_MAX_AGGR_NUM_8814A 0x04CA 302 #define REG_RTS_MAX_AGGR_NUM_8814A 0x04CB 303 #define REG_BAR_MODE_CTRL_8814A 0x04CC 304 #define REG_RA_TRY_RATE_AGG_LMT_8814A 0x04CF 305 #define REG_MACID_SLEEP2_8814A 0x04D0 306 #define REG_MACID_SLEEP0_8814A 0x04D4 307 #define REG_HW_SEQ0_8814A 0x04D8 308 #define REG_HW_SEQ1_8814A 0x04DA 309 #define REG_HW_SEQ2_8814A 0x04DC 310 #define REG_HW_SEQ3_8814A 0x04DE 311 #define REG_NULL_PKT_STATUS_8814A 0x04E0 312 #define REG_PTCL_ERR_STATUS_8814A 0x04E2 313 #define REG_DROP_PKT_NUM_8814A 0x04EC 314 #define REG_PTCL_TX_RPT_8814A 0x04F0 315 #define REG_Dummy_8814A 0x04FC 316 317 318 //----------------------------------------------------- 319 // 320 // 0x0500h ~ 0x05FFh EDCA Configuration 321 // 322 //----------------------------------------------------- 323 #define REG_EDCA_VO_PARAM_8814A 0x0500 324 #define REG_EDCA_VI_PARAM_8814A 0x0504 325 #define REG_EDCA_BE_PARAM_8814A 0x0508 326 #define REG_EDCA_BK_PARAM_8814A 0x050C 327 #define REG_BCNTCFG_8814A 0x0510 328 #define REG_PIFS_8814A 0x0512 329 #define REG_RDG_PIFS_8814A 0x0513 330 #define REG_SIFS_CTX_8814A 0x0514 331 #define REG_SIFS_TRX_8814A 0x0516 332 #define REG_AGGR_BREAK_TIME_8814A 0x051A 333 #define REG_SLOT_8814A 0x051B 334 #define REG_TX_PTCL_CTRL_8814A 0x0520 335 #define REG_TXPAUSE_8814A 0x0522 336 #define REG_DIS_TXREQ_CLR_8814A 0x0523 337 #define REG_RD_CTRL_8814A 0x0524 338 // 339 // Format for offset 540h-542h: 340 // [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 341 // [7:4]: Reserved. 342 // [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 343 // [23:20]: Reserved 344 // Description: 345 // | 346 // |<--Setup--|--Hold------------>| 347 // --------------|---------------------- 348 // | 349 // TBTT 350 // Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 351 // Described by Designer Tim and Bruce, 2011-01-14. 352 // 353 #define REG_TBTT_PROHIBIT_8814A 0x0540 354 #define REG_RD_NAV_NXT_8814A 0x0544 355 #define REG_NAV_PROT_LEN_8814A 0x0546 356 #define REG_BCN_CTRL_8814A 0x0550 357 #define REG_BCN_CTRL_1_8814A 0x0551 358 #define REG_MBID_NUM_8814A 0x0552 359 #define REG_DUAL_TSF_RST_8814A 0x0553 360 #define REG_MBSSID_BCN_SPACE_8814A 0x0554 361 #define REG_DRVERLYINT_8814A 0x0558 362 #define REG_BCNDMATIM_8814A 0x0559 363 #define REG_ATIMWND_8814A 0x055A 364 #define REG_USTIME_TSF_8814A 0x055C 365 #define REG_BCN_MAX_ERR_8814A 0x055D 366 #define REG_RXTSF_OFFSET_CCK_8814A 0x055E 367 #define REG_RXTSF_OFFSET_OFDM_8814A 0x055F 368 #define REG_TSFTR_8814A 0x0560 369 #define REG_CTWND_8814A 0x0572 370 #define REG_SECONDARY_CCA_CTRL_8814A 0x0577 // ?????? 371 #define REG_PSTIMER_8814A 0x0580 372 #define REG_TIMER0_8814A 0x0584 373 #define REG_TIMER1_8814A 0x0588 374 #define REG_BCN_PREDL_ITV_8814A 0x058F //Pre download beacon interval 375 #define REG_ACMHWCTRL_8814A 0x05C0 376 377 //----------------------------------------------------- 378 // 379 // 0x0600h ~ 0x07FFh WMAC Configuration 380 // 381 //----------------------------------------------------- 382 #define REG_MAC_CR_8814A 0x0600 383 #define REG_TCR_8814A 0x0604 384 #define REG_RCR_8814A 0x0608 385 #define REG_RX_PKT_LIMIT_8814A 0x060C 386 #define REG_RX_DLK_TIME_8814A 0x060D 387 #define REG_RX_DRVINFO_SZ_8814A 0x060F 388 389 #define REG_MACID_8814A 0x0610 390 #define REG_BSSID_8814A 0x0618 391 #define REG_MAR_8814A 0x0620 392 #define REG_MBIDCAMCFG_8814A 0x0628 393 394 #define REG_USTIME_EDCA_8814A 0x0638 395 #define REG_MAC_SPEC_SIFS_8814A 0x063A 396 #define REG_RESP_SIFP_CCK_8814A 0x063C 397 #define REG_RESP_SIFS_OFDM_8814A 0x063E 398 #define REG_ACKTO_8814A 0x0640 399 #define REG_CTS2TO_8814A 0x0641 400 #define REG_EIFS_8814A 0x0642 401 402 #define REG_NAV_UPPER_8814A 0x0652 // unit of 128 403 #define REG_TRXPTCL_CTL_8814A 0x0668 404 405 // Security 406 #define REG_CAMCMD_8814A 0x0670 407 #define REG_CAMWRITE_8814A 0x0674 408 #define REG_CAMREAD_8814A 0x0678 409 #define REG_CAMDBG_8814A 0x067C 410 #define REG_SECCFG_8814A 0x0680 411 412 // Power 413 #define REG_WOW_CTRL_8814A 0x0690 414 #define REG_PS_RX_INFO_8814A 0x0692 415 #define REG_UAPSD_TID_8814A 0x0693 416 #define REG_WKFMCAM_NUM_8814A 0x0698 417 #define REG_RXFLTMAP0_8814A 0x06A0 418 #define REG_RXFLTMAP1_8814A 0x06A2 419 #define REG_RXFLTMAP2_8814A 0x06A4 420 #define REG_BCN_PSR_RPT_8814A 0x06A8 421 #define REG_BT_COEX_TABLE_8814A 0x06C0 422 #define REG_TX_DATA_RSP_RATE_8814A 0x06DE 423 #define REG_ASSOCIATED_BFMER0_INFO_8814A 0x06E4 424 #define REG_ASSOCIATED_BFMER1_INFO_8814A 0x06EC 425 #define REG_CSI_RPT_PARAM_BW20_8814A 0x06F4 426 #define REG_CSI_RPT_PARAM_BW40_8814A 0x06F8 427 #define REG_CSI_RPT_PARAM_BW80_8814A 0x06FC 428 429 // Hardware Port 2 430 #define REG_MACID1_8814A 0x0700 431 #define REG_BSSID1_8814A 0x0708 432 // Hardware Port 3 433 #define REG_MACID2_8814A 0x1620 434 #define REG_BSSID2_8814A 0x1628 435 // Hardware Port 4 436 #define REG_MACID3_8814A 0x1630 437 #define REG_BSSID3_8814A 0x1638 438 // Hardware Port 5 439 #define REG_MACID4_8814A 0x1640 440 #define REG_BSSID4_8814A 0x1648 441 442 #define REG_ASSOCIATED_BFMEE_SEL_8814A 0x0714 443 #define REG_SND_PTCL_CTRL_8814A 0x0718 444 #define REG_IQ_DUMP_8814A 0x07C0 445 446 /**** page 19 ****/ 447 //TX BeamForming 448 #define REG_BB_TXBF_ANT_SET_BF1 0x19ac 449 #define REG_BB_TXBF_ANT_SET_BF0 0x19b4 450 451 // 0x1200h ~ 0x12FFh DDMA CTRL 452 // 453 //----------------------------------------------------- 454 #define REG_DDMA_CH0SA 0x1200 455 #define REG_DDMA_CH0DA 0x1204 456 #define REG_DDMA_CH0CTRL 0x1208 457 #define REG_DDMA_CH1SA 0x1210 458 #define REG_DDMA_CH1DA 0x1214 459 #define REG_DDMA_CH1CTRL 0x1218 460 #define REG_DDMA_CH2SA 0x1220 461 #define REG_DDMA_CH2DA 0x1224 462 #define REG_DDMA_CH2CTRL 0x1228 463 #define REG_DDMA_CH3SA 0x1230 464 #define REG_DDMA_CH3DA 0x1234 465 #define REG_DDMA_CH3CTRL 0x1238 466 #define REG_DDMA_CH4SA 0x1240 467 #define REG_DDMA_CH4DA 0x1244 468 #define REG_DDMA_CH4CTRL 0x1248 469 #define REG_DDMA_CH5SA 0x1250 470 #define REG_DDMA_CH5DA 0x1254 471 #define REG_DDMA_CH5CTRL 0x1258 472 #define REG_DDMA_INT_MSK 0x12E0 473 #define REG_DDMA_CHSTATUS 0x12E8 474 #define REG_DDMA_CHKSUM 0x12F0 475 #define REG_DDMA_MONITER 0x12FC 476 477 #define DDMA_LEN_MASK 0x0001FFFF 478 #define FW_CHKSUM_DUMMY_SZ 8 479 #define DDMA_CH_CHKSUM_CNT BIT(24) 480 #define DDMA_RST_CHKSUM_STS BIT(25) 481 #define DDMA_MODE_BLOCK_CPU BIT(26) 482 #define DDMA_CHKSUM_FAIL BIT(27) 483 #define DDMA_DA_W_DISABLE BIT(28) 484 #define DDMA_CHKSUM_EN BIT(29) 485 #define DDMA_CH_OWN BIT(31) 486 487 488 //3081 FWDL 489 #define FWDL_EN BIT0 490 #define IMEM_BOOT_DL_RDY BIT1 491 #define IMEM_BOOT_CHKSUM_FAIL BIT2 492 #define IMEM_DL_RDY BIT3 493 #define IMEM_CHKSUM_OK BIT4 494 #define DMEM_DL_RDY BIT5 495 #define DMEM_CHKSUM_OK BIT6 496 #define EMEM_DL_RDY BIT7 497 #define EMEM_CHKSUM_FAIL BIT8 498 #define EMEM_TXBUF_DL_RDY BIT9 499 #define EMEM_TXBUF_CHKSUM_FAIL BIT10 500 #define CPU_CLK_SWITCH_BUSY BIT11 501 #define CPU_CLK_SEL (BIT12|BIT13) 502 #define FWDL_OK BIT14 503 #define FW_INIT_RDY BIT15 504 #define R_EN_BOOT_FLASH BIT20 505 506 #define OCPBASE_IMEM_3081 0x00000000 507 #define OCPBASE_DMEM_3081 0x00200000 508 #define OCPBASE_RPTBUF_3081 0x18660000 509 #define OCPBASE_RXBUF2_3081 0x18680000 510 #define OCPBASE_RXBUF_3081 0x18700000 511 #define OCPBASE_TXBUF_3081 0x18780000 512 513 514 #define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448 515 #define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C 516 517 518 //----------------------------------------------------- 519 // 520 521 522 //----------------------------------------------------- 523 // 524 // Redifine 8192C register definition for compatibility 525 // 526 //----------------------------------------------------- 527 528 // TODO: use these definition when using REG_xxx naming rule. 529 // NOTE: DO NOT Remove these definition. Use later. 530 #define EFUSE_CTRL_8814A REG_EFUSE_CTRL_8814A // E-Fuse Control. 531 #define EFUSE_TEST_8814A REG_LDO_EFUSE_CTRL_8814A // E-Fuse Test. 532 #define MSR_8814A (REG_CR_8814A + 2) // Media Status register 533 #define ISR_8814A REG_HISR0_8814A 534 #define TSFR_8814A REG_TSFTR_8814A // Timing Sync Function Timer Register. 535 536 #define PBP_8814A REG_PBP_8814A 537 538 // Redifine MACID register, to compatible prior ICs. 539 #define IDR0_8814A REG_MACID_8814A // MAC ID Register, Offset 0x0050-0x0053 540 #define IDR4_8814A (REG_MACID_8814A + 4) // MAC ID Register, Offset 0x0054-0x0055 541 542 543 // 544 // 9. Security Control Registers (Offset: ) 545 // 546 #define RWCAM_8814A REG_CAMCMD_8814A //IN 8190 Data Sheet is called CAMcmd 547 #define WCAMI_8814A REG_CAMWRITE_8814A // Software write CAM input content 548 #define RCAMO_8814A REG_CAMREAD_8814A // Software read/write CAM config 549 #define CAMDBG_8814A REG_CAMDBG_8814A 550 #define SECR_8814A REG_SECCFG_8814A //Security Configuration Register 551 552 553 //---------------------------------------------------------------------------- 554 // 8195 IMR/ISR bits (offset 0xB0, 8bits) 555 //---------------------------------------------------------------------------- 556 #define IMR_DISABLED_8814A 0 557 // IMR DW0(0x00B0-00B3) Bit 0-31 558 #define IMR_TIMER2_8814A BIT31 // Timeout interrupt 2 559 #define IMR_TIMER1_8814A BIT30 // Timeout interrupt 1 560 #define IMR_PSTIMEOUT_8814A BIT29 // Power Save Time Out Interrupt 561 #define IMR_GTINT4_8814A BIT28 // When GTIMER4 expires, this bit is set to 1 562 #define IMR_GTINT3_8814A BIT27 // When GTIMER3 expires, this bit is set to 1 563 #define IMR_TXBCN0ERR_8814A BIT26 // Transmit Beacon0 Error 564 #define IMR_TXBCN0OK_8814A BIT25 // Transmit Beacon0 OK 565 #define IMR_TSF_BIT32_TOGGLE_8814A BIT24 // TSF Timer BIT32 toggle indication interrupt 566 #define IMR_BCNDMAINT0_8814A BIT20 // Beacon DMA Interrupt 0 567 #define IMR_BCNDERR0_8814A BIT16 // Beacon Queue DMA OK0 568 #define IMR_HSISR_IND_ON_INT_8814A BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) 569 #define IMR_BCNDMAINT_E_8814A BIT14 // Beacon DMA Interrupt Extension for Win7 570 #define IMR_ATIMEND_8814A BIT12 // CTWidnow End or ATIM Window End 571 #define IMR_C2HCMD_8814A BIT10 // CPU to Host Command INT Status, Write 1 clear 572 #define IMR_CPWM2_8814A BIT9 // CPU power Mode exchange INT Status, Write 1 clear 573 #define IMR_CPWM_8814A BIT8 // CPU power Mode exchange INT Status, Write 1 clear 574 #define IMR_HIGHDOK_8814A BIT7 // High Queue DMA OK 575 #define IMR_MGNTDOK_8814A BIT6 // Management Queue DMA OK 576 #define IMR_BKDOK_8814A BIT5 // AC_BK DMA OK 577 #define IMR_BEDOK_8814A BIT4 // AC_BE DMA OK 578 #define IMR_VIDOK_8814A BIT3 // AC_VI DMA OK 579 #define IMR_VODOK_8814A BIT2 // AC_VO DMA OK 580 #define IMR_RDU_8814A BIT1 // Rx Descriptor Unavailable 581 #define IMR_ROK_8814A BIT0 // Receive DMA OK 582 583 // IMR DW1(0x00B4-00B7) Bit 0-31 584 #define IMR_MCUERR_8814A BIT28 // Beacon DMA Interrupt 7 585 #define IMR_BCNDMAINT7_8814A BIT27 // Beacon DMA Interrupt 7 586 #define IMR_BCNDMAINT6_8814A BIT26 // Beacon DMA Interrupt 6 587 #define IMR_BCNDMAINT5_8814A BIT25 // Beacon DMA Interrupt 5 588 #define IMR_BCNDMAINT4_8814A BIT24 // Beacon DMA Interrupt 4 589 #define IMR_BCNDMAINT3_8814A BIT23 // Beacon DMA Interrupt 3 590 #define IMR_BCNDMAINT2_8814A BIT22 // Beacon DMA Interrupt 2 591 #define IMR_BCNDMAINT1_8814A BIT21 // Beacon DMA Interrupt 1 592 #define IMR_BCNDOK7_8814A BIT20 // Beacon Queue DMA OK Interrup 7 593 #define IMR_BCNDOK6_8814A BIT19 // Beacon Queue DMA OK Interrup 6 594 #define IMR_BCNDOK5_8814A BIT18 // Beacon Queue DMA OK Interrup 5 595 #define IMR_BCNDOK4_8814A BIT17 // Beacon Queue DMA OK Interrup 4 596 #define IMR_BCNDOK3_8814A BIT16 // Beacon Queue DMA OK Interrup 3 597 #define IMR_BCNDOK2_8814A BIT15 // Beacon Queue DMA OK Interrup 2 598 #define IMR_BCNDOK1_8814A BIT14 // Beacon Queue DMA OK Interrup 1 599 #define IMR_ATIMEND_E_8814A BIT13 // ATIM Window End Extension for Win7 600 #define IMR_TXERR_8814A BIT11 // Tx Error Flag Interrupt Status, write 1 clear. 601 #define IMR_RXERR_8814A BIT10 // Rx Error Flag INT Status, Write 1 clear 602 #define IMR_TXFOVW_8814A BIT9 // Transmit FIFO Overflow 603 #define IMR_RXFOVW_8814A BIT8 // Receive FIFO Overflow 604 605 606 #ifdef CONFIG_PCI_HCI 607 #define IMR_TX_MASK (IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A) 608 609 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A) 610 611 #define RT_AC_INT_MASKS (IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A) 612 #endif 613 614 615 /*=================================================================== 616 ===================================================================== 617 Here the register defines are for 92C. When the define is as same with 92C, 618 we will use the 92C's define for the consistency 619 So the following defines for 92C is not entire!!!!!! 620 ===================================================================== 621 =====================================================================*/ 622 623 624 //----------------------------------------------------- 625 // 626 // 0xFE00h ~ 0xFE55h USB Configuration 627 // 628 //----------------------------------------------------- 629 630 //2 Special Option 631 #define USB_AGG_EN_8814A BIT(7) 632 #define REG_USB_HRPWM_U3 0xF052 633 634 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A 2048-1 //20130415 KaiYuan add for 8814 635 636 #define MACID_NUM_8814A 128 637 #define SEC_CAM_ENT_NUM_8814A 64 638 #define NSS_NUM_8814A 3 639 #define BAND_CAP_8814A (BAND_CAP_2G | BAND_CAP_5G) 640 #define BW_CAP_8814A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M) 641 #define PROTO_CAP_8814A (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N|PROTO_CAP_11AC) 642 643 #endif //__RTL8814A_SPEC_H__ 644