1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19 #ifndef __RTL8192E_SPEC_H__ 20 #define __RTL8192E_SPEC_H__ 21 22 #include <drv_conf.h> 23 24 25 //============================================================ 26 // 8192E Regsiter offset definition 27 //============================================================ 28 29 //============================================================ 30 // 31 //============================================================ 32 33 //----------------------------------------------------- 34 // 35 // 0x0000h ~ 0x00FFh System Configuration 36 // 37 //----------------------------------------------------- 38 #define REG_SYS_SWR_CTRL1_8192E 0x0010 // 1 Byte 39 #define REG_SYS_SWR_CTRL2_8192E 0x0014 // 1 Byte 40 #define REG_AFE_CTRL1_8192E 0x0024 41 #define REG_AFE_CTRL2_8192E 0x0028 42 #define REG_AFE_CTRL3_8192E 0x002c 43 44 #define REG_PAD_CTRL1_8192E 0x0064 45 #define REG_SDIO_CTRL_8192E 0x0070 46 #define REG_OPT_CTRL_8192E 0x0074 47 #define REG_RF_B_CTRL_8192E 0x0076 48 #define REG_AFE_CTRL4_8192E 0x0078 49 #define REG_LDO_SWR_CTRL 0x007C 50 #define REG_FW_DRV_MSG_8192E 0x0088 51 #define REG_HMEBOX_E2_E3_8192E 0x008C 52 #define REG_HIMR0_8192E 0x00B0 53 #define REG_HISR0_8192E 0x00B4 54 #define REG_HIMR1_8192E 0x00B8 55 #define REG_HISR1_8192E 0x00BC 56 57 #define REG_SYS_CFG1_8192E 0x00F0 58 #define REG_SYS_CFG2_8192E 0x00FC 59 //----------------------------------------------------- 60 // 61 // 0x0100h ~ 0x01FFh MACTOP General Configuration 62 // 63 //----------------------------------------------------- 64 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 65 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 66 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 67 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 68 69 #define REG_RSVD3_8192E 0x0168 70 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 71 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 72 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 73 74 #define REG_HMEBOX_EXT0_8192E 0x01F0 75 #define REG_HMEBOX_EXT1_8192E 0x01F4 76 #define REG_HMEBOX_EXT2_8192E 0x01F8 77 #define REG_HMEBOX_EXT3_8192E 0x01FC 78 79 //----------------------------------------------------- 80 // 81 // 0x0200h ~ 0x027Fh TXDMA Configuration 82 // 83 //----------------------------------------------------- 84 #define REG_DWBCN0_CTRL 0x0208 85 #define REG_DWBCN1_CTRL 0x0228 86 87 //----------------------------------------------------- 88 // 89 // 0x0280h ~ 0x02FFh RXDMA Configuration 90 // 91 //----------------------------------------------------- 92 #define REG_RXDMA_8192E 0x0290 93 #define REG_EARLY_MODE_CONTROL_8192E 0x02BC 94 95 #define REG_RSVD5_8192E 0x02F0 96 #define REG_RSVD6_8192E 0x02F4 97 #define REG_RSVD7_8192E 0x02F8 98 #define REG_RSVD8_8192E 0x02FC 99 100 //----------------------------------------------------- 101 // 102 // 0x0300h ~ 0x03FFh PCIe 103 // 104 //----------------------------------------------------- 105 #define REG_PCIE_CTRL_REG_8192E 0x0300 106 #define REG_INT_MIG_8192E 0x0304 // Interrupt Migration 107 #define REG_BCNQ_TXBD_DESA_8192E 0x0308 // TX Beacon Descriptor Address 108 #define REG_MGQ_TXBD_DESA_8192E 0x0310 // TX Manage Queue Descriptor Address 109 #define REG_VOQ_TXBD_DESA_8192E 0x0318 // TX VO Queue Descriptor Address 110 #define REG_VIQ_TXBD_DESA_8192E 0x0320 // TX VI Queue Descriptor Address 111 #define REG_BEQ_TXBD_DESA_8192E 0x0328 // TX BE Queue Descriptor Address 112 #define REG_BKQ_TXBD_DESA_8192E 0x0330 // TX BK Queue Descriptor Address 113 #define REG_RXQ_RXBD_DESA_8192E 0x0338 // RX Queue Descriptor Address 114 #define REG_HI0Q_TXBD_DESA_8192E 0x0340 115 #define REG_HI1Q_TXBD_DESA_8192E 0x0348 116 #define REG_HI2Q_TXBD_DESA_8192E 0x0350 117 #define REG_HI3Q_TXBD_DESA_8192E 0x0358 118 #define REG_HI4Q_TXBD_DESA_8192E 0x0360 119 #define REG_HI5Q_TXBD_DESA_8192E 0x0368 120 #define REG_HI6Q_TXBD_DESA_8192E 0x0370 121 #define REG_HI7Q_TXBD_DESA_8192E 0x0378 122 #define REG_MGQ_TXBD_NUM_8192E 0x0380 123 #define REG_RX_RXBD_NUM_8192E 0x0382 124 #define REG_VOQ_TXBD_NUM_8192E 0x0384 125 #define REG_VIQ_TXBD_NUM_8192E 0x0386 126 #define REG_BEQ_TXBD_NUM_8192E 0x0388 127 #define REG_BKQ_TXBD_NUM_8192E 0x038A 128 #define REG_HI0Q_TXBD_NUM_8192E 0x038C 129 #define REG_HI1Q_TXBD_NUM_8192E 0x038E 130 #define REG_HI2Q_TXBD_NUM_8192E 0x0390 131 #define REG_HI3Q_TXBD_NUM_8192E 0x0392 132 #define REG_HI4Q_TXBD_NUM_8192E 0x0394 133 #define REG_HI5Q_TXBD_NUM_8192E 0x0396 134 #define REG_HI6Q_TXBD_NUM_8192E 0x0398 135 #define REG_HI7Q_TXBD_NUM_8192E 0x039A 136 #define REG_TSFTIMER_HCI_8192E 0x039C 137 138 //Read Write Point 139 #define REG_VOQ_TXBD_IDX_8192E 0x03A0 140 #define REG_VIQ_TXBD_IDX_8192E 0x03A4 141 #define REG_BEQ_TXBD_IDX_8192E 0x03A8 142 #define REG_BKQ_TXBD_IDX_8192E 0x03AC 143 #define REG_MGQ_TXBD_IDX_8192E 0x03B0 144 #define REG_RXQ_TXBD_IDX_8192E 0x03B4 145 #define REG_HI0Q_TXBD_IDX_8192E 0x03B8 146 #define REG_HI1Q_TXBD_IDX_8192E 0x03BC 147 #define REG_HI2Q_TXBD_IDX_8192E 0x03C0 148 #define REG_HI3Q_TXBD_IDX_8192E 0x03C4 149 #define REG_HI4Q_TXBD_IDX_8192E 0x03C8 150 #define REG_HI5Q_TXBD_IDX_8192E 0x03CC 151 #define REG_HI6Q_TXBD_IDX_8192E 0x03D0 152 #define REG_HI7Q_TXBD_IDX_8192E 0x03D4 153 154 #define REG_PCIE_HCPWM_8192EE 0x03D8 // ?????? 155 #define REG_PCIE_HRPWM_8192EE 0x03DC //PCIe RPWM // ?????? 156 #define REG_DBI_WDATA_V1_8192E 0x03E8 157 #define REG_DBI_RDATA_V1_8192E 0x03EC 158 #define REG_DBI_FLAG_V1_8192E 0x03F0 159 #define REG_MDIO_V1_8192E 0x3F4 160 #define REG_PCIE_MIX_CFG_8192E 0x3F8 161 162 //----------------------------------------------------- 163 // 164 // 0x0400h ~ 0x047Fh Protocol Configuration 165 // 166 //----------------------------------------------------- 167 #define REG_TXBF_CTRL_8192E 0x042C 168 #define REG_ARFR0_8192E 0x0444 169 #define REG_ARFR1_8192E 0x044C 170 #define REG_CCK_CHECK_8192E 0x0454 171 #define REG_AMPDU_MAX_TIME_8192E 0x0456 172 #define REG_BCNQ1_BDNY_8192E 0x0457 173 174 #define REG_AMPDU_MAX_LENGTH_8192E 0x0458 175 #define REG_WMAC_LBK_BUF_HD_8192E 0x045D 176 #define REG_NDPA_OPT_CTRL_8192E 0x045F 177 #define REG_DATA_SC_8192E 0x0483 178 #ifdef CONFIG_WOWLAN 179 #define REG_TXPKTBUF_IV_LOW 0x0484 180 #define REG_TXPKTBUF_IV_HIGH 0x0488 181 #endif 182 #define REG_ARFR2_8192E 0x048C 183 #define REG_ARFR3_8192E 0x0494 184 #define REG_TXRPT_START_OFFSET 0x04AC 185 #define REG_AMPDU_BURST_MODE_8192E 0x04BC 186 #define REG_HT_SINGLE_AMPDU_8192E 0x04C7 187 #define REG_MACID_PKT_DROP0_8192E 0x04D0 188 189 //----------------------------------------------------- 190 // 191 // 0x0500h ~ 0x05FFh EDCA Configuration 192 // 193 //----------------------------------------------------- 194 #define REG_CTWND_8192E 0x0572 195 #define REG_SECONDARY_CCA_CTRL_8192E 0x0577 196 #define REG_SCH_TXCMD_8192E 0x05F8 197 198 //----------------------------------------------------- 199 // 200 // 0x0600h ~ 0x07FFh WMAC Configuration 201 // 202 //----------------------------------------------------- 203 #define REG_MAC_CR_8192E 0x0600 204 205 #define REG_MAC_TX_SM_STATE_8192E 0x06B4 206 207 // Power 208 #define REG_BFMER0_INFO_8192E 0x06E4 209 #define REG_BFMER1_INFO_8192E 0x06EC 210 #define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 211 #define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 212 #define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC 213 214 // Hardware Port 2 215 #define REG_BFMEE_SEL_8192E 0x0714 216 #define REG_SND_PTCL_CTRL_8192E 0x0718 217 218 219 //----------------------------------------------------- 220 // 221 // Redifine register definition for compatibility 222 // 223 //----------------------------------------------------- 224 225 // TODO: use these definition when using REG_xxx naming rule. 226 // NOTE: DO NOT Remove these definition. Use later. 227 #define ISR_8192E REG_HISR0_8192E 228 229 //---------------------------------------------------------------------------- 230 // 8192E IMR/ISR bits (offset 0xB0, 8bits) 231 //---------------------------------------------------------------------------- 232 #define IMR_DISABLED_8192E 0 233 // IMR DW0(0x00B0-00B3) Bit 0-31 234 #define IMR_TIMER2_8192E BIT31 // Timeout interrupt 2 235 #define IMR_TIMER1_8192E BIT30 // Timeout interrupt 1 236 #define IMR_PSTIMEOUT_8192E BIT29 // Power Save Time Out Interrupt 237 #define IMR_GTINT4_8192E BIT28 // When GTIMER4 expires, this bit is set to 1 238 #define IMR_GTINT3_8192E BIT27 // When GTIMER3 expires, this bit is set to 1 239 #define IMR_TXBCN0ERR_8192E BIT26 // Transmit Beacon0 Error 240 #define IMR_TXBCN0OK_8192E BIT25 // Transmit Beacon0 OK 241 #define IMR_TSF_BIT32_TOGGLE_8192E BIT24 // TSF Timer BIT32 toggle indication interrupt 242 #define IMR_BCNDMAINT0_8192E BIT20 // Beacon DMA Interrupt 0 243 #define IMR_BCNDERR0_8192E BIT16 // Beacon Queue DMA OK0 244 #define IMR_HSISR_IND_ON_INT_8192E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) 245 #define IMR_BCNDMAINT_E_8192E BIT14 // Beacon DMA Interrupt Extension for Win7 246 #define IMR_ATIMEND_8192E BIT12 // CTWidnow End or ATIM Window End 247 #define IMR_C2HCMD_8192E BIT10 // CPU to Host Command INT Status, Write 1 clear 248 #define IMR_CPWM2_8192E BIT9 // CPU power Mode exchange INT Status, Write 1 clear 249 #define IMR_CPWM_8192E BIT8 // CPU power Mode exchange INT Status, Write 1 clear 250 #define IMR_HIGHDOK_8192E BIT7 // High Queue DMA OK 251 #define IMR_MGNTDOK_8192E BIT6 // Management Queue DMA OK 252 #define IMR_BKDOK_8192E BIT5 // AC_BK DMA OK 253 #define IMR_BEDOK_8192E BIT4 // AC_BE DMA OK 254 #define IMR_VIDOK_8192E BIT3 // AC_VI DMA OK 255 #define IMR_VODOK_8192E BIT2 // AC_VO DMA OK 256 #define IMR_RDU_8192E BIT1 // Rx Descriptor Unavailable 257 #define IMR_ROK_8192E BIT0 // Receive DMA OK 258 259 // IMR DW1(0x00B4-00B7) Bit 0-31 260 #define IMR_BCNDMAINT7_8192E BIT27 // Beacon DMA Interrupt 7 261 #define IMR_BCNDMAINT6_8192E BIT26 // Beacon DMA Interrupt 6 262 #define IMR_BCNDMAINT5_8192E BIT25 // Beacon DMA Interrupt 5 263 #define IMR_BCNDMAINT4_8192E BIT24 // Beacon DMA Interrupt 4 264 #define IMR_BCNDMAINT3_8192E BIT23 // Beacon DMA Interrupt 3 265 #define IMR_BCNDMAINT2_8192E BIT22 // Beacon DMA Interrupt 2 266 #define IMR_BCNDMAINT1_8192E BIT21 // Beacon DMA Interrupt 1 267 #define IMR_BCNDOK7_8192E BIT20 // Beacon Queue DMA OK Interrup 7 268 #define IMR_BCNDOK6_8192E BIT19 // Beacon Queue DMA OK Interrup 6 269 #define IMR_BCNDOK5_8192E BIT18 // Beacon Queue DMA OK Interrup 5 270 #define IMR_BCNDOK4_8192E BIT17 // Beacon Queue DMA OK Interrup 4 271 #define IMR_BCNDOK3_8192E BIT16 // Beacon Queue DMA OK Interrup 3 272 #define IMR_BCNDOK2_8192E BIT15 // Beacon Queue DMA OK Interrup 2 273 #define IMR_BCNDOK1_8192E BIT14 // Beacon Queue DMA OK Interrup 1 274 #define IMR_ATIMEND_E_8192E BIT13 // ATIM Window End Extension for Win7 275 #define IMR_TXERR_8192E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. 276 #define IMR_RXERR_8192E BIT10 // Rx Error Flag INT Status, Write 1 clear 277 #define IMR_TXFOVW_8192E BIT9 // Transmit FIFO Overflow 278 #define IMR_RXFOVW_8192E BIT8 // Receive FIFO Overflow 279 280 //---------------------------------------------------------------------------- 281 // 8192E Auto LLT bits (offset 0x224, 8bits) 282 //---------------------------------------------------------------------------- 283 //224 REG_AUTO_LLT 284 // move to hal_com_reg.h 285 286 //---------------------------------------------------------------------------- 287 // 8192E Auto LLT bits (offset 0x290, 32bits) 288 //---------------------------------------------------------------------------- 289 #define BIT_DMA_MODE BIT1 290 #define BIT_USB_RXDMA_AGG_EN BIT31 291 292 //---------------------------------------------------------------------------- 293 // 8192E REG_SYS_CFG1 (offset 0xF0, 32bits) 294 //---------------------------------------------------------------------------- 295 #define BIT_SPSLDO_SEL BIT24 296 297 298 //---------------------------------------------------------------------------- 299 // 8192E REG_CCK_CHECK (offset 0x454, 8bits) 300 //---------------------------------------------------------------------------- 301 #define BIT_BCN_PORT_SEL BIT5 302 303 //============================================================================ 304 // Regsiter Bit and Content definition 305 //============================================================================ 306 307 //2 ACMHWCTRL 0x05C0 308 #define AcmHw_HwEn_8192E BIT(0) 309 #define AcmHw_VoqEn_8192E BIT(1) 310 #define AcmHw_ViqEn_8192E BIT(2) 311 #define AcmHw_BeqEn_8192E BIT(3) 312 #define AcmHw_VoqStatus_8192E BIT(5) 313 #define AcmHw_ViqStatus_8192E BIT(6) 314 #define AcmHw_BeqStatus_8192E BIT(7) 315 316 //======================================================== 317 // General definitions 318 //======================================================== 319 320 #define MACID_NUM_8192E 128 321 #define SEC_CAM_ENT_NUM_8192E 64 322 #define NSS_NUM_8192E 2 323 #define BAND_CAP_8192E (BAND_CAP_2G) 324 #define BW_CAP_8192E (BW_CAP_20M | BW_CAP_40M) 325 #define PROTO_CAP_8192E (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N) 326 327 #endif //__RTL8192E_SPEC_H__ 328 329