1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 22 #ifndef __HALDMOUTSRC_H__ 23 #define __HALDMOUTSRC_H__ 24 25 //============================================================ 26 // include files 27 //============================================================ 28 #include "phydm_pre_define.h" 29 #include "phydm_dig.h" 30 #include "phydm_edcaturbocheck.h" 31 #include "phydm_pathdiv.h" 32 #include "phydm_antdiv.h" 33 #include "phydm_antdect.h" 34 #include "phydm_dynamicbbpowersaving.h" 35 #include "phydm_rainfo.h" 36 #include "phydm_dynamictxpower.h" 37 #include "phydm_cfotracking.h" 38 #include "phydm_acs.h" 39 #include "phydm_adaptivity.h" 40 41 42 #if (RTL8814A_SUPPORT == 1) 43 #include "rtl8814a/phydm_iqk_8814a.h" 44 #endif 45 46 47 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 48 #include "halphyrf_ap.h" 49 #include "phydm_powertracking_ap.h" 50 #endif 51 52 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 53 #include "phydm_beamforming.h" 54 #include "phydm_noisemonitor.h" 55 #include "halphyrf_ce.h" 56 #include "phydm_powertracking_ce.h" 57 #endif 58 59 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 60 #include "phydm_beamforming.h" 61 #include "phydm_rxhp.h" 62 #include "halphyrf_win.h" 63 #include "phydm_powertracking_win.h" 64 #endif 65 66 //============================================================ 67 // Definition 68 //============================================================ 69 // 70 // 2011/09/22 MH Define all team supprt ability. 71 // 72 73 // 74 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. 75 // 76 //#define DM_ODM_SUPPORT_AP 0 77 //#define DM_ODM_SUPPORT_ADSL 0 78 //#define DM_ODM_SUPPORT_CE 0 79 //#define DM_ODM_SUPPORT_MP 1 80 81 // 82 // 2011/09/28 MH Define ODM SW team support flag. 83 // 84 85 //For SW AntDiv, PathDiv, 8192C AntDiv joint use 86 #define TP_MODE 0 87 #define RSSI_MODE 1 88 89 #define TRAFFIC_LOW 0 90 #define TRAFFIC_HIGH 1 91 #define TRAFFIC_ULTRA_LOW 2 92 #define TRAFFIC_MID 3 93 94 95 #define NONE 0 96 97 98 99 100 //8723A High Power IGI Setting 101 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 102 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 103 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 104 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 105 106 107 //============================================================ 108 // structure and define 109 //============================================================ 110 111 // 112 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. 113 // We need to remove to other position??? 114 // 115 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 116 typedef struct rtl8192cd_priv { 117 u1Byte temp; 118 119 }rtl8192cd_priv, *prtl8192cd_priv; 120 #endif 121 122 123 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 124 typedef struct _ADAPTER{ 125 u1Byte temp; 126 #ifdef AP_BUILD_WORKAROUND 127 HAL_DATA_TYPE* temp2; 128 prtl8192cd_priv priv; 129 #endif 130 }ADAPTER, *PADAPTER; 131 #endif 132 133 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 134 135 typedef struct _WLAN_STA{ 136 u1Byte temp; 137 } WLAN_STA, *PRT_WLAN_STA; 138 139 #endif 140 141 typedef struct _Dynamic_Primary_CCA{ 142 u1Byte PriCCA_flag; 143 u1Byte intf_flag; 144 u1Byte intf_type; 145 u1Byte DupRTS_flag; 146 u1Byte Monitor_flag; 147 u1Byte CH_offset; 148 u1Byte MF_state; 149 }Pri_CCA_T, *pPri_CCA_T; 150 151 152 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 153 154 155 #ifdef ADSL_AP_BUILD_WORKAROUND 156 #define MAX_TOLERANCE 5 157 #define IQK_DELAY_TIME 1 //ms 158 #endif 159 #if 0//defined in 8192cd.h 160 // 161 // Indicate different AP vendor for IOT issue. 162 // 163 typedef enum _HT_IOT_PEER 164 { 165 HT_IOT_PEER_UNKNOWN = 0, 166 HT_IOT_PEER_REALTEK = 1, 167 HT_IOT_PEER_REALTEK_92SE = 2, 168 HT_IOT_PEER_BROADCOM = 3, 169 HT_IOT_PEER_RALINK = 4, 170 HT_IOT_PEER_ATHEROS = 5, 171 HT_IOT_PEER_CISCO = 6, 172 HT_IOT_PEER_MERU = 7, 173 HT_IOT_PEER_MARVELL = 8, 174 HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 175 HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP 176 HT_IOT_PEER_AIRGO = 11, 177 HT_IOT_PEER_INTEL = 12, 178 HT_IOT_PEER_RTK_APCLIENT = 13, 179 HT_IOT_PEER_REALTEK_81XX = 14, 180 HT_IOT_PEER_REALTEK_WOW = 15, 181 HT_IOT_PEER_MAX = 16 182 }HT_IOT_PEER_E, *PHTIOT_PEER_E; 183 #endif 184 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 185 186 #define DM_Type_ByFW 0 187 #define DM_Type_ByDriver 1 188 189 // 190 // Declare for common info 191 // 192 193 #define IQK_THRESHOLD 8 194 #define DPK_THRESHOLD 4 195 196 197 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 198 __PACK typedef struct _ODM_Phy_Status_Info_ 199 { 200 u1Byte RxPWDBAll; 201 u1Byte SignalQuality; /* in 0-100 index. */ 202 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 203 s1Byte RxMIMOSignalQuality[4]; /* EVM */ 204 s1Byte RxSNR[4]; /* per-path's SNR */ 205 #if (RTL8822B_SUPPORT == 1) 206 u1Byte RxCount; /* RX path counter---*/ 207 #endif 208 u1Byte BandWidth; 209 210 } __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; 211 212 typedef struct _ODM_Phy_Status_Info_Append_ 213 { 214 u1Byte MAC_CRC32; 215 216 }ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; 217 218 #else 219 220 typedef struct _ODM_Phy_Status_Info_ 221 { 222 // 223 // Be care, if you want to add any element please insert between 224 // RxPWDBAll & SignalStrength. 225 // 226 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 227 u4Byte RxPWDBAll; 228 #else 229 u1Byte RxPWDBAll; 230 #endif 231 u1Byte SignalQuality; /* in 0-100 index. */ 232 s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ 233 u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ 234 u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ 235 s2Byte Cfo_short[4]; /* per-path's Cfo_short */ 236 s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ 237 s1Byte RxPower; /* in dBm Translate from PWdB */ 238 s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ 239 u1Byte BTRxRSSIPercentage; 240 u1Byte SignalStrength; /* in 0-100 index. */ 241 s1Byte RxPwr[4]; /* per-path's pwdb */ 242 s1Byte RxSNR[4]; /* per-path's SNR */ 243 #if (RTL8822B_SUPPORT == 1) 244 u1Byte RxCount:2; /* RX path counter---*/ 245 u1Byte BandWidth:2; 246 u1Byte rxsc:4; /* sub-channel---*/ 247 #else 248 u1Byte BandWidth; 249 #endif 250 u1Byte btCoexPwrAdjust; 251 #if (RTL8822B_SUPPORT == 1) 252 u1Byte channel; /* channel number---*/ 253 BOOLEAN bMuPacket; /* is MU packet or not---*/ 254 BOOLEAN bBeamformed; /* BF packet---*/ 255 #endif 256 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T; 257 #endif 258 259 typedef struct _ODM_Per_Pkt_Info_ 260 { 261 //u1Byte Rate; 262 u1Byte DataRate; 263 u1Byte StationID; 264 BOOLEAN bPacketMatchBSSID; 265 BOOLEAN bPacketToSelf; 266 BOOLEAN bPacketBeacon; 267 BOOLEAN bToSelf; 268 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; 269 270 271 typedef struct _ODM_Phy_Dbg_Info_ 272 { 273 //ODM Write,debug info 274 s1Byte RxSNRdB[4]; 275 u4Byte NumQryPhyStatus; 276 u4Byte NumQryPhyStatusCCK; 277 u4Byte NumQryPhyStatusOFDM; 278 #if (RTL8822B_SUPPORT == 1) 279 u4Byte NumQryMuPkt; 280 u4Byte NumQryBfPkt; 281 #endif 282 u1Byte NumQryBeaconPkt; 283 //Others 284 s4Byte RxEVM[4]; 285 286 }ODM_PHY_DBG_INFO_T; 287 288 289 typedef struct _ODM_Mac_Status_Info_ 290 { 291 u1Byte test; 292 293 }ODM_MAC_INFO; 294 295 // 296 // 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T 297 // Please declare below ODM relative info in your STA info structure. 298 // 299 #if 1 300 typedef struct _ODM_STA_INFO{ 301 // Driver Write 302 BOOLEAN bUsed; // record the sta status link or not? 303 //u1Byte WirelessMode; // 304 u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E 305 306 // ODM Write 307 //1 PHY_STATUS_INFO 308 u1Byte RSSI_Path[4]; // 309 u1Byte RSSI_Ave; 310 u1Byte RXEVM[4]; 311 u1Byte RXSNR[4]; 312 313 // ODM Write 314 //1 TX_INFO (may changed by IC) 315 //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. 316 #if 0 317 u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit 318 u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit 319 u1Byte ANTSEL_C; //only in Jagar: 4bit 320 u1Byte ANTSEL_D; //only in Jagar: 4bit 321 u1Byte TX_ANTL; //not in Jagar: 2bit 322 u1Byte TX_ANT_HT; //not in Jagar: 2bit 323 u1Byte TX_ANT_CCK; //not in Jagar: 2bit 324 u1Byte TXAGC_A; //not in Jagar: 4bit 325 u1Byte TXAGC_B; //not in Jagar: 4bit 326 u1Byte TXPWR_OFFSET; //only in Jagar: 3bit 327 u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK 328 #endif 329 330 // 331 // Please use compile flag to disabe the strcutrue for other IC except 88E. 332 // Move To lower layer. 333 // 334 // ODM Write Wilson will handle this part(said by Luke.Lee) 335 //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. 336 #if 0 337 //1 For 88E RA (don't redefine the naming) 338 u1Byte rate_id; 339 u1Byte rate_SGI; 340 u1Byte rssi_sta_ra; 341 u1Byte SGI_enable; 342 u1Byte Decision_rate; 343 u1Byte Pre_rate; 344 u1Byte Active; 345 346 // Driver write Wilson handle. 347 //1 TX_RPT (don't redefine the naming) 348 u2Byte RTY[4]; // ??? 349 u2Byte TOTAL; // ??? 350 u2Byte DROP; // ??? 351 // 352 // Please use compile flag to disabe the strcutrue for other IC except 88E. 353 // 354 #endif 355 356 }ODM_STA_INFO_T, *PODM_STA_INFO_T; 357 #endif 358 359 // 360 // 2011/10/20 MH Define Common info enum for all team. 361 // 362 typedef enum _ODM_Common_Info_Definition 363 { 364 //-------------REMOVED CASE-----------// 365 //ODM_CMNINFO_CCK_HP, 366 //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? 367 //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E 368 //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E 369 //-------------REMOVED CASE-----------// 370 371 // 372 // Fixed value: 373 // 374 375 //-----------HOOK BEFORE REG INIT-----------// 376 ODM_CMNINFO_PLATFORM = 0, 377 ODM_CMNINFO_ABILITY, // ODM_ABILITY_E 378 ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E 379 ODM_CMNINFO_MP_TEST_CHIP, 380 ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E 381 ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E 382 ODM_CMNINFO_FAB_VER, // ODM_FAB_E 383 ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? 384 ODM_CMNINFO_RFE_TYPE, 385 ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E 386 ODM_CMNINFO_PACKAGE_TYPE, 387 ODM_CMNINFO_EXT_LNA, // TRUE 388 ODM_CMNINFO_5G_EXT_LNA, 389 ODM_CMNINFO_EXT_PA, 390 ODM_CMNINFO_5G_EXT_PA, 391 ODM_CMNINFO_GPA, 392 ODM_CMNINFO_APA, 393 ODM_CMNINFO_GLNA, 394 ODM_CMNINFO_ALNA, 395 ODM_CMNINFO_EXT_TRSW, 396 ODM_CMNINFO_EXT_LNA_GAIN, 397 ODM_CMNINFO_PATCH_ID, //CUSTOMER ID 398 ODM_CMNINFO_BINHCT_TEST, 399 ODM_CMNINFO_BWIFI_TEST, 400 ODM_CMNINFO_SMART_CONCURRENT, 401 ODM_CMNINFO_CONFIG_BB_RF, 402 ODM_CMNINFO_DOMAIN_CODE_2G, 403 ODM_CMNINFO_DOMAIN_CODE_5G, 404 ODM_CMNINFO_IQKFWOFFLOAD, 405 ODM_CMNINFO_HUBUSBMODE, 406 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 407 ODM_CMNINFO_TX_TP, 408 ODM_CMNINFO_RX_TP, 409 ODM_CMNINFO_SOUNDING_SEQ, 410 //-----------HOOK BEFORE REG INIT-----------// 411 412 413 // 414 // Dynamic value: 415 // 416 //--------- POINTER REFERENCE-----------// 417 ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E 418 ODM_CMNINFO_TX_UNI, 419 ODM_CMNINFO_RX_UNI, 420 ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E 421 ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E 422 ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E 423 ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E 424 ODM_CMNINFO_BW, // ODM_BW_E 425 ODM_CMNINFO_CHNL, 426 ODM_CMNINFO_FORCED_RATE, 427 428 ODM_CMNINFO_DMSP_GET_VALUE, 429 ODM_CMNINFO_BUDDY_ADAPTOR, 430 ODM_CMNINFO_DMSP_IS_MASTER, 431 ODM_CMNINFO_SCAN, 432 ODM_CMNINFO_POWER_SAVING, 433 ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E 434 ODM_CMNINFO_DRV_STOP, 435 ODM_CMNINFO_PNP_IN, 436 ODM_CMNINFO_INIT_ON, 437 ODM_CMNINFO_ANT_TEST, 438 ODM_CMNINFO_NET_CLOSED, 439 //ODM_CMNINFO_RTSTA_AID, // For win driver only? 440 ODM_CMNINFO_FORCED_IGI_LB, 441 ODM_CMNINFO_P2P_LINK, 442 ODM_CMNINFO_FCS_MODE, 443 ODM_CMNINFO_IS1ANTENNA, 444 ODM_CMNINFO_RFDEFAULTPATH, 445 //--------- POINTER REFERENCE-----------// 446 447 //------------CALL BY VALUE-------------// 448 ODM_CMNINFO_WIFI_DIRECT, 449 ODM_CMNINFO_WIFI_DISPLAY, 450 ODM_CMNINFO_LINK_IN_PROGRESS, 451 ODM_CMNINFO_LINK, 452 ODM_CMNINFO_STATION_STATE, 453 ODM_CMNINFO_RSSI_MIN, 454 ODM_CMNINFO_DBG_COMP, // u8Byte 455 ODM_CMNINFO_DBG_LEVEL, // u4Byte 456 ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte 457 ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte 458 ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte 459 ODM_CMNINFO_BT_ENABLED, 460 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 461 ODM_CMNINFO_BT_HS_RSSI, 462 ODM_CMNINFO_BT_OPERATION, 463 ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not 464 ODM_CMNINFO_BT_DIG, 465 ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil 466 ODM_CMNINFO_BT_DISABLE_EDCA, 467 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 468 #ifdef UNIVERSAL_REPEATER 469 ODM_CMNINFO_VXD_LINK, 470 #endif 471 #endif 472 ODM_CMNINFO_AP_TOTAL_NUM, 473 ODM_CMNINFO_POWER_TRAINING, 474 //------------CALL BY VALUE-------------// 475 476 // 477 // Dynamic ptr array hook itms. 478 // 479 ODM_CMNINFO_STA_STATUS, 480 ODM_CMNINFO_PHY_STATUS, 481 ODM_CMNINFO_MAC_STATUS, 482 483 ODM_CMNINFO_MAX, 484 485 486 }ODM_CMNINFO_E; 487 488 // 489 // 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY 490 // 491 typedef enum _ODM_Support_Ability_Definition 492 { 493 // 494 // BB ODM section BIT 0-19 495 // 496 ODM_BB_DIG = BIT0, 497 ODM_BB_RA_MASK = BIT1, 498 ODM_BB_DYNAMIC_TXPWR = BIT2, 499 ODM_BB_FA_CNT = BIT3, 500 ODM_BB_RSSI_MONITOR = BIT4, 501 ODM_BB_CCK_PD = BIT5, 502 ODM_BB_ANT_DIV = BIT6, 503 ODM_BB_PWR_SAVE = BIT7, 504 ODM_BB_PWR_TRAIN = BIT8, 505 ODM_BB_RATE_ADAPTIVE = BIT9, 506 ODM_BB_PATH_DIV = BIT10, 507 ODM_BB_PSD = BIT11, 508 ODM_BB_RXHP = BIT12, 509 ODM_BB_ADAPTIVITY = BIT13, 510 ODM_BB_CFO_TRACKING = BIT14, 511 ODM_BB_NHM_CNT = BIT15, 512 ODM_BB_PRIMARY_CCA = BIT16, 513 ODM_BB_TXBF = BIT17, 514 515 // 516 // MAC DM section BIT 20-23 517 // 518 ODM_MAC_EDCA_TURBO = BIT20, 519 ODM_MAC_EARLY_MODE = BIT21, 520 521 // 522 // RF ODM section BIT 24-31 523 // 524 ODM_RF_TX_PWR_TRACK = BIT24, 525 ODM_RF_RX_GAIN_TRACK = BIT25, 526 ODM_RF_CALIBRATION = BIT26, 527 528 }ODM_ABILITY_E; 529 530 //Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino 531 532 // ODM_CMNINFO_ONE_PATH_CCA 533 typedef enum tag_CCA_Path 534 { 535 ODM_CCA_2R = 0, 536 ODM_CCA_1R_A = 1, 537 ODM_CCA_1R_B = 2, 538 }ODM_CCA_PATH_E; 539 540 //move RAInfo to Phydm_RaInfo.h 541 542 //Remove struct PATHDIV_PARA to odm_PathDiv.h 543 544 //Remove struct to odm_PowerTracking.h by YuChen 545 // 546 // ODM Dynamic common info value definition 547 // 548 //Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino 549 550 //move PathDiv to Phydm_PathDiv.h 551 552 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ 553 PHY_REG_PG_RELATIVE_VALUE = 0, 554 PHY_REG_PG_EXACT_VALUE = 1 555 } PHY_REG_PG_TYPE; 556 557 // 558 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. 559 // 560 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 561 #if (RT_PLATFORM != PLATFORM_LINUX) 562 typedef 563 #endif 564 565 struct DM_Out_Source_Dynamic_Mechanism_Structure 566 #else// for AP,ADSL,CE Team 567 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure 568 #endif 569 { 570 //RT_TIMER FastAntTrainingTimer; 571 // 572 // Add for different team use temporarily 573 // 574 PADAPTER Adapter; // For CE/NIC team 575 prtl8192cd_priv priv; // For AP/ADSL team 576 // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. 577 BOOLEAN odm_ready; 578 579 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) 580 rtl8192cd_priv fake_priv; 581 #endif 582 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 583 // ADSL_AP_BUILD_WORKAROUND 584 ADAPTER fake_adapter; 585 #endif 586 587 PHY_REG_PG_TYPE PhyRegPgValueType; 588 u1Byte PhyRegPgVersion; 589 590 u8Byte DebugComponents; 591 u4Byte DebugLevel; 592 593 u4Byte NumQryPhyStatusAll; //CCK + OFDM 594 u4Byte LastNumQryPhyStatusAll; 595 u4Byte RxPWDBAve; 596 BOOLEAN MPDIG_2G; //off MPDIG 597 u1Byte Times_2G; 598 599 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 600 BOOLEAN bCckHighPower; 601 u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE 602 u1Byte ControlChannel; 603 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// 604 605 //--------REMOVED COMMON INFO----------// 606 //u1Byte PseudoMacPhyMode; 607 //BOOLEAN *BTCoexist; 608 //BOOLEAN PseudoBtCoexist; 609 //u1Byte OPMode; 610 //BOOLEAN bAPMode; 611 //BOOLEAN bClientMode; 612 //BOOLEAN bAdHocMode; 613 //BOOLEAN bSlaveOfDMSP; 614 //--------REMOVED COMMON INFO----------// 615 616 617 //1 COMMON INFORMATION 618 619 // 620 // Init Value 621 // 622 //-----------HOOK BEFORE REG INIT-----------// 623 // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 624 u1Byte SupportPlatform; 625 // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K 626 u4Byte SupportAbility; 627 // ODM PCIE/USB/SDIO = 1/2/3 628 u1Byte SupportInterface; 629 // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... 630 u4Byte SupportICType; 631 // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... 632 u1Byte CutVersion; 633 // Fab Version TSMC/UMC = 0/1 634 u1Byte FabVersion; 635 // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... 636 u1Byte RFType; 637 u1Byte RFEType; 638 // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... 639 u1Byte BoardType; 640 u1Byte PackageType; 641 u2Byte TypeGLNA; 642 u2Byte TypeGPA; 643 u2Byte TypeALNA; 644 u2Byte TypeAPA; 645 // with external LNA NO/Yes = 0/1 646 u1Byte ExtLNA; // 2G 647 u1Byte ExtLNA5G; //5G 648 // with external PA NO/Yes = 0/1 649 u1Byte ExtPA; // 2G 650 u1Byte ExtPA5G; //5G 651 // with external TRSW NO/Yes = 0/1 652 u1Byte ExtTRSW; 653 u1Byte ExtLNAGain; // 2G 654 u1Byte PatchID; //Customer ID 655 BOOLEAN bInHctTest; 656 BOOLEAN bWIFITest; 657 658 BOOLEAN bDualMacSmartConcurrent; 659 u4Byte BK_SupportAbility; 660 u1Byte AntDivType; 661 BOOLEAN ConfigBBRF; 662 u1Byte odm_Regulation2_4G; 663 u1Byte odm_Regulation5G; 664 u1Byte IQKFWOffload; 665 //-----------HOOK BEFORE REG INIT-----------// 666 667 // 668 // Dynamic Value 669 // 670 //--------- POINTER REFERENCE-----------// 671 672 u1Byte u1Byte_temp; 673 BOOLEAN BOOLEAN_temp; 674 PADAPTER PADAPTER_temp; 675 676 // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 677 u1Byte *pMacPhyMode; 678 //TX Unicast byte count 679 u8Byte *pNumTxBytesUnicast; 680 //RX Unicast byte count 681 u8Byte *pNumRxBytesUnicast; 682 // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 683 u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E 684 // Frequence band 2.4G/5G = 0/1 685 u1Byte *pBandType; 686 // Secondary channel offset don't_care/below/above = 0/1/2 687 u1Byte *pSecChOffset; 688 // Security mode Open/WEP/AES/TKIP = 0/1/2/3 689 u1Byte *pSecurity; 690 // BW info 20M/40M/80M = 0/1/2 691 u1Byte *pBandWidth; 692 // Central channel location Ch1/Ch2/.... 693 u1Byte *pChannel; //central channel number 694 BOOLEAN DPK_Done; 695 // Common info for 92D DMSP 696 697 BOOLEAN *pbGetValueFromOtherMac; 698 PADAPTER *pBuddyAdapter; 699 BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave 700 // Common info for Status 701 BOOLEAN *pbScanInProcess; 702 BOOLEAN *pbPowerSaving; 703 // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. 704 u1Byte *pOnePathCCA; 705 //pMgntInfo->AntennaTest 706 u1Byte *pAntennaTest; 707 BOOLEAN *pbNet_closed; 708 //u1Byte *pAidMap; 709 u1Byte *pu1ForcedIgiLb; 710 BOOLEAN *pIsFcsModeEnable; 711 /*--------- For 8723B IQK-----------*/ 712 BOOLEAN *pIs1Antenna; 713 u1Byte *pRFDefaultPath; 714 // 0:S1, 1:S0 715 716 //--------- POINTER REFERENCE-----------// 717 pu2Byte pForcedDataRate; 718 pu1Byte HubUsbMode; 719 BOOLEAN *pbFwDwRsvdPageInProgress; 720 u4Byte *pCurrentTxTP; 721 u4Byte *pCurrentRxTP; 722 u1Byte *pSoundingSeq; 723 //------------CALL BY VALUE-------------// 724 BOOLEAN bLinkInProcess; 725 BOOLEAN bWIFI_Direct; 726 BOOLEAN bWIFI_Display; 727 BOOLEAN bLinked; 728 BOOLEAN bsta_state; 729 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 730 #ifdef UNIVERSAL_REPEATER 731 BOOLEAN VXD_bLinked; 732 #endif 733 #endif // for repeater mode add by YuChen 2014.06.23 734 u1Byte RSSI_Min; 735 u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ 736 BOOLEAN bIsMPChip; 737 BOOLEAN bOneEntryOnly; 738 BOOLEAN mp_mode; 739 u4Byte OneEntry_MACID; 740 u1Byte pre_number_linked_client; 741 u1Byte number_linked_client; 742 u1Byte pre_number_active_client; 743 u1Byte number_active_client; 744 // Common info for BTDM 745 BOOLEAN bBtEnabled; // BT is enabled 746 BOOLEAN bBtConnectProcess; // BT HS is under connection progress. 747 u1Byte btHsRssi; // BT HS mode wifi rssi value. 748 BOOLEAN bBtHsOperation; // BT HS mode is under progress 749 u1Byte btHsDigVal; // use BT rssi to decide the DIG value 750 BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo 751 BOOLEAN bBtBusy; // BT is busy. 752 BOOLEAN bBtLimitedDig; // BT is busy. 753 BOOLEAN bDisablePhyApi; 754 //------------CALL BY VALUE-------------// 755 u1Byte RSSI_A; 756 u1Byte RSSI_B; 757 u1Byte RSSI_C; 758 u1Byte RSSI_D; 759 u8Byte RSSI_TRSW; 760 u8Byte RSSI_TRSW_H; 761 u8Byte RSSI_TRSW_L; 762 u8Byte RSSI_TRSW_iso; 763 u1Byte TXAntStatus; 764 u1Byte RXAntStatus; 765 u1Byte cck_lna_idx; 766 u1Byte cck_vga_idx; 767 u1Byte ofdm_agc_idx[4]; 768 769 u1Byte RxRate; 770 BOOLEAN bNoisyState; 771 u1Byte TxRate; 772 u1Byte LinkedInterval; 773 u1Byte preChannel; 774 u4Byte TxagcOffsetValueA; 775 BOOLEAN IsTxagcOffsetPositiveA; 776 u4Byte TxagcOffsetValueB; 777 BOOLEAN IsTxagcOffsetPositiveB; 778 u4Byte tx_tp; 779 u4Byte rx_tp; 780 u4Byte total_tp; 781 u8Byte curTxOkCnt; 782 u8Byte curRxOkCnt; 783 u8Byte lastTxOkCnt; 784 u8Byte lastRxOkCnt; 785 u4Byte BbSwingOffsetA; 786 BOOLEAN IsBbSwingOffsetPositiveA; 787 u4Byte BbSwingOffsetB; 788 BOOLEAN IsBbSwingOffsetPositiveB; 789 u1Byte antdiv_rssi; 790 u1Byte fat_comb_a; 791 u1Byte fat_comb_b; 792 u1Byte antdiv_intvl; 793 u1Byte AntType; 794 u1Byte pre_AntType; 795 u1Byte antdiv_period; 796 u1Byte antdiv_select; 797 u1Byte path_select; 798 u1Byte antdiv_evm_en; 799 u1Byte bdc_holdstate; 800 u1Byte NdpaPeriod; 801 BOOLEAN H2C_RARpt_connect; 802 BOOLEAN cck_agc_report_type; 803 804 u1Byte dm_dig_max_TH; 805 u1Byte dm_dig_min_TH; 806 u1Byte print_agc; 807 u1Byte TrafficLoad; 808 u1Byte pre_TrafficLoad; 809 810 811 //For Adaptivtiy 812 u2Byte NHM_cnt_0; 813 u2Byte NHM_cnt_1; 814 s1Byte TH_L2H_default; 815 s1Byte TH_EDCCA_HL_diff_default; 816 s1Byte TH_L2H_ini; 817 s1Byte TH_EDCCA_HL_diff; 818 s1Byte TH_L2H_ini_mode2; 819 s1Byte TH_EDCCA_HL_diff_mode2; 820 BOOLEAN Carrier_Sense_enable; 821 u1Byte Adaptivity_IGI_upper; 822 BOOLEAN adaptivity_flag; 823 u1Byte DCbackoff; 824 BOOLEAN Adaptivity_enable; 825 u1Byte APTotalNum; 826 BOOLEAN EDCCA_enable; 827 ADAPTIVITY_STATISTICS Adaptivity; 828 //For Adaptivtiy 829 u1Byte LastUSBHub; 830 u1Byte TxBfDataRate; 831 832 u1Byte c2h_cmd_start; 833 u1Byte fw_debug_trace[60]; 834 u1Byte pre_c2h_seq; 835 BOOLEAN fw_buff_is_enpty; 836 u4Byte data_frame_num; 837 838 /*for noise detection*/ 839 BOOLEAN NoisyDecision; /*b_noisy*/ 840 BOOLEAN pre_b_noisy; 841 u4Byte NoisyDecision_Smooth; 842 843 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 844 ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; 845 #endif 846 // 847 //2 Define STA info. 848 // _ODM_STA_INFO 849 // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? 850 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 851 u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ 852 853 #if (RATE_ADAPTIVE_SUPPORT == 1) 854 u2Byte CurrminRptTime; 855 ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 856 #endif 857 // 858 // 2012/02/14 MH Add to share 88E ra with other SW team. 859 // We need to colelct all support abilit to a proper area. 860 // 861 BOOLEAN RaSupport88E; 862 863 // Define ........... 864 865 // Latest packet phy info (ODM write) 866 ODM_PHY_DBG_INFO_T PhyDbgInfo; 867 //PHY_INFO_88E PhyInfo; 868 869 // Latest packet phy info (ODM write) 870 ODM_MAC_INFO *pMacInfo; 871 //MAC_INFO_88E MacInfo; 872 873 // Different Team independt structure?? 874 875 // 876 //TX_RTP_CMN TX_retrpo; 877 //TX_RTP_88E TX_retrpo; 878 //TX_RTP_8195 TX_retrpo; 879 880 // 881 //ODM Structure 882 // 883 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 884 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 885 BDC_T DM_BdcTable; 886 #endif 887 888 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 889 SAT_T dm_sat_table; 890 #endif 891 892 #endif 893 FAT_T DM_FatTable; 894 DIG_T DM_DigTable; 895 896 PS_T DM_PSTable; 897 Pri_CCA_T DM_PriCCA; 898 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 899 RXHP_T DM_RXHP_Table; 900 #endif 901 RA_T DM_RA_Table; 902 FALSE_ALARM_STATISTICS FalseAlmCnt; 903 FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 904 SWAT_T DM_SWAT_Table; 905 CFO_TRACKING DM_CfoTrack; 906 ACS DM_ACS; 907 908 909 #if (RTL8814A_SUPPORT == 1) 910 IQK_INFO IQK_info; 911 #endif /* (RTL8814A_SUPPORT==1) */ 912 913 914 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 915 //Path Div Struct 916 PATHDIV_PARA pathIQK; 917 #endif 918 #if(defined(CONFIG_PATH_DIVERSITY)) 919 PATHDIV_T DM_PathDiv; 920 #endif 921 922 EDCA_T DM_EDCA_Table; 923 u4Byte WMMEDCA_BE; 924 925 // Copy from SD4 structure 926 // 927 // ================================================== 928 // 929 930 //common 931 //u1Byte DM_Type; 932 //u1Byte PSD_Report_RXHP[80]; // Add By Gary 933 //u1Byte PSD_func_flag; // Add By Gary 934 //for DIG 935 //u1Byte bDMInitialGainEnable; 936 //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. 937 938 BOOLEAN *pbDriverStopped; 939 BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; 940 BOOLEAN *pinit_adpt_in_progress; 941 942 //PSD 943 BOOLEAN bUserAssignLevel; 944 RT_TIMER PSDTimer; 945 u1Byte RSSI_BT; //come from BT 946 BOOLEAN bPSDinProcess; 947 BOOLEAN bPSDactive; 948 BOOLEAN bDMInitialGainEnable; 949 950 //MPT DIG 951 RT_TIMER MPT_DIGTimer; 952 953 //for rate adaptive, in fact, 88c/92c fw will handle this 954 u1Byte bUseRAMask; 955 956 ODM_RATE_ADAPTIVE RateAdaptive; 957 //#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 958 #if(defined(CONFIG_ANT_DETECTION)) 959 ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool 960 #endif 961 ODM_RF_CAL_T RFCalibrateInfo; 962 963 964 // 965 // Dynamic ATC switch 966 // 967 968 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) 969 // 970 // Power Training 971 // 972 u1Byte ForcePowerTrainingState; 973 BOOLEAN bChangeState; 974 u4Byte PT_score; 975 u8Byte OFDM_RX_Cnt; 976 u8Byte CCK_RX_Cnt; 977 #endif 978 BOOLEAN bDisablePowerTraining; 979 980 // 981 // ODM system resource. 982 // 983 984 // ODM relative time. 985 RT_TIMER PathDivSwitchTimer; 986 //2011.09.27 add for Path Diversity 987 RT_TIMER CCKPathDiversityTimer; 988 RT_TIMER FastAntTrainingTimer; 989 #ifdef ODM_EVM_ENHANCE_ANTDIV 990 RT_TIMER EVM_FastAntTrainingTimer; 991 #endif 992 RT_TIMER sbdcnt_timer; 993 994 // ODM relative workitem. 995 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 996 #if USE_WORKITEM 997 RT_WORK_ITEM PathDivSwitchWorkitem; 998 RT_WORK_ITEM CCKPathDiversityWorkitem; 999 RT_WORK_ITEM FastAntTrainingWorkitem; 1000 RT_WORK_ITEM MPT_DIGWorkitem; 1001 RT_WORK_ITEM RaRptWorkitem; 1002 RT_WORK_ITEM sbdcnt_workitem; 1003 #endif 1004 #endif 1005 1006 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1007 #if (BEAMFORMING_SUPPORT == 1) 1008 RT_BEAMFORMING_INFO BeamformingInfo; 1009 #endif 1010 #endif 1011 1012 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) 1013 1014 #if (RT_PLATFORM != PLATFORM_LINUX) 1015 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1016 #else 1017 }; 1018 #endif 1019 1020 #else// for AP,ADSL,CE Team 1021 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure 1022 #endif 1023 1024 1025 typedef enum _PHYDM_STRUCTURE_TYPE{ 1026 PHYDM_FALSEALMCNT, 1027 PHYDM_CFOTRACK, 1028 PHYDM_ADAPTIVITY, 1029 PHYDM_ROMINFO, 1030 1031 }PHYDM_STRUCTURE_TYPE; 1032 1033 1034 1035 typedef enum _ODM_RF_CONTENT{ 1036 odm_radioa_txt = 0x1000, 1037 odm_radiob_txt = 0x1001, 1038 odm_radioc_txt = 0x1002, 1039 odm_radiod_txt = 0x1003 1040 } ODM_RF_CONTENT; 1041 1042 typedef enum _ODM_BB_Config_Type{ 1043 CONFIG_BB_PHY_REG, 1044 CONFIG_BB_AGC_TAB, 1045 CONFIG_BB_AGC_TAB_2G, 1046 CONFIG_BB_AGC_TAB_5G, 1047 CONFIG_BB_PHY_REG_PG, 1048 CONFIG_BB_PHY_REG_MP, 1049 CONFIG_BB_AGC_TAB_DIFF, 1050 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1051 1052 typedef enum _ODM_RF_Config_Type{ 1053 CONFIG_RF_RADIO, 1054 CONFIG_RF_TXPWR_LMT, 1055 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1056 1057 typedef enum _ODM_FW_Config_Type{ 1058 CONFIG_FW_NIC, 1059 CONFIG_FW_NIC_2, 1060 CONFIG_FW_AP, 1061 CONFIG_FW_AP_2, 1062 CONFIG_FW_MP, 1063 CONFIG_FW_WoWLAN, 1064 CONFIG_FW_WoWLAN_2, 1065 CONFIG_FW_AP_WoWLAN, 1066 CONFIG_FW_BT, 1067 } ODM_FW_Config_Type; 1068 1069 // Status code 1070 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1071 typedef enum _RT_STATUS{ 1072 RT_STATUS_SUCCESS, 1073 RT_STATUS_FAILURE, 1074 RT_STATUS_PENDING, 1075 RT_STATUS_RESOURCE, 1076 RT_STATUS_INVALID_CONTEXT, 1077 RT_STATUS_INVALID_PARAMETER, 1078 RT_STATUS_NOT_SUPPORT, 1079 RT_STATUS_OS_API_FAILED, 1080 }RT_STATUS,*PRT_STATUS; 1081 #endif // end of RT_STATUS definition 1082 1083 #ifdef REMOVE_PACK 1084 #pragma pack() 1085 #endif 1086 1087 //#include "odm_function.h" 1088 1089 //3=========================================================== 1090 //3 DIG 1091 //3=========================================================== 1092 1093 //Remove DIG by Yuchen 1094 1095 //3=========================================================== 1096 //3 AGC RX High Power Mode 1097 //3=========================================================== 1098 #define LNA_Low_Gain_1 0x64 1099 #define LNA_Low_Gain_2 0x5A 1100 #define LNA_Low_Gain_3 0x58 1101 1102 #define FA_RXHP_TH1 5000 1103 #define FA_RXHP_TH2 1500 1104 #define FA_RXHP_TH3 800 1105 #define FA_RXHP_TH4 600 1106 #define FA_RXHP_TH5 500 1107 1108 //3=========================================================== 1109 //3 EDCA 1110 //3=========================================================== 1111 1112 //3=========================================================== 1113 //3 Dynamic Tx Power 1114 //3=========================================================== 1115 //Dynamic Tx Power Control Threshold 1116 1117 //Remove By YuChen 1118 1119 //3=========================================================== 1120 //3 Tx Power Tracking 1121 //3=========================================================== 1122 1123 1124 1125 //3=========================================================== 1126 //3 Rate Adaptive 1127 //3=========================================================== 1128 //Remove to odm_RaInfo.h by RS_James 1129 1130 //3=========================================================== 1131 //3 BB Power Save 1132 //3=========================================================== 1133 1134 typedef enum tag_1R_CCA_Type_Definition 1135 { 1136 CCA_1R =0, 1137 CCA_2R = 1, 1138 CCA_MAX = 2, 1139 }DM_1R_CCA_E; 1140 1141 typedef enum tag_RF_Type_Definition 1142 { 1143 RF_Save =0, 1144 RF_Normal = 1, 1145 RF_MAX = 2, 1146 }DM_RF_E; 1147 1148 1149 // 1150 // Extern Global Variables. 1151 // 1152 //PowerTracking move to odm_powerTrakcing.h by YuChen 1153 // 1154 // check Sta pointer valid or not 1155 // 1156 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) 1157 #define IS_STA_VALID(pSta) (pSta && pSta->expire_to) 1158 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1159 #define IS_STA_VALID(pSta) (pSta && pSta->bUsed) 1160 #else 1161 #define IS_STA_VALID(pSta) (pSta) 1162 #endif 1163 1164 //Remove DIG by yuchen 1165 1166 //Remove BB power saving by Yuchen 1167 1168 //remove PT by yuchen 1169 1170 //ODM_RAStateCheck() Remove by RS_James 1171 1172 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) 1173 //============================================================ 1174 // function prototype 1175 //============================================================ 1176 //#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh 1177 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, 1178 // IN INT32 DM_Type, 1179 // IN INT32 DM_Value); 1180 1181 //Remove DIG by yuchen 1182 1183 1184 BOOLEAN 1185 ODM_CheckPowerStatus( 1186 IN PADAPTER Adapter 1187 ); 1188 1189 1190 //Remove ODM_RateAdaptiveStateApInit() by RS_James 1191 1192 //Remove Edca by YuChen 1193 1194 #endif 1195 1196 1197 1198 u4Byte odm_ConvertTo_dB(u4Byte Value); 1199 1200 u4Byte odm_ConvertTo_linear(u4Byte Value); 1201 1202 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) 1203 1204 u4Byte 1205 GetPSDData( 1206 PDM_ODM_T pDM_Odm, 1207 unsigned int point, 1208 u1Byte initial_gain_psd); 1209 1210 #endif 1211 1212 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1213 VOID 1214 ODM_DMWatchdog_LPS( 1215 IN PDM_ODM_T pDM_Odm 1216 ); 1217 #endif 1218 1219 1220 s4Byte 1221 ODM_PWdB_Conversion( 1222 IN s4Byte X, 1223 IN u4Byte TotalBit, 1224 IN u4Byte DecimalBit 1225 ); 1226 1227 s4Byte 1228 ODM_SignConversion( 1229 IN s4Byte value, 1230 IN u4Byte TotalBit 1231 ); 1232 1233 VOID 1234 ODM_DMInit( 1235 IN PDM_ODM_T pDM_Odm 1236 ); 1237 1238 VOID 1239 ODM_DMReset( 1240 IN PDM_ODM_T pDM_Odm 1241 ); 1242 1243 VOID 1244 phydm_support_ablity_debug( 1245 IN PVOID pDM_VOID, 1246 IN u4Byte *const dm_value, 1247 IN u4Byte *_used, 1248 OUT char *output, 1249 IN u4Byte *_out_len 1250 ); 1251 1252 VOID 1253 ODM_DMWatchdog( 1254 IN PDM_ODM_T pDM_Odm // For common use in the future 1255 ); 1256 1257 VOID 1258 ODM_CmnInfoInit( 1259 IN PDM_ODM_T pDM_Odm, 1260 IN ODM_CMNINFO_E CmnInfo, 1261 IN u4Byte Value 1262 ); 1263 1264 VOID 1265 ODM_CmnInfoHook( 1266 IN PDM_ODM_T pDM_Odm, 1267 IN ODM_CMNINFO_E CmnInfo, 1268 IN PVOID pValue 1269 ); 1270 1271 VOID 1272 ODM_CmnInfoPtrArrayHook( 1273 IN PDM_ODM_T pDM_Odm, 1274 IN ODM_CMNINFO_E CmnInfo, 1275 IN u2Byte Index, 1276 IN PVOID pValue 1277 ); 1278 1279 VOID 1280 ODM_CmnInfoUpdate( 1281 IN PDM_ODM_T pDM_Odm, 1282 IN u4Byte CmnInfo, 1283 IN u8Byte Value 1284 ); 1285 1286 #if(DM_ODM_SUPPORT_TYPE==ODM_AP) 1287 VOID 1288 ODM_InitAllThreads( 1289 IN PDM_ODM_T pDM_Odm 1290 ); 1291 1292 VOID 1293 ODM_StopAllThreads( 1294 IN PDM_ODM_T pDM_Odm 1295 ); 1296 #endif 1297 1298 VOID 1299 ODM_InitAllTimers( 1300 IN PDM_ODM_T pDM_Odm 1301 ); 1302 1303 VOID 1304 ODM_CancelAllTimers( 1305 IN PDM_ODM_T pDM_Odm 1306 ); 1307 1308 VOID 1309 ODM_ReleaseAllTimers( 1310 IN PDM_ODM_T pDM_Odm 1311 ); 1312 1313 1314 1315 1316 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1317 VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1318 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); 1319 1320 1321 1322 u8Byte 1323 PlatformDivision64( 1324 IN u8Byte x, 1325 IN u8Byte y 1326 ); 1327 1328 //==================================================== 1329 //3 PathDiV End 1330 //==================================================== 1331 1332 1333 #define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh 1334 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, 1335 // IN INT32 DM_Type, 1336 // IN INT32 DM_Value); 1337 // 1338 // PathDiveristy Remove by RS_James 1339 1340 typedef enum tag_DIG_Connect_Definition 1341 { 1342 DIG_STA_DISCONNECT = 0, 1343 DIG_STA_CONNECT = 1, 1344 DIG_STA_BEFORE_CONNECT = 2, 1345 DIG_MultiSTA_DISCONNECT = 3, 1346 DIG_MultiSTA_CONNECT = 4, 1347 DIG_CONNECT_MAX 1348 }DM_DIG_CONNECT_E; 1349 1350 1351 // 1352 // 2012/01/12 MH Check afapter status. Temp fix BSOD. 1353 // 1354 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\ 1355 if (pDM_Odm->Adapter == NULL)\ 1356 {\ 1357 return;\ 1358 }\ 1359 1360 1361 // 1362 // For new definition in MP temporarily fro power tracking, 1363 // 1364 /* 1365 #define odm_TXPowerTrackingDirectCall(_Adapter) \ 1366 IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ 1367 IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ 1368 IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ 1369 ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter) 1370 */ 1371 1372 1373 #endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1374 1375 VOID 1376 ODM_AsocEntry_Init( 1377 IN PDM_ODM_T pDM_Odm 1378 ); 1379 1380 //Remove ODM_DynamicARFBSelect() by RS_James 1381 1382 PVOID 1383 PhyDM_Get_Structure( 1384 IN PDM_ODM_T pDM_Odm, 1385 IN u1Byte Structure_Type 1386 ); 1387 1388 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) 1389 /*===========================================================*/ 1390 /* The following is for compile only*/ 1391 /*===========================================================*/ 1392 1393 #define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE 1394 #define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE 1395 #define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE 1396 #define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE 1397 #define RF_T_METER_92D 0x42 1398 1399 1400 #define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value) 1401 #define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value) 1402 #define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value) 1403 #define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value) 1404 1405 #define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) 1406 1407 #define RX_HAL_IS_CCK_RATE_92C(pDesc)\ 1408 (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\ 1409 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\ 1410 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\ 1411 GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M) 1412 1413 #define H2C_92C_PSD_RESULT 16 1414 1415 #define rConfig_ram64x16 0xb2c 1416 1417 #define TARGET_CHNL_NUM_2G_5G 59 1418 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1419 1420 VOID 1421 FillH2CCmd92C( 1422 IN PADAPTER Adapter, 1423 IN u1Byte ElementID, 1424 IN u4Byte CmdLen, 1425 IN pu1Byte pCmdBuffer 1426 ); 1427 VOID 1428 PHY_SetTxPowerLevel8192C( 1429 IN PADAPTER Adapter, 1430 IN u1Byte channel 1431 ); 1432 u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); 1433 1434 #endif 1435 1436 //=========================================================== 1437 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1438 1439 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1440 void odm_dtc(PDM_ODM_T pDM_Odm); 1441 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ 1442 1443 1444 VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); 1445 1446 1447 #endif 1448 1449