1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HAL_MP_C_
21 #ifdef CONFIG_MP_INCLUDED
22
23 #ifdef CONFIG_RTL8188E
24 #include <rtl8188e_hal.h>
25 #endif
26 #ifdef CONFIG_RTL8723B
27 #include <rtl8723b_hal.h>
28 #endif
29 #ifdef CONFIG_RTL8192E
30 #include <rtl8192e_hal.h>
31 #endif
32 #ifdef CONFIG_RTL8814A
33 #include <rtl8814a_hal.h>
34 #endif
35 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
36 #include <rtl8812a_hal.h>
37 #endif
38 #ifdef CONFIG_RTL8703B
39 #include <rtl8703b_hal.h>
40 #endif
41 #ifdef CONFIG_RTL8188F
42 #include <rtl8188f_hal.h>
43 #endif
44
45
MgntQuery_NssTxRate(u16 Rate)46 u8 MgntQuery_NssTxRate(u16 Rate)
47 {
48 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
49
50 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
51 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
52 NssNum = RF_2TX;
53 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
54 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
55 NssNum = RF_3TX;
56 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
57 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
58 NssNum = RF_4TX;
59 else
60 NssNum = RF_1TX;
61
62 return NssNum;
63 }
64
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)65 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
66 {
67 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
68 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
69 u8 ChannelToSw = pMptCtx->MptChannelToSw;
70 ULONG ulRateIdx = pMptCtx->MptRateIndex;
71 ULONG ulbandwidth = pMptCtx->MptBandWidth;
72
73 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
74 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
75 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
76 pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
77 pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
78
79 if ((PlatformEFIORead4Byte(pAdapter, 0xF4)&BIT29) == BIT29) {
80 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
81 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
82 } else {
83 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
84 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
85 }
86 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
87
88 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
89 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
90 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
91 } else {
92 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
93 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
94 }
95
96 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
97 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
98 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
99 }
100 }
101
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)102 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
103 {
104 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
105 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
106
107
108 if (!netif_running(padapter->pnetdev)) {
109 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
110 return _FAIL;
111 }
112
113 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
114 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
115 return _FAIL;
116 }
117 if (enable)
118 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
119 else
120 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
121
122 return _SUCCESS;
123 }
124
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)125 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
126 {
127 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
128 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
129
130
131 *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
132 }
133
134
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)135 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
136 {
137 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
138 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
139 u8 i;
140 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
141
142 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
143 u1Byte u1Channel = pHalData->CurrentChannel;
144 ULONG ulRateIdx = pMptCtx->MptRateIndex;
145 u1Byte DataRate = 0xFF;
146
147 DataRate = MptToMgntRate(ulRateIdx);
148
149 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
150 pHalData->bCCKinCH14 = TRUE;
151 else
152 pHalData->bCCKinCH14 = FALSE;
153
154 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
155 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
156 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
157 PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
158 PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
159
160 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));
161 } else {
162 /* Normal setting for 8703B, just recover to the default setting. */
163 /* This hardcore values reference from the parameter which BB team gave. */
164 for (i = 0 ; i < 2 ; ++i)
165 PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
166
167 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel));
168 }
169 } else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
170 /* No difference between CCK in CH14 and others, no need to change TX filter */
171 } else {
172
173 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
174 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
175
176 if (!pHalData->bCCKinCH14) {
177 /* Readback the current bb cck swing value and compare with the table to */
178 /* get the current swing index */
179 for (i = 0; i < CCK_TABLE_SIZE; i++) {
180 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
181 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
182 CCKSwingIndex = i;
183 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
184 (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
185 break;
186 }
187 }
188
189 /*Write 0xa22 0xa23*/
190 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
191 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
192
193
194 /*Write 0xa24 ~ 0xa27*/
195 TempVal2 = 0;
196 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
197 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
198 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16) +
199 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
200
201 /*Write 0xa28 0xa29*/
202 TempVal3 = 0;
203 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
204 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
205 } else {
206 for (i = 0; i < CCK_TABLE_SIZE; i++) {
207 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
208 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
209 CCKSwingIndex = i;
210 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
211 (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
212 break;
213 }
214 }
215
216 /*Write 0xa22 0xa23*/
217 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
218 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
219
220 /*Write 0xa24 ~ 0xa27*/
221 TempVal2 = 0;
222 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
223 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
224 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16) +
225 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
226
227 /*Write 0xa28 0xa29*/
228 TempVal3 = 0;
229 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
230 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
231 }
232
233 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
234 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
235 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
236
237 }
238
239 }
240
hal_mpt_SetChannel(PADAPTER pAdapter)241 void hal_mpt_SetChannel(PADAPTER pAdapter)
242 {
243 u8 eRFPath;
244 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
245 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
246 struct mp_priv *pmp = &pAdapter->mppriv;
247 u8 channel = pmp->channel;
248 u8 bandwidth = pmp->bandwidth;
249
250 hal_mpt_SwitchRfSetting(pAdapter);
251
252 SelectChannel(pAdapter, channel);
253
254 pHalData->bSwChnl = _TRUE;
255 pHalData->bSetChnlBW = _TRUE;
256 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
257
258 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
259
260 }
261
262 /*
263 * Notice
264 * Switch bandwitdth may change center frequency(channel)
265 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)266 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
267 {
268 struct mp_priv *pmp = &pAdapter->mppriv;
269 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
270
271 u8 channel = pmp->channel;
272 u8 bandwidth = pmp->bandwidth;
273
274 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
275 pHalData->bSwChnl = _TRUE;
276 pHalData->bSetChnlBW = _TRUE;
277 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
278
279 hal_mpt_SwitchRfSetting(pAdapter);
280 }
281
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)282 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
283 {
284 RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate));
285 switch (Rate) {
286 case MPT_CCK:
287 {
288 u4Byte TxAGC = 0, pwr = 0;
289 u1Byte rf;
290
291 pwr = pTxPower[ODM_RF_PATH_A];
292 if (pwr < 0x3f) {
293 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
294 PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
295 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
296 }
297 pwr = pTxPower[ODM_RF_PATH_B];
298 if (pwr < 0x3f) {
299 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
300 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
301 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
302 }
303
304 } break;
305
306 case MPT_OFDM_AND_HT:
307 {
308 u4Byte TxAGC = 0;
309 u1Byte pwr = 0, rf;
310
311 pwr = pTxPower[0];
312 if (pwr < 0x3f) {
313 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
314 DBG_871X("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
315
316 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
317 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
318 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
319 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
320 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
321 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
322 }
323 TxAGC = 0;
324 pwr = pTxPower[1];
325 if (pwr < 0x3f) {
326 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
327 DBG_871X("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
328
329 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
330 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
331 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
332 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
333 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
334 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
335 }
336 } break;
337
338 default:
339 break;
340 }
341 DBG_871X("<===mpt_SetTxPower_Old()\n");
342 }
343
344
345
346 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,pu1Byte pTxPower)347 mpt_SetTxPower(
348 PADAPTER pAdapter,
349 MPT_TXPWR_DEF Rate,
350 pu1Byte pTxPower
351 )
352 {
353 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
354
355 u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
356 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
357
358 if (IS_HARDWARE_TYPE_8814A(pAdapter))
359 EndPath = ODM_RF_PATH_D;
360
361 switch (Rate) {
362 case MPT_CCK:
363 {
364 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
365
366 for (path = StartPath; path <= EndPath; path++)
367 for (i = 0; i < sizeof(rate); ++i)
368 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
369 }
370 break;
371
372 case MPT_OFDM:
373 {
374 u1Byte rate[] = {
375 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
376 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
377 };
378
379 for (path = StartPath; path <= EndPath; path++)
380 for (i = 0; i < sizeof(rate); ++i)
381 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
382 } break;
383
384 case MPT_HT:
385 {
386 u1Byte rate[] = {
387 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
388 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
389 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
390 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
391 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
392 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
393 MGN_MCS30, MGN_MCS31,
394 };
395 if (pHalData->rf_type == RF_3T3R)
396 MaxRate = MGN_MCS23;
397 else if (pHalData->rf_type == RF_2T2R)
398 MaxRate = MGN_MCS15;
399 else
400 MaxRate = MGN_MCS7;
401
402 for (path = StartPath; path <= EndPath; path++) {
403 for (i = 0; i < sizeof(rate); ++i) {
404 if (rate[i] > MaxRate)
405 break;
406 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
407 }
408 }
409 } break;
410
411 case MPT_VHT:
412 {
413 u1Byte rate[] = {
414 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
415 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
416 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
417 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
418 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
419 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
420 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
421 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
422 };
423
424 if (pHalData->rf_type == RF_3T3R)
425 MaxRate = MGN_VHT3SS_MCS9;
426 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
427 MaxRate = MGN_VHT2SS_MCS9;
428 else
429 MaxRate = MGN_VHT1SS_MCS9;
430
431 for (path = StartPath; path <= EndPath; path++) {
432 for (i = 0; i < sizeof(rate); ++i) {
433 if (rate[i] > MaxRate)
434 break;
435 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
436 }
437 }
438 } break;
439
440 default:
441 DBG_871X("<===mpt_SetTxPower: Illegal channel!!\n");
442 break;
443 }
444
445 }
446
447
hal_mpt_SetTxPower(PADAPTER pAdapter)448 void hal_mpt_SetTxPower(PADAPTER pAdapter)
449 {
450 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
451 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
452 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
453
454 if (pHalData->rf_chip < RF_TYPE_MAX) {
455 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
456 IS_HARDWARE_TYPE_8723B(pAdapter) ||
457 IS_HARDWARE_TYPE_8192E(pAdapter) ||
458 IS_HARDWARE_TYPE_8703B(pAdapter) ||
459 IS_HARDWARE_TYPE_8188F(pAdapter)) {
460 u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
461
462 DBG_8192C("===> MPT_ProSetTxPower: Old\n");
463
464 RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n"));
465 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
466 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
467
468 } else {
469 DBG_871X("===> MPT_ProSetTxPower: Jaguar\n");
470 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
471 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
472 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
473 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
474
475 }
476 } else
477 DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
478
479 ODM_ClearTxPowerTrackingState(pDM_Odm);
480
481 }
482
483
hal_mpt_SetDataRate(PADAPTER pAdapter)484 void hal_mpt_SetDataRate(PADAPTER pAdapter)
485 {
486 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
487 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
488 u32 DataRate;
489
490 DataRate = MptToMgntRate(pMptCtx->MptRateIndex);
491
492 hal_mpt_SwitchRfSetting(pAdapter);
493
494 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
495 #ifdef CONFIG_RTL8723B
496 if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
497 if (IS_CCK_RATE(DataRate)) {
498 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
499 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
500 else
501 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
502 } else {
503 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
504 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
505 else
506 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
507 }
508 }
509
510 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
511 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
512 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
513 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
514 else
515 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
516 }
517 #endif
518 }
519
520
521 #define RF_PATH_AB 22
522
523 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)524 VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
525 {
526 u1Byte Path = 0;
527 u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
528
529 for (Path; Path <= ODM_RF_PATH_D; Path++) {
530 switch (Path) {
531 case ODM_RF_PATH_B:
532 IGReg = rB_IGI_Jaguar;
533 break;
534 case ODM_RF_PATH_C:
535 IGReg = rC_IGI_Jaguar2;
536 break;
537 case ODM_RF_PATH_D:
538 IGReg = rD_IGI_Jaguar2;
539 break;
540 default:
541 IGReg = rA_IGI_Jaguar;
542 break;
543 }
544
545 IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);
546 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue+2);
547 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);
548 }
549 }
550
mpt_SetRFPath_8814A(PADAPTER pAdapter)551 VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
552 {
553
554 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
555 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
556 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
557 R_ANTENNA_SELECT_CCK *p_cck_txrx;
558 u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex);
559 u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
560 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
561 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
562
563 u32 ulAntennaTx = pHalData->AntennaTxPath;
564 u32 ulAntennaRx = pHalData->AntennaRxPath;
565 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
566
567 if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) {
568 DBG_871X("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
569
570 switch (ulAntennaTx) {
571 case ANTENNA_BC:
572 pMptCtx->MptRfPath = ODM_RF_PATH_BC;
573 /*pHalData->ValidTxPath = 0x06; linux no use */
574 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/
575 break;
576
577 case ANTENNA_CD:
578 pMptCtx->MptRfPath = ODM_RF_PATH_CD;
579 /*pHalData->ValidTxPath = 0x0C;*/
580 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/
581 break;
582 case ANTENNA_AB: default:
583 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
584 /*pHalData->ValidTxPath = 0x03;*/
585 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/
586 break;
587 }
588
589 } else if (NssforRate == RF_3TX) {
590 DBG_871X("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
591
592 switch (ulAntennaTx) {
593 case ANTENNA_BCD:
594 pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
595 /*pHalData->ValidTxPath = 0x0e;*/
596 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
597 break;
598
599 case ANTENNA_ABC: default:
600 pMptCtx->MptRfPath = ODM_RF_PATH_ABC;
601 /*pHalData->ValidTxPath = 0x0d;*/
602 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
603 break;
604 }
605
606 } else { /*/if(NssforRate == RF_1TX)*/
607 DBG_871X("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
608 switch (ulAntennaTx) {
609 case ANTENNA_BCD:
610 pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
611 /*pHalData->ValidTxPath = 0x0e;*/
612 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
613 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
614 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
615 break;
616
617 case ANTENNA_BC:
618 pMptCtx->MptRfPath = ODM_RF_PATH_BC;
619 /*pHalData->ValidTxPath = 0x06;*/
620 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
621 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
622 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
623 break;
624 case ANTENNA_B:
625 pMptCtx->MptRfPath = ODM_RF_PATH_B;
626 /*pHalData->ValidTxPath = 0x02;*/
627 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
628 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
629 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
630 break;
631
632 case ANTENNA_C:
633 pMptCtx->MptRfPath = ODM_RF_PATH_C;
634 /*pHalData->ValidTxPath = 0x04;*/
635 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
636 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
637 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
638 break;
639
640 case ANTENNA_D:
641 pMptCtx->MptRfPath = ODM_RF_PATH_D;
642 /*pHalData->ValidTxPath = 0x08;*/
643 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
644 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
645 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
646 break;
647
648 case ANTENNA_A: default:
649 pMptCtx->MptRfPath = ODM_RF_PATH_A;
650 /*pHalData->ValidTxPath = 0x01;*/
651 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
652 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
653 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
654 break;
655 }
656 }
657
658 switch (ulAntennaRx) {
659 case ANTENNA_A:
660 /*pHalData->ValidRxPath = 0x01;*/
661 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
662 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
663 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
664 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
665 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
666 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
667 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
668 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
669 /*/ CCA related PD_delay_th*/
670 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
671 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
672 break;
673
674 case ANTENNA_B:
675 /*pHalData->ValidRxPath = 0x02;*/
676 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
677 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
678 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
679 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
680 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
681 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
682 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
683 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
684 /*/ CCA related PD_delay_th*/
685 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
686 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
687 break;
688
689 case ANTENNA_C:
690 /*pHalData->ValidRxPath = 0x04;*/
691 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
692 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
693 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
694 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
695 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
696 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
697 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
698 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
699 /*/ CCA related PD_delay_th*/
700 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
701 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
702 break;
703
704 case ANTENNA_D:
705 /*pHalData->ValidRxPath = 0x08;*/
706 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
707 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
708 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
709 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
710 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
711 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
712 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
713 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
714 /*/ CCA related PD_delay_th*/
715 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
716 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
717 break;
718
719 case ANTENNA_BC:
720 /*pHalData->ValidRxPath = 0x06;*/
721 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
722 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
723 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
724 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
725 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
726 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
727 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
728 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
729 /*/ CCA related PD_delay_th*/
730 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
731 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
732 break;
733
734 case ANTENNA_CD:
735 /*pHalData->ValidRxPath = 0x0C;*/
736 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
737 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
738 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
739 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
740 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
741 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
742 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
743 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
744 /*/ CCA related PD_delay_th*/
745 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
746 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
747 break;
748
749 case ANTENNA_BCD:
750 /*pHalData->ValidRxPath = 0x0e;*/
751 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
752 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
753 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
754 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
755 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
756 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
757 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
758 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
759 /*/ CCA related PD_delay_th*/
760 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
761 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
762 break;
763
764 case ANTENNA_ABCD:
765 /*pHalData->ValidRxPath = 0x0f;*/
766 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
767 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
768 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
769 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
770 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
771 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
772 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
773 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
774 /*/ CCA related PD_delay_th*/
775 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
776 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
777 break;
778
779 default:
780 RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n"));
781 break;
782 }
783
784 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
785
786 mpt_ToggleIG_8814A(pAdapter);
787 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
788 }
789
790 VOID
mpt_SetSingleTone_8814A(IN PADAPTER pAdapter,IN BOOLEAN bSingleTone,IN BOOLEAN bEnPMacTx)791 mpt_SetSingleTone_8814A(
792 IN PADAPTER pAdapter,
793 IN BOOLEAN bSingleTone,
794 IN BOOLEAN bEnPMacTx)
795 {
796
797 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
798 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A;
799 static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
800
801 if (bSingleTone) {
802 regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
803 regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
804 regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
805 regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
806
807 switch (pMptCtx->MptRfPath) {
808 case ODM_RF_PATH_A: case ODM_RF_PATH_B:
809 case ODM_RF_PATH_C: case ODM_RF_PATH_D:
810 StartPath = pMptCtx->MptRfPath;
811 EndPath = pMptCtx->MptRfPath;
812 break;
813 case ODM_RF_PATH_AB:
814 EndPath = ODM_RF_PATH_B;
815 break;
816 case ODM_RF_PATH_BC:
817 StartPath = ODM_RF_PATH_B;
818 EndPath = ODM_RF_PATH_C;
819 break;
820 case ODM_RF_PATH_ABC:
821 EndPath = ODM_RF_PATH_C;
822 break;
823 case ODM_RF_PATH_BCD:
824 StartPath = ODM_RF_PATH_B;
825 EndPath = ODM_RF_PATH_D;
826 break;
827 case ODM_RF_PATH_ABCD:
828 EndPath = ODM_RF_PATH_D;
829 break;
830 }
831
832 if (bEnPMacTx == FALSE) {
833 hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);
834 issue_nulldata(pAdapter, NULL, 1, 3, 500);
835 }
836
837 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
838
839 for (StartPath; StartPath <= EndPath; StartPath++) {
840 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
841 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
842
843 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
844 }
845
846 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
847 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
848 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
849 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
850
851 } else {
852
853 switch (pMptCtx->MptRfPath) {
854 case ODM_RF_PATH_A: case ODM_RF_PATH_B:
855 case ODM_RF_PATH_C: case ODM_RF_PATH_D:
856 StartPath = pMptCtx->MptRfPath;
857 EndPath = pMptCtx->MptRfPath;
858 break;
859 case ODM_RF_PATH_AB:
860 EndPath = ODM_RF_PATH_B;
861 break;
862 case ODM_RF_PATH_BC:
863 StartPath = ODM_RF_PATH_B;
864 EndPath = ODM_RF_PATH_C;
865 break;
866 case ODM_RF_PATH_ABC:
867 EndPath = ODM_RF_PATH_C;
868 break;
869 case ODM_RF_PATH_BCD:
870 StartPath = ODM_RF_PATH_B;
871 EndPath = ODM_RF_PATH_D;
872 break;
873 case ODM_RF_PATH_ABCD:
874 EndPath = ODM_RF_PATH_D;
875 break;
876 }
877
878 for (StartPath; StartPath <= EndPath; StartPath++)
879 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /*// RF LO disabled*/
880
881
882 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
883
884 if (bEnPMacTx == FALSE)
885 hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);
886
887 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
888 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
889 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
890 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
891 }
892 }
893
894 #endif
895
896 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)897 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
898 {
899 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
900 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
901 u32 ulAntennaTx, ulAntennaRx;
902
903 ulAntennaTx = pHalData->AntennaTxPath;
904 ulAntennaRx = pHalData->AntennaRxPath;
905
906 switch (ulAntennaTx) {
907 case ANTENNA_A:
908 pMptCtx->MptRfPath = ODM_RF_PATH_A;
909 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
910 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
911 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
912 break;
913 case ANTENNA_B:
914 pMptCtx->MptRfPath = ODM_RF_PATH_B;
915 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
916 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
917 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
918 break;
919 case ANTENNA_AB:
920 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
921 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
922 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
923 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
924 break;
925 default:
926 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
927 DBG_871X("Unknown Tx antenna.\n");
928 break;
929 }
930
931 switch (ulAntennaRx) {
932 u32 reg0xC50 = 0;
933 case ANTENNA_A:
934 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
935 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
936 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
937 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3);
938
939 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
940 reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
941 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50+2);
942 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
943 break;
944 case ANTENNA_B:
945 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
946 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
947 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
948 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3);
949
950 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
951 reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
952 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50+2);
953 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
954 break;
955 case ANTENNA_AB:
956 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
957 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
958 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
959 break;
960 default:
961 DBG_871X("Unknown Rx antenna.\n");
962 break;
963 }
964 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
965 }
966 #endif
967
968
969 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)970 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
971 {
972 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
973 u8 p = 0, i = 0;
974 u32 ulAntennaTx, ulAntennaRx;
975 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
976 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
977 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
978
979 ulAntennaTx = pHalData->AntennaTxPath;
980 ulAntennaRx = pHalData->AntennaRxPath;
981
982 if (pHalData->rf_chip >= RF_TYPE_MAX) {
983 DBG_8192C("This RF chip ID is not supported\n");
984 return;
985 }
986
987 switch (pAdapter->mppriv.antenna_tx) {
988 case ANTENNA_A: /*/ Actually path S1 (Wi-Fi)*/
989 {
990 pMptCtx->MptRfPath = ODM_RF_PATH_A;
991 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);
992 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
993
994 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
995 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
996 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
997 else
998 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
999
1000
1001 for (i = 0; i < 3; ++i) {
1002 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1003 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
1004
1005 if (offset != 0) {
1006 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1007 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1008 }
1009
1010 }
1011 for (i = 0; i < 2; ++i) {
1012 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1013 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
1014
1015 if (offset != 0) {
1016 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1017 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1018 }
1019 }
1020 }
1021 break;
1022 case ANTENNA_B: /*/ Actually path S0 (BT)*/
1023 {
1024 u4Byte offset;
1025 u4Byte data;
1026
1027 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1028 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);
1029 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1030
1031 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1032 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1033 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1034 else
1035 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1036
1037 for (i = 0; i < 3; ++i) {
1038 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1039 offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1040 data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
1041 if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1042 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1043 DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1044 }
1045 }
1046 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1047 for (i = 0; i < 2; ++i) {
1048 offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1049 data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
1050
1051 if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1052 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1053 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1054 }
1055 }
1056 }
1057 break;
1058 default:
1059 pMptCtx->MptRfPath = RF_PATH_AB;
1060 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1061 break;
1062 }
1063 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1064 }
1065 #endif
1066
1067 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1068 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1069 {
1070 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1071 u1Byte p = 0, i = 0;
1072 u4Byte ulAntennaTx, ulAntennaRx;
1073 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1074 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1075 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1076
1077 ulAntennaTx = pHalData->AntennaTxPath;
1078 ulAntennaRx = pHalData->AntennaRxPath;
1079
1080 if (pHalData->rf_chip >= RF_TYPE_MAX) {
1081 DBG_871X("This RF chip ID is not supported\n");
1082 return;
1083 }
1084
1085 switch (pAdapter->mppriv.antenna_tx) {
1086 case ANTENNA_A: /* Actually path S1 (Wi-Fi) */
1087 {
1088 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1089 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);
1090 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1091
1092 for (i = 0; i < 3; ++i) {
1093 u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1094 u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1095
1096 if (offset != 0) {
1097 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1098 DBG_871X("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1099 }
1100
1101 }
1102 for (i = 0; i < 2; ++i) {
1103 u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1104 u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1105
1106 if (offset != 0) {
1107 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1108 DBG_871X("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1109 }
1110 }
1111 }
1112 break;
1113 case ANTENNA_B: /* Actually path S0 (BT)*/
1114 {
1115 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1116 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);
1117 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1118
1119 for (i = 0; i < 3; ++i) {
1120 u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1121 u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1122
1123 if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) {
1124 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1125 DBG_871X("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1126 }
1127 }
1128 for (i = 0; i < 2; ++i) {
1129 u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1130 u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1131
1132 if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) {
1133 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1134 DBG_871X("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1135 }
1136 }
1137 }
1138 break;
1139 default:
1140 pMptCtx->MptRfPath = RF_PATH_AB;
1141 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1142 break;
1143 }
1144
1145 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1146 }
1147 #endif
1148
1149
mpt_SetRFPath_819X(PADAPTER pAdapter)1150 VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
1151 {
1152 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1153 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1154 u4Byte ulAntennaTx, ulAntennaRx;
1155 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1156 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1157 u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1158 u1Byte chgTx = 0, chgRx = 0;
1159 u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1160
1161 ulAntennaTx = pHalData->AntennaTxPath;
1162 ulAntennaRx = pHalData->AntennaRxPath;
1163
1164 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1165 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1166
1167 p_ofdm_tx->r_ant_ht1 = 0x1;
1168 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1169 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1170
1171 switch (ulAntennaTx) {
1172 case ANTENNA_A:
1173 p_ofdm_tx->r_tx_antenna = 0x1;
1174 r_ofdm_tx_en_val = 0x1;
1175 p_ofdm_tx->r_ant_l = 0x1;
1176 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1177 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1178 p_cck_txrx->r_ccktx_enable = 0x8;
1179 chgTx = 1;
1180 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1181 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1182 {
1183 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1184 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1185 r_ofdm_tx_en_val = 0x3;
1186 /*/ Power save*/
1187 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1188 /*/ We need to close RFB by SW control*/
1189 if (pHalData->rf_type == RF_2T2R) {
1190 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1191 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1192 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1193 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1194 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1195 }
1196 }
1197 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1198 break;
1199 case ANTENNA_B:
1200 p_ofdm_tx->r_tx_antenna = 0x2;
1201 r_ofdm_tx_en_val = 0x2;
1202 p_ofdm_tx->r_ant_l = 0x2;
1203 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1204 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1205 p_cck_txrx->r_ccktx_enable = 0x4;
1206 chgTx = 1;
1207 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1208 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1209 {
1210 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1211 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1212
1213 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1214 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1215 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1216 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1217 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1218 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1219 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1220 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1221 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1222 }
1223 }
1224 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1225 break;
1226 case ANTENNA_AB:/*/ For 8192S*/
1227 p_ofdm_tx->r_tx_antenna = 0x3;
1228 r_ofdm_tx_en_val = 0x3;
1229 p_ofdm_tx->r_ant_l = 0x3;
1230 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1231 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1232 p_cck_txrx->r_ccktx_enable = 0xC;
1233 chgTx = 1;
1234 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1235 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1236 {
1237 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1238 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1239 /* Disable Power save*/
1240 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1241 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1242 if (pHalData->rf_type == RF_2T2R) {
1243 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1244
1245 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1246 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1247 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1248 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1249 }
1250 }
1251 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
1252 break;
1253 default:
1254 break;
1255 }
1256
1257
1258
1259 /*// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
1260 // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
1261 // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1262 switch (ulAntennaRx) {
1263 case ANTENNA_A:
1264 r_rx_antenna_ofdm = 0x1; /* A*/
1265 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1266 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1267 chgRx = 1;
1268 break;
1269 case ANTENNA_B:
1270 r_rx_antenna_ofdm = 0x2; /*/ B*/
1271 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1272 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1273 chgRx = 1;
1274 break;
1275 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1276 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1277 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1278 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1279 chgRx = 1;
1280 break;
1281 default:
1282 break;
1283 }
1284
1285
1286 if (chgTx && chgRx) {
1287 switch (pHalData->rf_chip) {
1288 case RF_8225:
1289 case RF_8256:
1290 case RF_6052:
1291 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1292 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1293 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1294 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1295 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1296 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1297 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1298 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1299 }
1300 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1301 break;
1302
1303 default:
1304 DBG_871X("Unsupported RFChipID for switching antenna.\n");
1305 break;
1306 }
1307 }
1308 } /* MPT_ProSetRFPath */
1309
1310
hal_mpt_SetAntenna(PADAPTER pAdapter)1311 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1312
1313 {
1314 DBG_871X("Do %s\n", __func__);
1315 #ifdef CONFIG_RTL8814A
1316 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1317 mpt_SetRFPath_8814A(pAdapter);
1318 return;
1319 }
1320 #endif
1321 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1322 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1323 mpt_SetRFPath_8812A(pAdapter);
1324 return;
1325 }
1326 #endif
1327 #ifdef CONFIG_RTL8723B
1328 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1329 mpt_SetRFPath_8723B(pAdapter);
1330 return;
1331 }
1332 #endif
1333 #ifdef CONFIG_RTL8703B
1334 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1335 mpt_SetRFPath_8703B(pAdapter);
1336 return;
1337 }
1338 #endif
1339
1340 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1341 mpt_SetRFPath_8821B(pAdapter);
1342 Prepare for 8822B
1343 else if (IS_HARDWARE_TYPE_8822B(Context))
1344 mpt_SetRFPath_8822B(Context);
1345 */
1346 mpt_SetRFPath_819X(pAdapter);
1347 DBG_871X("mpt_SetRFPath_819X Do %s\n", __func__);
1348
1349 }
1350
1351
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1352 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1353 {
1354 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1355
1356 if (!netif_running(pAdapter->pnetdev)) {
1357 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
1358 return _FAIL;
1359 }
1360
1361
1362 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1363 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
1364 return _FAIL;
1365 }
1366
1367
1368 target_ther &= 0xff;
1369 if (target_ther < 0x07)
1370 target_ther = 0x07;
1371 else if (target_ther > 0x1d)
1372 target_ther = 0x1d;
1373
1374 pHalData->EEPROMThermalMeter = target_ther;
1375
1376 return _SUCCESS;
1377 }
1378
1379
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1380 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1381 {
1382 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1383
1384 }
1385
1386
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)1387 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1388
1389 {
1390 u32 ThermalValue = 0;
1391
1392 ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
1393 return (u8)ThermalValue;
1394
1395 }
1396
1397
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 * value)1398 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1399 {
1400 #if 0
1401 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1402 rtw_msleep_os(1000);
1403 fw_cmd_data(pAdapter, value, 1);
1404 *value &= 0xFF;
1405 #else
1406 hal_mpt_TriggerRFThermalMeter(pAdapter);
1407 rtw_msleep_os(1000);
1408 *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1409 #endif
1410
1411 }
1412
1413
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1414 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1415 {
1416 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1417
1418 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
1419
1420 if (bStart) {/*/ Start Single Carrier.*/
1421 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
1422 /*/ Start Single Carrier.*/
1423 /*/ 1. if OFDM block on?*/
1424 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1425 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1426
1427 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1428 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1429
1430 /*/ 3. turn on scramble setting*/
1431 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1432
1433 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1434 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
1435 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1436 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);
1437 else
1438 #endif
1439 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);
1440
1441 } else {
1442 /*/ Stop Single Carrier.*/
1443 /*/ Stop Single Carrier.*/
1444 /*/ Turn off all test modes.*/
1445 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
1446 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1447 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1448 else
1449 #endif
1450
1451 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1452
1453 rtw_msleep_os(10);
1454 /*/BB Reset*/
1455 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1456 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1457 }
1458 }
1459
1460
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1461 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1462 {
1463 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1464 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1465 u4Byte ulAntennaTx = pHalData->AntennaTxPath;
1466 static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1467 u8 rfPath;
1468
1469 switch (ulAntennaTx) {
1470 case ANTENNA_B:
1471 rfPath = ODM_RF_PATH_B;
1472 break;
1473 case ANTENNA_C:
1474 rfPath = ODM_RF_PATH_C;
1475 break;
1476 case ANTENNA_D:
1477 rfPath = ODM_RF_PATH_D;
1478 break;
1479 case ANTENNA_A:
1480 default:
1481 rfPath = ODM_RF_PATH_A;
1482 break;
1483 }
1484
1485 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
1486 if (bStart) {
1487 /*/ Start Single Tone.*/
1488 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1489 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1490 regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
1491
1492 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1493 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1494 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1495 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1496 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1497 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);
1498 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1499 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1500 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1501 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1502 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1503 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1504 } else {
1505 /*/ S0/S1 both use PATH A to configure*/
1506 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1507 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1508 }
1509 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1510 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1511 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1512 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1513 }
1514 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1515 /*Set BB REG 88C: Prevent SingleTone Fail*/
1516 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1517 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1);
1518 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2);
1519
1520 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1521 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1522 u1Byte p = ODM_RF_PATH_A;
1523
1524 regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1525 regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1526 regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1527 regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);
1528 regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);
1529
1530 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); /*/ Disable CCK and OFDM*/
1531
1532 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1533 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1534 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1535 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1536 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1537 }
1538 } else {
1539 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1540 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1541 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1542 }
1543
1544 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1545 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1546
1547 if (pHalData->ExternalPA_5G) {
1548 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1549 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1550 } else if (pHalData->ExternalPA_2G) {
1551 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1552 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1553 }
1554 #endif
1555 }
1556 #ifdef CONFIG_RTL8814A
1557 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1558 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1559 #endif
1560 else /*/ Turn On SingleTone and turn off the other test modes.*/
1561 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone);
1562
1563 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1564 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1565
1566 } else {/*/ Stop Single Ton e.*/
1567
1568 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1569 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);
1570 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1571 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1572 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1573 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1574 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */
1575 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1576 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);
1577 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1578 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1579
1580 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1581 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1582 } else {
1583 /*/ S0/S1 both use PATH A to configure*/
1584 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1585 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1586 }
1587 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1588
1589 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1590 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1591 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1592 }
1593 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1594 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1595 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/
1596 /*Set BB REG 88C: Prevent SingleTone Fail*/
1597 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1598 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1599 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1600 u1Byte p = ODM_RF_PATH_A;
1601
1602 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); /*/ Disable CCK and OFDM*/
1603
1604 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1605 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1606 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1607 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1608 }
1609 } else {
1610 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1611 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1612 }
1613
1614 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1615 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1616 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB2);
1617 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB3);
1618 #endif
1619 }
1620 #ifdef CONFIG_RTL8814A
1621 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1622 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1623
1624 else/*/ Turn off all test modes.*/
1625 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1626 #endif
1627 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1628 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1629
1630 }
1631 }
1632
1633
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1634 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1635 {
1636 u8 Rate;
1637 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
1638
1639 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1640 if (bStart) {/* Start Carrier Suppression.*/
1641 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
1642 if (Rate <= MPT_RATE_11M) {
1643 /*/ 1. if CCK block on?*/
1644 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1645 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1646
1647 /*/Turn Off All Test Mode*/
1648 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1649 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/* rSingleTone_ContTx_Jaguar*/
1650 else
1651 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1652
1653 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1654 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
1655
1656 /*/Set CCK Tx Test Rate*/
1657 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
1658 }
1659
1660 /*Set for dynamic set Power index*/
1661 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1662 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1663
1664 } else {/* Stop Carrier Suppression.*/
1665 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
1666
1667 if (Rate <= MPT_RATE_11M) {
1668 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1669 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1670
1671 /*BB Reset*/
1672 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1673 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1674 }
1675 /*Stop for dynamic set Power index*/
1676 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1677 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1678 }
1679 DBG_871X("\n MPT_ProSetCarrierSupp() is finished.\n");
1680 }
1681
hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter,u8 bStart)1682 void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
1683 {
1684 u32 cckrate;
1685
1686 if (bStart) {
1687 RT_TRACE(_module_mp_, _drv_alert_,
1688 ("SetCCKContinuousTx: test start\n"));
1689
1690 /*/ 1. if CCK block on?*/
1691 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1692 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1693
1694 /*/Turn Off All Test Mode*/
1695 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1696 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/*rSingleTone_ContTx_Jaguar*/
1697 else
1698 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1699
1700 /*/Set CCK Tx Test Rate*/
1701
1702 cckrate = pAdapter->mppriv.rateidx;
1703
1704 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1705 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1706 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1707
1708 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1709 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/
1710 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1711 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1712 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
1713 }
1714
1715 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1716 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1717
1718 } else {
1719 RT_TRACE(_module_mp_, _drv_info_,
1720 ("SetCCKContinuousTx: test stop\n"));
1721
1722 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/
1723 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1724
1725 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {
1726 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/
1727 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/
1728
1729 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1730 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1731 }
1732
1733 /*/BB Reset*/
1734 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1735 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1736
1737 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1738 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1739 }
1740
1741 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
1742 pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
1743 }
1744
hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter,u8 bStart)1745 void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
1746 {
1747 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1748
1749 if (bStart) {
1750 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/
1751 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1752 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/
1753
1754 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1755 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1756
1757 /*/ 3. turn on scramble setting*/
1758 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1759
1760 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1761 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/
1762 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
1763 }
1764
1765 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1766 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1767 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);/*rSingleTone_ContTx_Jaguar*/
1768 else
1769 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx);
1770
1771 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1772 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1773
1774 } else {
1775 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
1776 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1777 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1778 else
1779 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1780 /*/Delay 10 ms*/
1781 rtw_msleep_os(10);
1782
1783 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1784 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/
1785 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/
1786 }
1787
1788 /*/BB Reset*/
1789 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1790 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1791
1792 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1793 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1794 }
1795
1796 pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
1797 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
1798 }
1799
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)1800 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1801 {
1802 u8 Rate;
1803 RT_TRACE(_module_mp_, _drv_info_,
1804 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
1805
1806 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1807 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
1808
1809 if (Rate <= MPT_RATE_11M)
1810 hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
1811 else if (Rate >= MPT_RATE_6M)
1812 hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
1813 }
1814
1815 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B)
1816 /* for HW TX mode */
mpt_StopCckContTx(PADAPTER pAdapter)1817 static VOID mpt_StopCckContTx(
1818 PADAPTER pAdapter
1819 )
1820 {
1821 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1822 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1823 u1Byte u1bReg;
1824
1825 pMptCtx->bCckContTx = FALSE;
1826 pMptCtx->bOfdmContTx = FALSE;
1827
1828 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1829 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1830
1831 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1832 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
1833 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
1834
1835 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1836 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1837 }
1838
1839 /*BB Reset*/
1840 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1841 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1842
1843 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1844 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1845
1846 } /* mpt_StopCckContTx */
1847
1848
mpt_StopOfdmContTx(PADAPTER pAdapter)1849 static VOID mpt_StopOfdmContTx(
1850 PADAPTER pAdapter
1851 )
1852 {
1853 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1854 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1855 u1Byte u1bReg;
1856 u4Byte data;
1857
1858 pMptCtx->bCckContTx = FALSE;
1859 pMptCtx->bOfdmContTx = FALSE;
1860
1861 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1862 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1863 else
1864 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1865
1866 rtw_mdelay_os(10);
1867
1868 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1869 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
1870 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
1871 }
1872
1873 /*BB Reset*/
1874 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1875 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1876
1877 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1878 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1879 } /* mpt_StopOfdmContTx */
1880
1881
mpt_StartCckContTx(PADAPTER pAdapter)1882 static VOID mpt_StartCckContTx(
1883 PADAPTER pAdapter
1884 )
1885 {
1886 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1887 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1888 u4Byte cckrate;
1889
1890 /* 1. if CCK block on */
1891 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1892 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
1893
1894 /*Turn Off All Test Mode*/
1895 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1896 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1897 else
1898 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1899
1900 cckrate = pAdapter->mppriv.rateidx;
1901
1902 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1903
1904 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
1905 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1906
1907 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1908 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
1909 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1910 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1911 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
1912 }
1913
1914 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1915 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1916
1917 pMptCtx->bCckContTx = TRUE;
1918 pMptCtx->bOfdmContTx = FALSE;
1919
1920 } /* mpt_StartCckContTx */
1921
1922
mpt_StartOfdmContTx(PADAPTER pAdapter)1923 static VOID mpt_StartOfdmContTx(
1924 PADAPTER pAdapter
1925 )
1926 {
1927 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1928 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1929
1930 /* 1. if OFDM block on?*/
1931 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1932 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
1933
1934 /* 2. set CCK test mode off, set to CCK normal mode*/
1935 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1936
1937 /* 3. turn on scramble setting*/
1938 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1939
1940 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1941 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
1942 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
1943 }
1944
1945 /* 4. Turn On Continue Tx and turn off the other test modes.*/
1946 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1947 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);
1948 else
1949 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx);
1950
1951 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1952 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1953
1954 pMptCtx->bCckContTx = FALSE;
1955 pMptCtx->bOfdmContTx = TRUE;
1956 } /* mpt_StartOfdmContTx */
1957
1958
mpt_ProSetPMacTx(PADAPTER Adapter)1959 void mpt_ProSetPMacTx(PADAPTER Adapter)
1960 {
1961 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
1962 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1963 u32 u4bTmp;
1964
1965 DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
1966 DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
1967 #if 0
1968 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
1969 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
1970 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
1971 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
1972 DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
1973 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
1974
1975 PRINT_DATA("Src Address", Adapter->mac_addr, 6);
1976 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
1977 #endif
1978
1979 if (PMacTxInfo.bEnPMacTx == FALSE) {
1980 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
1981 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
1982 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1983 mpt_StopCckContTx(Adapter);
1984 else
1985 mpt_StopOfdmContTx(Adapter);
1986 } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
1987 u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord);
1988 PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp+50);
1989 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
1990 } else
1991 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
1992
1993 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
1994 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
1995 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1996 mpt_StopCckContTx(Adapter);
1997 else
1998 mpt_StopOfdmContTx(Adapter);
1999
2000 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2001 }
2002
2003 return;
2004 }
2005
2006 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2007 PMacTxInfo.PacketCount = 1;
2008
2009 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2010 mpt_StartCckContTx(Adapter);
2011 else
2012 mpt_StartOfdmContTx(Adapter);
2013 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2014 /* Continuous TX -> HW TX -> RF Setting */
2015 PMacTxInfo.PacketCount = 1;
2016
2017 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2018 mpt_StartCckContTx(Adapter);
2019 else
2020 mpt_StartOfdmContTx(Adapter);
2021 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2022 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2023 PMacTxInfo.PacketCount = 0xffff;
2024 }
2025
2026 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2027 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2028 u4bTmp = PMacTxInfo.PacketCount|(PMacTxInfo.SFD << 16);
2029 PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2030 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2031 u4bTmp = PMacTxInfo.SignalField|(PMacTxInfo.ServiceField << 8)|(PMacTxInfo.LENGTH << 16);
2032 PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2033 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2034 PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2035
2036 if (PMacTxInfo.bSPreamble)
2037 PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0);
2038 else
2039 PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1);
2040 } else {
2041 PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2042
2043 u4bTmp = PMacTxInfo.LSIG[0]|((PMacTxInfo.LSIG[1]) << 8)|((PMacTxInfo.LSIG[2]) << 16)|((PMacTxInfo.PacketPattern) << 24);
2044 PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2045
2046 if (PMacTxInfo.PacketPattern == 0x12)
2047 u4bTmp = 0x3000000;
2048 else
2049 u4bTmp = 0;
2050 }
2051
2052 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2053 u4bTmp |= PMacTxInfo.HT_SIG[0]|((PMacTxInfo.HT_SIG[1]) << 8)|((PMacTxInfo.HT_SIG[2]) << 16);
2054 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2055 u4bTmp = PMacTxInfo.HT_SIG[3]|((PMacTxInfo.HT_SIG[4]) << 8)|((PMacTxInfo.HT_SIG[5]) << 16);
2056 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2057 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2058 u4bTmp |= PMacTxInfo.VHT_SIG_A[0]|((PMacTxInfo.VHT_SIG_A[1]) << 8)|((PMacTxInfo.VHT_SIG_A[2]) << 16);
2059 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2060 u4bTmp = PMacTxInfo.VHT_SIG_A[3]|((PMacTxInfo.VHT_SIG_A[4]) << 8)|((PMacTxInfo.VHT_SIG_A[5]) << 16);
2061 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2062
2063 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2064 PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2065 }
2066
2067 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2068 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24)|PMacTxInfo.PacketPeriod; /* for TX interval */
2069 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2070
2071 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2072 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2073
2074 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2075 /*& Duration & Frame control*/
2076 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2077
2078 /* Address1 [0:3]*/
2079 u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24);
2080 PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2081
2082 /* Address3 [3:0]*/
2083 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2084
2085 /* Address2[0:1] & Address1 [5:4]*/
2086 u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24);
2087 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2088
2089 /* Address2 [5:2]*/
2090 u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24);
2091 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2092
2093 /* Sequence Control & Address3 [5:4]*/
2094 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2095 /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2096 } else {
2097 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2098 /* & Duration & Frame control */
2099 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2100
2101 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2102 /* Address1 [0:3]*/
2103 u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24);
2104 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2105
2106 /* Address3 [3:0]*/
2107 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2108
2109 /* Address2[0:1] & Address1 [5:4]*/
2110 u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24);
2111 PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2112
2113 /* Address2 [5:2] */
2114 u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24);
2115 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2116
2117 /* Sequence Control & Address3 [5:4]*/
2118 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2119 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2120 }
2121
2122 PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2123
2124 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2125 u4bTmp = (PMacTxInfo.TX_SC)|((PMacTxInfo.BandWidth) << 4)|((PMacTxInfo.m_STBC - 1) << 6)|((PMacTxInfo.NDP_sound) << 8);
2126 PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2127
2128 if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
2129 u4Byte offset = 0xb44;
2130
2131 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2132 PHY_SetBBReg(Adapter, offset, 0xc0000000, 0);
2133 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2134 PHY_SetBBReg(Adapter, offset, 0xc0000000, 1);
2135 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2136 PHY_SetBBReg(Adapter, offset, 0xc0000000, 2);
2137 }
2138
2139 PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2140 /* //PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); //TX Stop*/
2141 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2142 PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2143 PHY_SetBBReg(Adapter, 0xA84, BIT31, 0);
2144 } else
2145 PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2146
2147 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2148 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2149
2150 }
2151 #endif
2152
2153 #endif /* CONFIG_MP_INCLUDE*/
2154
2155