1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 /* ************************************************************
17 * include files
18 * ************************************************************ */
19
20 #include "mp_precomp.h"
21 #include "phydm_precomp.h"
22
23
24 const u16 phy_rate_table[] = { /*20M*/
25 1, 2, 5, 11,
26 6, 9, 12, 18, 24, 36, 48, 54,
27 6, 13, 19, 26, 39, 52, 58, 65, /*MCS0~7*/
28 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/
29 };
30
31 void
phydm_traffic_load_decision(void * p_dm_void)32 phydm_traffic_load_decision(
33 void *p_dm_void
34 )
35 {
36 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
37 u8 bit_shift_num = 0;
38
39 /*---TP & Trafic-load calculation---*/
40
41 if (p_dm->last_tx_ok_cnt > (*(p_dm->p_num_tx_bytes_unicast)))
42 p_dm->last_tx_ok_cnt = (*(p_dm->p_num_tx_bytes_unicast));
43
44 if (p_dm->last_rx_ok_cnt > (*(p_dm->p_num_rx_bytes_unicast)))
45 p_dm->last_rx_ok_cnt = (*(p_dm->p_num_rx_bytes_unicast));
46
47 p_dm->cur_tx_ok_cnt = *(p_dm->p_num_tx_bytes_unicast) - p_dm->last_tx_ok_cnt;
48 p_dm->cur_rx_ok_cnt = *(p_dm->p_num_rx_bytes_unicast) - p_dm->last_rx_ok_cnt;
49 p_dm->last_tx_ok_cnt = *(p_dm->p_num_tx_bytes_unicast);
50 p_dm->last_rx_ok_cnt = *(p_dm->p_num_rx_bytes_unicast);
51
52 bit_shift_num = 17 + (PHYDM_WATCH_DOG_PERIOD - 1); /*AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
53 /*WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
54
55 p_dm->tx_tp = ((p_dm->tx_tp) >> 1) + (u32)(((p_dm->cur_tx_ok_cnt) >> bit_shift_num) >> 1);
56 p_dm->rx_tp = ((p_dm->rx_tp) >> 1) + (u32)(((p_dm->cur_rx_ok_cnt) >> bit_shift_num) >> 1);
57
58 p_dm->total_tp = p_dm->tx_tp + p_dm->rx_tp;
59
60 /*[Calculate TX/RX state]*/
61 if (p_dm->tx_tp > (p_dm->rx_tp << 1))
62 p_dm->txrx_state_all = TX_STATE;
63 else if (p_dm->rx_tp > (p_dm->tx_tp << 1))
64 p_dm->txrx_state_all = RX_STATE;
65 else
66 p_dm->txrx_state_all = BI_DIRECTION_STATE;
67
68 /*[Calculate consecutive idlel time]*/
69 if (p_dm->total_tp == 0)
70 p_dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
71 else
72 p_dm->consecutive_idlel_time = 0;
73
74 /*[Traffic load decision]*/
75 p_dm->pre_traffic_load = p_dm->traffic_load;
76
77 if (p_dm->cur_tx_ok_cnt > 1875000 || p_dm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
78
79 p_dm->traffic_load = TRAFFIC_HIGH;
80 /**/
81 } else if (p_dm->cur_tx_ok_cnt > 500000 || p_dm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
82
83 p_dm->traffic_load = TRAFFIC_MID;
84 /**/
85 } else if (p_dm->cur_tx_ok_cnt > 100000 || p_dm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
86
87 p_dm->traffic_load = TRAFFIC_LOW;
88 /**/
89 } else {
90
91 p_dm->traffic_load = TRAFFIC_ULTRA_LOW;
92 /**/
93 }
94
95 /*
96 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
97 p_dm->cur_tx_ok_cnt, p_dm->cur_rx_ok_cnt, p_dm->last_tx_ok_cnt, p_dm->last_rx_ok_cnt));
98
99 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("tx_tp = %d, rx_tp = %d\n",
100 p_dm->tx_tp, p_dm->rx_tp));
101 */
102
103 }
104
105 void
phydm_init_cck_setting(struct PHY_DM_STRUCT * p_dm)106 phydm_init_cck_setting(
107 struct PHY_DM_STRUCT *p_dm
108 )
109 {
110 #if (RTL8192E_SUPPORT == 1)
111 u32 value_824, value_82c;
112 #endif
113
114 p_dm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm, ODM_REG(CCK_RPT_FORMAT, p_dm), ODM_BIT(CCK_RPT_FORMAT, p_dm));
115
116 phydm_config_cck_rx_antenna_init(p_dm);
117 phydm_config_cck_rx_path(p_dm, BB_PATH_A);
118
119 #if (RTL8192E_SUPPORT == 1)
120 if (p_dm->support_ic_type & (ODM_RTL8192E)) {
121
122 /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */
123 value_824 = odm_get_bb_reg(p_dm, 0x824, BIT(9));
124 value_82c = odm_get_bb_reg(p_dm, 0x82c, BIT(9));
125
126 if (value_824 != value_82c)
127 odm_set_bb_reg(p_dm, 0x82c, BIT(9), value_824);
128 odm_set_bb_reg(p_dm, 0xa80, BIT(7), value_824);
129 p_dm->cck_agc_report_type = (boolean)value_824;
130
131 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm->cck_agc_report_type, p_dm->ext_lna_gain));
132 }
133 #endif
134
135 #if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
136 if (p_dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
137
138 p_dm->cck_agc_report_type = odm_get_bb_reg(p_dm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */
139
140 if (p_dm->cck_agc_report_type != 1) {
141 dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n");
142 /**/
143 }
144 }
145 #endif
146
147 #if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
148 if (p_dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B))
149 p_dm->cck_new_agc = odm_get_bb_reg(p_dm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/
150 else
151 #endif
152 {
153 p_dm->cck_new_agc = false;
154 /**/
155 }
156
157 phydm_get_cck_rssi_table_from_reg(p_dm);
158
159 }
160
161 void
phydm_init_hw_info_by_rfe(struct PHY_DM_STRUCT * p_dm)162 phydm_init_hw_info_by_rfe(
163 struct PHY_DM_STRUCT *p_dm
164 )
165 {
166 #if (RTL8822B_SUPPORT == 1)
167 if (p_dm->support_ic_type & ODM_RTL8822B)
168 phydm_init_hw_info_by_rfe_type_8822b(p_dm);
169 #endif
170 #if (RTL8821C_SUPPORT == 1)
171 if (p_dm->support_ic_type & ODM_RTL8821C)
172 phydm_init_hw_info_by_rfe_type_8821c(p_dm);
173 #endif
174 #if (RTL8197F_SUPPORT == 1)
175 if (p_dm->support_ic_type & ODM_RTL8197F)
176 phydm_init_hw_info_by_rfe_type_8197f(p_dm);
177 #endif
178 }
179
180 void
phydm_common_info_self_init(struct PHY_DM_STRUCT * p_dm)181 phydm_common_info_self_init(
182 struct PHY_DM_STRUCT *p_dm
183 )
184 {
185 phydm_init_cck_setting(p_dm);
186 p_dm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm, ODM_REG(BB_RX_PATH, p_dm), ODM_BIT(BB_RX_PATH, p_dm));
187 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
188 p_dm->p_is_net_closed = &p_dm->BOOLEAN_temp;
189
190 phydm_init_debug_setting(p_dm);
191 #endif
192 phydm_init_trx_antenna_setting(p_dm);
193 phydm_init_soft_ml_setting(p_dm);
194
195 p_dm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
196 p_dm->phydm_sys_up_time = 0;
197
198 if (p_dm->support_ic_type & ODM_IC_1SS)
199 p_dm->num_rf_path = 1;
200 else if (p_dm->support_ic_type & ODM_IC_2SS)
201 p_dm->num_rf_path = 2;
202 else if (p_dm->support_ic_type & ODM_IC_3SS)
203 p_dm->num_rf_path = 3;
204 else if (p_dm->support_ic_type & ODM_IC_4SS)
205 p_dm->num_rf_path = 4;
206
207 p_dm->tx_rate = 0xFF;
208 p_dm->rssi_min_by_path = 0xFF;
209
210 p_dm->number_linked_client = 0;
211 p_dm->pre_number_linked_client = 0;
212 p_dm->number_active_client = 0;
213 p_dm->pre_number_active_client = 0;
214
215 p_dm->last_tx_ok_cnt = 0;
216 p_dm->last_rx_ok_cnt = 0;
217 p_dm->tx_tp = 0;
218 p_dm->rx_tp = 0;
219 p_dm->total_tp = 0;
220 p_dm->traffic_load = TRAFFIC_LOW;
221
222 p_dm->nbi_set_result = 0;
223 p_dm->is_init_hw_info_by_rfe = false;
224 p_dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
225 p_dm->tp_active_th = 5;
226 p_dm->disable_phydm_watchdog = 0;
227
228 p_dm->u8_dummy = 0xf;
229 p_dm->u16_dummy = 0xffff;
230 p_dm->u32_dummy = 0xffffffff;
231
232 /*odm_memory_set(p_dm, &(p_dm->pause_lv_table.lv_dig), 0, sizeof(struct phydm_pause_lv));*/
233 p_dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
234 p_dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
235
236 }
237
238 void
phydm_cmn_sta_info_update(void * p_dm_void,u8 macid)239 phydm_cmn_sta_info_update(
240 void *p_dm_void,
241 u8 macid
242 )
243 {
244 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
245 struct cmn_sta_info *p_sta = p_dm->p_phydm_sta_info[macid];
246 struct ra_sta_info *p_ra = NULL;
247
248 if (is_sta_active(p_sta)) {
249 p_ra = &(p_sta->ra_info);
250 } else {
251 PHYDM_DBG(p_dm, DBG_RA_MASK, ("[Warning] %s invalid sta_info\n", __func__));
252 return;
253 }
254
255 PHYDM_DBG(p_dm, DBG_RA_MASK, ("%s ======>\n", __func__));
256 PHYDM_DBG(p_dm, DBG_RA_MASK, ("MACID=%d\n", p_sta->mac_id));
257
258 /*[Calculate TX/RX state]*/
259 if (p_sta->tx_moving_average_tp > (p_sta->rx_moving_average_tp << 1))
260 p_ra->txrx_state= TX_STATE;
261 else if (p_sta->rx_moving_average_tp > (p_sta->tx_moving_average_tp << 1))
262 p_ra->txrx_state = RX_STATE;
263 else
264 p_ra->txrx_state = BI_DIRECTION_STATE;
265
266 }
267
268 void
phydm_common_info_self_update(struct PHY_DM_STRUCT * p_dm)269 phydm_common_info_self_update(
270 struct PHY_DM_STRUCT *p_dm
271 )
272 {
273 u8 sta_cnt = 0, num_active_client = 0;
274 u32 i, one_entry_macid = 0;
275 u32 ma_rx_tp = 0;
276 struct cmn_sta_info *p_sta;
277
278 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
279
280 struct _ADAPTER *adapter = p_dm->adapter;
281 PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
282
283 p_sta = p_dm->p_phydm_sta_info[0];
284 if (p_mgnt_info->mAssoc) {
285 p_sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
286 for (i = 0; i < 6; i++)
287 p_sta->mac_addr[i] = p_mgnt_info->Bssid[i];
288 } else if (GetFirstClientPort(adapter)) {
289 struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter);
290
291 p_sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
292 for (i = 0; i < 6; i++)
293 p_sta->mac_addr[i] = p_client_adapter->MgntInfo.Bssid[i];
294 } else {
295 p_sta->dm_ctrl = p_sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
296 for (i = 0; i < 6; i++)
297 p_sta->mac_addr[i] = 0;
298 }
299
300 /* STA mode is linked to AP */
301 if (is_sta_active(p_sta) && !ACTING_AS_AP(adapter))
302 p_dm->bsta_state = true;
303 else
304 p_dm->bsta_state = false;
305 #endif
306
307 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
308 p_sta = p_dm->p_phydm_sta_info[i];
309 if (is_sta_active(p_sta)) {
310 sta_cnt++;
311
312 if (sta_cnt == 1)
313 one_entry_macid = i;
314
315 phydm_cmn_sta_info_update(p_dm, (u8)i);
316
317 ma_rx_tp = p_sta->rx_moving_average_tp + p_sta->tx_moving_average_tp;
318 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp));
319
320 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
321 num_active_client++;
322 }
323 }
324
325 if (sta_cnt == 1) {
326 p_dm->is_one_entry_only = true;
327 p_dm->one_entry_macid = one_entry_macid;
328 p_dm->one_entry_tp = ma_rx_tp;
329
330 p_dm->tp_active_occur = 0;
331
332 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
333 p_dm->one_entry_tp, p_dm->pre_one_entry_tp));
334
335 if ((p_dm->one_entry_tp > p_dm->pre_one_entry_tp) && (p_dm->pre_one_entry_tp <= 2)) {
336 if ((p_dm->one_entry_tp - p_dm->pre_one_entry_tp) > p_dm->tp_active_th)
337 p_dm->tp_active_occur = 1;
338 }
339 p_dm->pre_one_entry_tp = p_dm->one_entry_tp;
340 } else
341 p_dm->is_one_entry_only = false;
342
343 p_dm->pre_number_linked_client = p_dm->number_linked_client;
344 p_dm->pre_number_active_client = p_dm->number_active_client;
345
346 p_dm->number_linked_client = sta_cnt;
347 p_dm->number_active_client = num_active_client;
348
349 /*Traffic load information update*/
350 phydm_traffic_load_decision(p_dm);
351
352 p_dm->phydm_sys_up_time += p_dm->phydm_period;
353
354 p_dm->is_dfs_band = phydm_is_dfs_band(p_dm);
355
356 }
357
358 void
phydm_common_info_self_reset(struct PHY_DM_STRUCT * p_dm)359 phydm_common_info_self_reset(
360 struct PHY_DM_STRUCT *p_dm
361 )
362 {
363 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
364 p_dm->phy_dbg_info.num_qry_beacon_pkt = 0;
365 #endif
366 }
367
368 void *
phydm_get_structure(struct PHY_DM_STRUCT * p_dm,u8 structure_type)369 phydm_get_structure(
370 struct PHY_DM_STRUCT *p_dm,
371 u8 structure_type
372 )
373
374 {
375 void *p_struct = NULL;
376 #if RTL8195A_SUPPORT
377 switch (structure_type) {
378 case PHYDM_FALSEALMCNT:
379 p_struct = &false_alm_cnt;
380 break;
381
382 case PHYDM_CFOTRACK:
383 p_struct = &dm_cfo_track;
384 break;
385
386 case PHYDM_ADAPTIVITY:
387 p_struct = &(p_dm->adaptivity);
388 break;
389
390 default:
391 break;
392 }
393
394 #else
395 switch (structure_type) {
396 case PHYDM_FALSEALMCNT:
397 p_struct = &(p_dm->false_alm_cnt);
398 break;
399
400 case PHYDM_CFOTRACK:
401 p_struct = &(p_dm->dm_cfo_track);
402 break;
403
404 case PHYDM_ADAPTIVITY:
405 p_struct = &(p_dm->adaptivity);
406 break;
407
408 case PHYDM_DFS:
409 p_struct = &(p_dm->dfs);
410 break;
411
412 default:
413 break;
414 }
415
416 #endif
417 return p_struct;
418 }
419
420 void
phydm_hw_setting(struct PHY_DM_STRUCT * p_dm)421 phydm_hw_setting(
422 struct PHY_DM_STRUCT *p_dm
423 )
424 {
425 #if (RTL8821A_SUPPORT == 1)
426 if (p_dm->support_ic_type & ODM_RTL8821)
427 odm_hw_setting_8821a(p_dm);
428 #endif
429
430 #if (RTL8814A_SUPPORT == 1)
431 if (p_dm->support_ic_type & ODM_RTL8814A)
432 phydm_hwsetting_8814a(p_dm);
433 #endif
434
435 #if (RTL8822B_SUPPORT == 1)
436 if (p_dm->support_ic_type & ODM_RTL8822B)
437 phydm_hwsetting_8822b(p_dm);
438 #endif
439
440 #if (RTL8197F_SUPPORT == 1)
441 if (p_dm->support_ic_type & ODM_RTL8197F)
442 phydm_hwsetting_8197f(p_dm);
443 #endif
444 }
445
446
447 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
448 u64
phydm_supportability_init_win(void * p_dm_void)449 phydm_supportability_init_win(
450 void *p_dm_void
451 )
452 {
453 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
454 u64 support_ability = 0;
455
456 switch (p_dm->support_ic_type) {
457
458 /*---------------N Series--------------------*/
459 #if (RTL8188E_SUPPORT == 1)
460 case ODM_RTL8188E:
461 support_ability |=
462 ODM_BB_DIG |
463 ODM_BB_RA_MASK |
464 /*ODM_BB_DYNAMIC_TXPWR |*/
465 ODM_BB_FA_CNT |
466 ODM_BB_RSSI_MONITOR |
467 ODM_BB_CCK_PD |
468 /*ODM_BB_PWR_TRAIN |*/
469 ODM_BB_RATE_ADAPTIVE |
470 ODM_BB_CFO_TRACKING |
471 ODM_BB_ENV_MONITOR |
472 ODM_BB_PRIMARY_CCA;
473 break;
474 #endif
475
476 #if (RTL8192E_SUPPORT == 1)
477 case ODM_RTL8192E:
478 support_ability |=
479 ODM_BB_DIG |
480 ODM_BB_RA_MASK |
481 /*ODM_BB_DYNAMIC_TXPWR |*/
482 ODM_BB_FA_CNT |
483 ODM_BB_RSSI_MONITOR |
484 ODM_BB_CCK_PD |
485 /*ODM_BB_PWR_TRAIN |*/
486 ODM_BB_RATE_ADAPTIVE |
487 ODM_BB_CFO_TRACKING |
488 ODM_BB_ENV_MONITOR |
489 ODM_BB_PRIMARY_CCA;
490 break;
491 #endif
492
493 #if (RTL8723B_SUPPORT == 1)
494 case ODM_RTL8723B:
495 support_ability |=
496 ODM_BB_DIG |
497 ODM_BB_RA_MASK |
498 /*ODM_BB_DYNAMIC_TXPWR |*/
499 ODM_BB_FA_CNT |
500 ODM_BB_RSSI_MONITOR |
501 ODM_BB_CCK_PD |
502 /*ODM_BB_PWR_TRAIN |*/
503 ODM_BB_RATE_ADAPTIVE |
504 ODM_BB_CFO_TRACKING |
505 ODM_BB_ENV_MONITOR |
506 ODM_BB_PRIMARY_CCA;
507 break;
508 #endif
509
510 #if (RTL8703B_SUPPORT == 1)
511 case ODM_RTL8703B:
512 support_ability |=
513 ODM_BB_DIG |
514 ODM_BB_RA_MASK |
515 /*ODM_BB_DYNAMIC_TXPWR |*/
516 ODM_BB_FA_CNT |
517 ODM_BB_RSSI_MONITOR |
518 ODM_BB_CCK_PD |
519 /*ODM_BB_PWR_TRAIN |*/
520 ODM_BB_RATE_ADAPTIVE |
521 ODM_BB_CFO_TRACKING |
522 ODM_BB_ENV_MONITOR;
523 break;
524 #endif
525
526 #if (RTL8723D_SUPPORT == 1)
527 case ODM_RTL8723D:
528 support_ability |=
529 ODM_BB_DIG |
530 ODM_BB_RA_MASK |
531 /*ODM_BB_DYNAMIC_TXPWR |*/
532 ODM_BB_FA_CNT |
533 ODM_BB_RSSI_MONITOR |
534 ODM_BB_CCK_PD |
535 /* ODM_BB_PWR_TRAIN | */
536 ODM_BB_RATE_ADAPTIVE |
537 ODM_BB_CFO_TRACKING |
538 ODM_BB_ENV_MONITOR;
539 break;
540 #endif
541
542 #if (RTL8710B_SUPPORT == 1)
543 case ODM_RTL8710B:
544 support_ability |=
545 ODM_BB_DIG |
546 ODM_BB_RA_MASK |
547 /*ODM_BB_DYNAMIC_TXPWR |*/
548 ODM_BB_FA_CNT |
549 ODM_BB_RSSI_MONITOR |
550 ODM_BB_CCK_PD |
551 /*ODM_BB_PWR_TRAIN |*/
552 ODM_BB_RATE_ADAPTIVE |
553 ODM_BB_CFO_TRACKING |
554 ODM_BB_ENV_MONITOR;
555 break;
556 #endif
557
558 #if (RTL8188F_SUPPORT == 1)
559 case ODM_RTL8188F:
560 support_ability |=
561 ODM_BB_DIG |
562 ODM_BB_RA_MASK |
563 /*ODM_BB_DYNAMIC_TXPWR |*/
564 ODM_BB_FA_CNT |
565 ODM_BB_RSSI_MONITOR |
566 ODM_BB_CCK_PD |
567 /*ODM_BB_PWR_TRAIN |*/
568 ODM_BB_RATE_ADAPTIVE |
569 ODM_BB_CFO_TRACKING |
570 ODM_BB_ENV_MONITOR;
571 break;
572 #endif
573
574 /*---------------AC Series-------------------*/
575
576 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
577 case ODM_RTL8812:
578 case ODM_RTL8821:
579 support_ability |=
580 ODM_BB_DIG |
581 ODM_BB_RA_MASK |
582 ODM_BB_DYNAMIC_TXPWR |
583 ODM_BB_FA_CNT |
584 ODM_BB_RSSI_MONITOR |
585 ODM_BB_CCK_PD |
586 /*ODM_BB_PWR_TRAIN |*/
587 ODM_BB_RATE_ADAPTIVE |
588 ODM_BB_CFO_TRACKING |
589 ODM_BB_ENV_MONITOR;
590 break;
591 #endif
592
593 #if (RTL8814A_SUPPORT == 1)
594 case ODM_RTL8814A:
595 support_ability |=
596 ODM_BB_DIG |
597 ODM_BB_RA_MASK |
598 ODM_BB_DYNAMIC_TXPWR |
599 ODM_BB_FA_CNT |
600 ODM_BB_RSSI_MONITOR |
601 ODM_BB_CCK_PD |
602 /*ODM_BB_PWR_TRAIN |*/
603 ODM_BB_RATE_ADAPTIVE |
604 ODM_BB_CFO_TRACKING |
605 ODM_BB_ENV_MONITOR;
606 break;
607 #endif
608
609 #if (RTL8814B_SUPPORT == 1)
610 case ODM_RTL8814B:
611 support_ability |=
612 ODM_BB_DIG |
613 ODM_BB_RA_MASK |
614 /*ODM_BB_DYNAMIC_TXPWR |*/
615 ODM_BB_FA_CNT |
616 ODM_BB_RSSI_MONITOR |
617 ODM_BB_CCK_PD |
618 /*ODM_BB_PWR_TRAIN |*/
619 ODM_BB_RATE_ADAPTIVE |
620 ODM_BB_CFO_TRACKING |
621 ODM_BB_ENV_MONITOR;
622 break;
623 #endif
624
625 #if (RTL8822B_SUPPORT == 1)
626 case ODM_RTL8822B:
627 support_ability |=
628 ODM_BB_DIG |
629 ODM_BB_RA_MASK |
630 /*ODM_BB_DYNAMIC_TXPWR |*/
631 ODM_BB_FA_CNT |
632 ODM_BB_RSSI_MONITOR |
633 ODM_BB_CCK_PD |
634 /*ODM_BB_PWR_TRAIN |*/
635 ODM_BB_RATE_ADAPTIVE |
636 ODM_BB_CFO_TRACKING |
637 ODM_BB_ENV_MONITOR |
638 ODM_BB_ADAPTIVE_SOML;
639 break;
640 #endif
641
642 #if (RTL8821C_SUPPORT == 1)
643 case ODM_RTL8821C:
644 support_ability |=
645 ODM_BB_DIG |
646 ODM_BB_RA_MASK |
647 /*ODM_BB_DYNAMIC_TXPWR |*/
648 ODM_BB_FA_CNT |
649 ODM_BB_RSSI_MONITOR |
650 ODM_BB_CCK_PD |
651 /*ODM_BB_PWR_TRAIN |*/
652 ODM_BB_RATE_ADAPTIVE |
653 ODM_BB_CFO_TRACKING |
654 ODM_BB_ENV_MONITOR;
655 break;
656 #endif
657
658 default:
659 support_ability |=
660 ODM_BB_DIG |
661 ODM_BB_RA_MASK |
662 /*ODM_BB_DYNAMIC_TXPWR |*/
663 ODM_BB_FA_CNT |
664 ODM_BB_RSSI_MONITOR |
665 ODM_BB_CCK_PD |
666 /*ODM_BB_PWR_TRAIN |*/
667 ODM_BB_RATE_ADAPTIVE |
668 ODM_BB_CFO_TRACKING |
669 ODM_BB_ENV_MONITOR;
670
671 dbg_print("[Warning] Supportability Init Warning !!!\n");
672 break;
673
674 }
675
676 /*[Config Antenna Diveristy]*/
677 if (*(p_dm->p_enable_antdiv))
678 support_ability |= ODM_BB_ANT_DIV;
679
680 /*[Config Adaptivity]*/
681 if (*(p_dm->p_enable_adaptivity))
682 support_ability |= ODM_BB_ADAPTIVITY;
683
684 return support_ability;
685 }
686 #endif
687
688 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
689 u64
phydm_supportability_init_ce(void * p_dm_void)690 phydm_supportability_init_ce(
691 void *p_dm_void
692 )
693 {
694 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
695 u64 support_ability = 0;
696
697 switch (p_dm->support_ic_type) {
698
699 /*---------------N Series--------------------*/
700 #if (RTL8188E_SUPPORT == 1)
701 case ODM_RTL8188E:
702 support_ability |=
703 ODM_BB_DIG |
704 ODM_BB_RA_MASK |
705 /*ODM_BB_DYNAMIC_TXPWR |*/
706 ODM_BB_FA_CNT |
707 ODM_BB_RSSI_MONITOR |
708 ODM_BB_CCK_PD |
709 /*ODM_BB_PWR_TRAIN |*/
710 ODM_BB_RATE_ADAPTIVE |
711 ODM_BB_CFO_TRACKING |
712 ODM_BB_ENV_MONITOR |
713 ODM_BB_PRIMARY_CCA;
714 break;
715 #endif
716
717 #if (RTL8192E_SUPPORT == 1)
718 case ODM_RTL8192E:
719 support_ability |=
720 ODM_BB_DIG |
721 ODM_BB_RA_MASK |
722 /*ODM_BB_DYNAMIC_TXPWR |*/
723 ODM_BB_FA_CNT |
724 ODM_BB_RSSI_MONITOR |
725 ODM_BB_CCK_PD |
726 /*ODM_BB_PWR_TRAIN |*/
727 ODM_BB_RATE_ADAPTIVE |
728 ODM_BB_CFO_TRACKING |
729 ODM_BB_ENV_MONITOR |
730 ODM_BB_PRIMARY_CCA;
731 break;
732 #endif
733
734 #if (RTL8723B_SUPPORT == 1)
735 case ODM_RTL8723B:
736 support_ability |=
737 ODM_BB_DIG |
738 ODM_BB_RA_MASK |
739 /*ODM_BB_DYNAMIC_TXPWR |*/
740 ODM_BB_FA_CNT |
741 ODM_BB_RSSI_MONITOR |
742 ODM_BB_CCK_PD |
743 /*ODM_BB_PWR_TRAIN |*/
744 ODM_BB_RATE_ADAPTIVE |
745 ODM_BB_CFO_TRACKING |
746 ODM_BB_ENV_MONITOR |
747 ODM_BB_PRIMARY_CCA;
748 break;
749 #endif
750
751 #if (RTL8703B_SUPPORT == 1)
752 case ODM_RTL8703B:
753 support_ability |=
754 ODM_BB_DIG |
755 ODM_BB_RA_MASK |
756 /*ODM_BB_DYNAMIC_TXPWR |*/
757 ODM_BB_FA_CNT |
758 ODM_BB_RSSI_MONITOR |
759 ODM_BB_CCK_PD |
760 /*ODM_BB_PWR_TRAIN |*/
761 ODM_BB_RATE_ADAPTIVE |
762 ODM_BB_CFO_TRACKING |
763 ODM_BB_ENV_MONITOR;
764 break;
765 #endif
766
767 #if (RTL8723D_SUPPORT == 1)
768 case ODM_RTL8723D:
769 support_ability |=
770 ODM_BB_DIG |
771 ODM_BB_RA_MASK |
772 /*ODM_BB_DYNAMIC_TXPWR |*/
773 ODM_BB_FA_CNT |
774 ODM_BB_RSSI_MONITOR |
775 ODM_BB_CCK_PD |
776 /* ODM_BB_PWR_TRAIN | */
777 ODM_BB_RATE_ADAPTIVE |
778 ODM_BB_CFO_TRACKING |
779 ODM_BB_ENV_MONITOR;
780 break;
781 #endif
782
783 #if (RTL8710B_SUPPORT == 1)
784 case ODM_RTL8710B:
785 support_ability |=
786 ODM_BB_DIG |
787 ODM_BB_RA_MASK |
788 /*ODM_BB_DYNAMIC_TXPWR |*/
789 ODM_BB_FA_CNT |
790 ODM_BB_RSSI_MONITOR |
791 ODM_BB_CCK_PD |
792 /*ODM_BB_PWR_TRAIN |*/
793 ODM_BB_RATE_ADAPTIVE |
794 ODM_BB_CFO_TRACKING |
795 ODM_BB_ENV_MONITOR;
796 break;
797 #endif
798
799 #if (RTL8188F_SUPPORT == 1)
800 case ODM_RTL8188F:
801 support_ability |=
802 ODM_BB_DIG |
803 ODM_BB_RA_MASK |
804 /*ODM_BB_DYNAMIC_TXPWR |*/
805 ODM_BB_FA_CNT |
806 ODM_BB_RSSI_MONITOR |
807 ODM_BB_CCK_PD |
808 /*ODM_BB_PWR_TRAIN |*/
809 ODM_BB_RATE_ADAPTIVE |
810 ODM_BB_CFO_TRACKING |
811 ODM_BB_ENV_MONITOR;
812 break;
813 #endif
814
815 /*---------------AC Series-------------------*/
816
817 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
818 case ODM_RTL8812:
819 case ODM_RTL8821:
820 support_ability |=
821 ODM_BB_DIG |
822 ODM_BB_RA_MASK |
823 /*ODM_BB_DYNAMIC_TXPWR |*/
824 ODM_BB_FA_CNT |
825 ODM_BB_RSSI_MONITOR |
826 ODM_BB_CCK_PD |
827 /*ODM_BB_PWR_TRAIN |*/
828 ODM_BB_RATE_ADAPTIVE |
829 ODM_BB_CFO_TRACKING |
830 ODM_BB_ENV_MONITOR;
831 break;
832 #endif
833
834 #if (RTL8814A_SUPPORT == 1)
835 case ODM_RTL8814A:
836 support_ability |=
837 ODM_BB_DIG |
838 ODM_BB_RA_MASK |
839 /*ODM_BB_DYNAMIC_TXPWR |*/
840 ODM_BB_FA_CNT |
841 ODM_BB_RSSI_MONITOR |
842 ODM_BB_CCK_PD |
843 /*ODM_BB_PWR_TRAIN |*/
844 ODM_BB_RATE_ADAPTIVE |
845 ODM_BB_CFO_TRACKING |
846 ODM_BB_ENV_MONITOR;
847 break;
848 #endif
849
850 #if (RTL8814B_SUPPORT == 1)
851 case ODM_RTL8814B:
852 support_ability |=
853 ODM_BB_DIG |
854 ODM_BB_RA_MASK |
855 /*ODM_BB_DYNAMIC_TXPWR |*/
856 ODM_BB_FA_CNT |
857 ODM_BB_RSSI_MONITOR |
858 ODM_BB_CCK_PD |
859 /*ODM_BB_PWR_TRAIN |*/
860 ODM_BB_RATE_ADAPTIVE |
861 ODM_BB_CFO_TRACKING |
862 ODM_BB_ENV_MONITOR;
863 break;
864 #endif
865
866 #if (RTL8822B_SUPPORT == 1)
867 case ODM_RTL8822B:
868 support_ability |=
869 ODM_BB_DIG |
870 ODM_BB_RA_MASK |
871 /*ODM_BB_DYNAMIC_TXPWR |*/
872 ODM_BB_FA_CNT |
873 ODM_BB_RSSI_MONITOR |
874 ODM_BB_CCK_PD |
875 /*ODM_BB_PWR_TRAIN |*/
876 ODM_BB_RATE_ADAPTIVE |
877 ODM_BB_CFO_TRACKING |
878 ODM_BB_ENV_MONITOR;
879 break;
880 #endif
881
882 #if (RTL8821C_SUPPORT == 1)
883 case ODM_RTL8821C:
884 support_ability |=
885 ODM_BB_DIG |
886 ODM_BB_RA_MASK |
887 /*ODM_BB_DYNAMIC_TXPWR |*/
888 ODM_BB_FA_CNT |
889 ODM_BB_RSSI_MONITOR |
890 ODM_BB_CCK_PD |
891 /*ODM_BB_PWR_TRAIN |*/
892 ODM_BB_RATE_ADAPTIVE |
893 ODM_BB_CFO_TRACKING |
894 ODM_BB_ENV_MONITOR;
895 break;
896 #endif
897
898 default:
899 support_ability |=
900 ODM_BB_DIG |
901 ODM_BB_RA_MASK |
902 /*ODM_BB_DYNAMIC_TXPWR |*/
903 ODM_BB_FA_CNT |
904 ODM_BB_RSSI_MONITOR |
905 ODM_BB_CCK_PD |
906 /*ODM_BB_PWR_TRAIN |*/
907 ODM_BB_RATE_ADAPTIVE |
908 ODM_BB_CFO_TRACKING |
909 ODM_BB_ENV_MONITOR;
910
911 dbg_print("[Warning] Supportability Init Warning !!!\n");
912 break;
913
914 }
915
916 /*[Config Antenna Diveristy]*/
917 if (*(p_dm->p_enable_antdiv))
918 support_ability |= ODM_BB_ANT_DIV;
919
920 /*[Config Adaptivity]*/
921 if (*(p_dm->p_enable_adaptivity))
922 support_ability |= ODM_BB_ADAPTIVITY;
923
924 return support_ability;
925 }
926 #endif
927
928 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
929 u64
phydm_supportability_init_ap(void * p_dm_void)930 phydm_supportability_init_ap(
931 void *p_dm_void
932 )
933 {
934 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
935 u64 support_ability = 0;
936
937 switch (p_dm->support_ic_type) {
938
939 /*---------------N Series--------------------*/
940 #if (RTL8188E_SUPPORT == 1)
941 case ODM_RTL8188E:
942 support_ability |=
943 ODM_BB_DIG |
944 ODM_BB_RA_MASK |
945 ODM_BB_FA_CNT |
946 ODM_BB_RSSI_MONITOR |
947 ODM_BB_CCK_PD |
948 /*ODM_BB_PWR_TRAIN |*/
949 ODM_BB_RATE_ADAPTIVE |
950 ODM_BB_CFO_TRACKING |
951 ODM_BB_ENV_MONITOR |
952 ODM_BB_PRIMARY_CCA;
953 break;
954 #endif
955
956 #if (RTL8192E_SUPPORT == 1)
957 case ODM_RTL8192E:
958 support_ability |=
959 ODM_BB_DIG |
960 ODM_BB_RA_MASK |
961 ODM_BB_FA_CNT |
962 ODM_BB_RSSI_MONITOR |
963 ODM_BB_CCK_PD |
964 /*ODM_BB_PWR_TRAIN |*/
965 ODM_BB_RATE_ADAPTIVE |
966 ODM_BB_CFO_TRACKING |
967 ODM_BB_ENV_MONITOR |
968 ODM_BB_PRIMARY_CCA;
969 break;
970 #endif
971
972 #if (RTL8723B_SUPPORT == 1)
973 case ODM_RTL8723B:
974 support_ability |=
975 ODM_BB_DIG |
976 ODM_BB_RA_MASK |
977 ODM_BB_FA_CNT |
978 ODM_BB_RSSI_MONITOR |
979 ODM_BB_CCK_PD |
980 /*ODM_BB_PWR_TRAIN |*/
981 ODM_BB_RATE_ADAPTIVE |
982 ODM_BB_CFO_TRACKING |
983 ODM_BB_ENV_MONITOR;
984 break;
985 #endif
986
987 #if ((RTL8198F_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
988 case ODM_RTL8198F:
989 case ODM_RTL8197F:
990 support_ability |=
991 ODM_BB_DIG |
992 ODM_BB_RA_MASK |
993 ODM_BB_FA_CNT |
994 ODM_BB_RSSI_MONITOR |
995 ODM_BB_CCK_PD |
996 /*ODM_BB_PWR_TRAIN |*/
997 ODM_BB_RATE_ADAPTIVE |
998 ODM_BB_CFO_TRACKING |
999 ODM_BB_ADAPTIVE_SOML |
1000 ODM_BB_ENV_MONITOR |
1001 ODM_BB_LNA_SAT_CHK |
1002 ODM_BB_PRIMARY_CCA;
1003 break;
1004 #endif
1005
1006 /*---------------AC Series-------------------*/
1007
1008 #if (RTL8881A_SUPPORT == 1)
1009 case ODM_RTL8881A:
1010 support_ability |=
1011 ODM_BB_DIG |
1012 ODM_BB_RA_MASK |
1013 ODM_BB_FA_CNT |
1014 ODM_BB_RSSI_MONITOR |
1015 ODM_BB_CCK_PD |
1016 /*ODM_BB_PWR_TRAIN |*/
1017 ODM_BB_RATE_ADAPTIVE |
1018 ODM_BB_CFO_TRACKING |
1019 ODM_BB_ENV_MONITOR;
1020 break;
1021 #endif
1022
1023 #if (RTL8814A_SUPPORT == 1)
1024 case ODM_RTL8814A:
1025 support_ability |=
1026 ODM_BB_DIG |
1027 ODM_BB_RA_MASK |
1028 ODM_BB_FA_CNT |
1029 ODM_BB_RSSI_MONITOR |
1030 ODM_BB_CCK_PD |
1031 /*ODM_BB_PWR_TRAIN |*/
1032 ODM_BB_RATE_ADAPTIVE |
1033 ODM_BB_CFO_TRACKING |
1034 ODM_BB_ENV_MONITOR;
1035 break;
1036 #endif
1037
1038 #if (RTL8814B_SUPPORT == 1)
1039 case ODM_RTL8814B:
1040 support_ability |=
1041 ODM_BB_DIG |
1042 ODM_BB_RA_MASK |
1043 ODM_BB_FA_CNT |
1044 ODM_BB_RSSI_MONITOR |
1045 ODM_BB_CCK_PD |
1046 /*ODM_BB_PWR_TRAIN |*/
1047 ODM_BB_RATE_ADAPTIVE |
1048 ODM_BB_CFO_TRACKING |
1049 ODM_BB_ENV_MONITOR;
1050 break;
1051 #endif
1052
1053 #if (RTL8822B_SUPPORT == 1)
1054 case ODM_RTL8822B:
1055 support_ability |=
1056 ODM_BB_DIG |
1057 ODM_BB_RA_MASK |
1058 ODM_BB_FA_CNT |
1059 ODM_BB_RSSI_MONITOR |
1060 ODM_BB_CCK_PD |
1061 /*ODM_BB_PWR_TRAIN |*/
1062 ODM_BB_RATE_ADAPTIVE |
1063 ODM_BB_CFO_TRACKING |
1064 ODM_BB_ENV_MONITOR |
1065 ODM_BB_ADAPTIVE_SOML;
1066 break;
1067 #endif
1068
1069 #if (RTL8821C_SUPPORT == 1)
1070 case ODM_RTL8821C:
1071 support_ability |=
1072 ODM_BB_DIG |
1073 ODM_BB_RA_MASK |
1074 ODM_BB_FA_CNT |
1075 ODM_BB_RSSI_MONITOR |
1076 ODM_BB_CCK_PD |
1077 /*ODM_BB_PWR_TRAIN |*/
1078 ODM_BB_RATE_ADAPTIVE |
1079 ODM_BB_CFO_TRACKING |
1080 ODM_BB_ENV_MONITOR;
1081
1082 break;
1083 #endif
1084
1085 default:
1086 support_ability |=
1087 ODM_BB_DIG |
1088 ODM_BB_RA_MASK |
1089 ODM_BB_FA_CNT |
1090 ODM_BB_RSSI_MONITOR |
1091 ODM_BB_CCK_PD |
1092 /*ODM_BB_PWR_TRAIN |*/
1093 ODM_BB_RATE_ADAPTIVE |
1094 ODM_BB_CFO_TRACKING |
1095 ODM_BB_ENV_MONITOR;
1096
1097 dbg_print("[Warning] Supportability Init Warning !!!\n");
1098 break;
1099
1100 }
1101
1102 #if 0
1103 /*[Config Antenna Diveristy]*/
1104 if (*(p_dm->p_enable_antdiv))
1105 support_ability |= ODM_BB_ANT_DIV;
1106
1107 /*[Config Adaptivity]*/
1108 if (*(p_dm->p_enable_adaptivity))
1109 support_ability |= ODM_BB_ADAPTIVITY;
1110 #endif
1111
1112 return support_ability;
1113 }
1114 #endif
1115
1116 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1117 u64
phydm_supportability_init_iot(void * p_dm_void)1118 phydm_supportability_init_iot(
1119 void *p_dm_void
1120 )
1121 {
1122 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1123 u64 support_ability = 0;
1124
1125 switch (p_dm->support_ic_type) {
1126
1127 #if (RTL8710B_SUPPORT == 1)
1128 case ODM_RTL8710B:
1129 support_ability |=
1130 ODM_BB_DIG |
1131 ODM_BB_RA_MASK |
1132 /*ODM_BB_DYNAMIC_TXPWR |*/
1133 ODM_BB_FA_CNT |
1134 ODM_BB_RSSI_MONITOR |
1135 ODM_BB_CCK_PD |
1136 /*ODM_BB_PWR_TRAIN |*/
1137 ODM_BB_RATE_ADAPTIVE |
1138 ODM_BB_CFO_TRACKING |
1139 ODM_BB_ENV_MONITOR;
1140 break;
1141 #endif
1142
1143 #if (RTL8195A_SUPPORT == 1)
1144 case ODM_RTL8195A:
1145 support_ability |=
1146 ODM_BB_DIG |
1147 ODM_BB_RA_MASK |
1148 /*ODM_BB_DYNAMIC_TXPWR |*/
1149 ODM_BB_FA_CNT |
1150 ODM_BB_RSSI_MONITOR |
1151 ODM_BB_CCK_PD |
1152 /*ODM_BB_PWR_TRAIN |*/
1153 ODM_BB_RATE_ADAPTIVE |
1154 ODM_BB_CFO_TRACKING |
1155 ODM_BB_ENV_MONITOR;
1156 break;
1157 #endif
1158
1159 default:
1160 support_ability |=
1161 ODM_BB_DIG |
1162 ODM_BB_RA_MASK |
1163 /*ODM_BB_DYNAMIC_TXPWR |*/
1164 ODM_BB_FA_CNT |
1165 ODM_BB_RSSI_MONITOR |
1166 ODM_BB_CCK_PD |
1167 /*ODM_BB_PWR_TRAIN |*/
1168 ODM_BB_RATE_ADAPTIVE |
1169 ODM_BB_CFO_TRACKING |
1170 ODM_BB_ENV_MONITOR;
1171
1172 dbg_print("[Warning] Supportability Init Warning !!!\n");
1173 break;
1174
1175 }
1176
1177 /*[Config Antenna Diveristy]*/
1178 if (*(p_dm->p_enable_antdiv))
1179 support_ability |= ODM_BB_ANT_DIV;
1180
1181 /*[Config Adaptivity]*/
1182 if (*(p_dm->p_enable_adaptivity))
1183 support_ability |= ODM_BB_ADAPTIVITY;
1184
1185 return support_ability;
1186 }
1187 #endif
1188
1189 void
phydm_fwoffload_ability_init(struct PHY_DM_STRUCT * p_dm,enum phydm_offload_ability offload_ability)1190 phydm_fwoffload_ability_init(
1191 struct PHY_DM_STRUCT *p_dm,
1192 enum phydm_offload_ability offload_ability
1193 )
1194 {
1195
1196 switch (offload_ability) {
1197
1198 case PHYDM_PHY_PARAM_OFFLOAD:
1199 if (p_dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1200 p_dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1201 break;
1202
1203 case PHYDM_RF_IQK_OFFLOAD:
1204 p_dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1205 break;
1206
1207 default:
1208 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("fwofflad, wrong init type!!\n"));
1209 break;
1210
1211 }
1212
1213 PHYDM_DBG(p_dm, ODM_COMP_INIT,
1214 ("fw_offload_ability = %x\n", p_dm->fw_offload_ability));
1215
1216 }
1217 void
phydm_fwoffload_ability_clear(struct PHY_DM_STRUCT * p_dm,enum phydm_offload_ability offload_ability)1218 phydm_fwoffload_ability_clear(
1219 struct PHY_DM_STRUCT *p_dm,
1220 enum phydm_offload_ability offload_ability
1221 )
1222 {
1223
1224 switch (offload_ability) {
1225
1226 case PHYDM_PHY_PARAM_OFFLOAD:
1227 if (p_dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1228 p_dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1229 break;
1230
1231 case PHYDM_RF_IQK_OFFLOAD:
1232 p_dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1233 break;
1234
1235 default:
1236 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("fwofflad, wrong init type!!\n"));
1237 break;
1238
1239 }
1240
1241 PHYDM_DBG(p_dm, ODM_COMP_INIT,
1242 ("fw_offload_ability = %x\n", p_dm->fw_offload_ability));
1243
1244 }
1245
1246 void
phydm_supportability_init(void * p_dm_void)1247 phydm_supportability_init(
1248 void *p_dm_void
1249 )
1250 {
1251 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1252 u64 support_ability;
1253
1254 if (*(p_dm->p_mp_mode) == true) {
1255 support_ability = 0;
1256 /**/
1257 } else {
1258
1259 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1260 support_ability = phydm_supportability_init_win(p_dm);
1261 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1262 support_ability = phydm_supportability_init_ap(p_dm);
1263 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1264 support_ability = phydm_supportability_init_ce(p_dm);
1265 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1266 support_ability = phydm_supportability_init_iot(p_dm);
1267 #endif
1268 }
1269 odm_cmn_info_init(p_dm, ODM_CMNINFO_ABILITY, support_ability);
1270 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("IC = ((0x%x)), Supportability Init = ((0x%llx))\n", p_dm->support_ic_type, p_dm->support_ability));
1271 }
1272
1273 void
phydm_rfe_init(void * p_dm_void)1274 phydm_rfe_init(
1275 void *p_dm_void
1276 )
1277 {
1278 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1279
1280 PHYDM_DBG(p_dm, ODM_COMP_INIT, ("RFE_Init\n"));
1281 #if (RTL8822B_SUPPORT == 1)
1282 if (p_dm->support_ic_type == ODM_RTL8822B) {
1283 phydm_rfe_8822b_init(p_dm);
1284 /**/
1285 }
1286 #endif
1287 }
1288
1289 void
phydm_dm_early_init(struct PHY_DM_STRUCT * p_dm)1290 phydm_dm_early_init(
1291 struct PHY_DM_STRUCT *p_dm
1292 )
1293 {
1294 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1295 halrf_init(p_dm);
1296 #endif
1297 }
1298
1299 void
odm_dm_init(struct PHY_DM_STRUCT * p_dm)1300 odm_dm_init(
1301 struct PHY_DM_STRUCT *p_dm
1302 )
1303 {
1304 halrf_init(p_dm);
1305 phydm_supportability_init(p_dm);
1306 phydm_rfe_init(p_dm);
1307 phydm_common_info_self_init(p_dm);
1308 phydm_rx_phy_status_init(p_dm);
1309 phydm_auto_dbg_engine_init(p_dm);
1310 phydm_dig_init(p_dm);
1311 phydm_cck_pd_init(p_dm);
1312 phydm_nhm_init(p_dm);
1313 phydm_adaptivity_init(p_dm);
1314 phydm_ra_info_init(p_dm);
1315 phydm_rssi_monitor_init(p_dm);
1316 phydm_cfo_tracking_init(p_dm);
1317 phydm_rf_init(p_dm);
1318 odm_txpowertracking_init(p_dm);
1319 phydm_dc_cancellation(p_dm);
1320 #ifdef PHYDM_TXA_CALIBRATION
1321 phydm_txcurrentcalibration(p_dm);
1322 phydm_get_pa_bias_offset(p_dm);
1323 #endif
1324 odm_antenna_diversity_init(p_dm);
1325 phydm_adaptive_soml_init(p_dm);
1326 #ifdef CONFIG_DYNAMIC_RX_PATH
1327 phydm_dynamic_rx_path_init(p_dm);
1328 #endif
1329 odm_auto_channel_select_init(p_dm);
1330 phydm_path_diversity_init(p_dm);
1331 phydm_dynamic_tx_power_init(p_dm);
1332 #if (PHYDM_LA_MODE_SUPPORT == 1)
1333 adc_smp_init(p_dm);
1334 #endif
1335
1336 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1337 phydm_beamforming_init(p_dm);
1338 #endif
1339 #if (RTL8188E_SUPPORT == 1)
1340 odm_ra_info_init_all(p_dm);
1341 #endif
1342
1343 phydm_primary_cca_init(p_dm);
1344
1345 #ifdef CONFIG_PSD_TOOL
1346 phydm_psd_init(p_dm);
1347 #endif
1348
1349 #ifdef CONFIG_SMART_ANTENNA
1350 phydm_smt_ant_init(p_dm);
1351 #endif
1352
1353 }
1354
1355 void
odm_dm_reset(struct PHY_DM_STRUCT * p_dm)1356 odm_dm_reset(
1357 struct PHY_DM_STRUCT *p_dm
1358 )
1359 {
1360 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
1361
1362 odm_ant_div_reset(p_dm);
1363 phydm_set_edcca_threshold_api(p_dm, p_dig_t->cur_ig_value);
1364 }
1365
1366 void
phydm_support_ability_debug(void * p_dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)1367 phydm_support_ability_debug(
1368 void *p_dm_void,
1369 u32 *const dm_value,
1370 u32 *_used,
1371 char *output,
1372 u32 *_out_len
1373 )
1374 {
1375 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1376 u64 pre_support_ability, one = 1;
1377 u32 used = *_used;
1378 u32 out_len = *_out_len;
1379
1380 pre_support_ability = p_dm->support_ability;
1381
1382 PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================"));
1383 if (dm_value[0] == 100) {
1384 PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n"));
1385 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1386 PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm->support_ability & ODM_BB_DIG) ? ("V") : ("."))));
1387 PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm->support_ability & ODM_BB_RA_MASK) ? ("V") : ("."))));
1388 PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYN_TXPWR\n", ((p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))));
1389 PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm->support_ability & ODM_BB_FA_CNT) ? ("V") : ("."))));
1390 PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MNTR\n", ((p_dm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))));
1391 PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm->support_ability & ODM_BB_CCK_PD) ? ("V") : ("."))));
1392 PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm->support_ability & ODM_BB_ANT_DIV) ? ("V") : ("."))));
1393 PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))SMT_ANT\n", ((p_dm->support_ability & ODM_BB_SMT_ANT) ? ("V") : ("."))));
1394 PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : ("."))));
1395 PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RA\n", ((p_dm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))));
1396 PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm->support_ability & ODM_BB_PATH_DIV) ? ("V") : ("."))));
1397 PHYDM_SNPRINTF((output + used, out_len - used, "11. (( %s ))DFS\n", ((p_dm->support_ability & ODM_BB_DFS) ? ("V") : ("."))));
1398 PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYN_ARFR\n", ((p_dm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))));
1399 PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : ("."))));
1400 PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))CFO_TRACK\n", ((p_dm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : ("."))));
1401 PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))ENV_MONITOR\n", ((p_dm->support_ability & ODM_BB_ENV_MONITOR) ? ("V") : ("."))));
1402 PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRI_CCA\n", ((p_dm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))));
1403 PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADPTV_SOML\n", ((p_dm->support_ability & ODM_BB_ADAPTIVE_SOML) ? ("V") : ("."))));
1404 /*PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))TBD\n", ((p_dm->support_ability & ODM_BB_TBD) ? ("V") : ("."))));*/
1405 /*PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TBD\n", ((p_dm->support_ability & ODM_BB_TBD) ? ("V") : ("."))));*/
1406 PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))DYN_RX_PATH\n", ((p_dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : ("."))));
1407 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1408 PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM offload ability\n"));
1409 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1410 PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))PHY PARAM OFFLOAD\n", ((p_dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ? ("V") : ("."))));
1411 PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RF IQK OFFLOAD\n", ((p_dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? ("V") : ("."))));
1412 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1413
1414 }
1415 /*
1416 else if(dm_value[0] == 101)
1417 {
1418 p_dm->support_ability = 0 ;
1419 dbg_print("Disable all support_ability components\n");
1420 PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components"));
1421 }
1422 */
1423 else {
1424
1425 if (dm_value[1] == 1) { /* enable */
1426 p_dm->support_ability |= (one << dm_value[0]);
1427 if (BIT(dm_value[0]) & ODM_BB_PATH_DIV)
1428 phydm_path_diversity_init(p_dm);
1429 } else if (dm_value[1] == 2) /* disable */
1430 p_dm->support_ability &= ~(one << dm_value[0]);
1431 else
1432 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable"));
1433 }
1434 PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%llx\n", pre_support_ability));
1435 PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%llx\n", p_dm->support_ability));
1436 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1437
1438 *_used = used;
1439 *_out_len = out_len;
1440 }
1441
1442 void
phydm_watchdog_lps_32k(struct PHY_DM_STRUCT * p_dm)1443 phydm_watchdog_lps_32k(
1444 struct PHY_DM_STRUCT *p_dm
1445 )
1446 {
1447 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("%s ======>\n", __func__));
1448
1449 phydm_common_info_self_update(p_dm);
1450 phydm_rssi_monitor_check(p_dm);
1451 phydm_dig_lps_32k(p_dm);
1452 phydm_common_info_self_reset(p_dm);
1453 }
1454
1455 void
phydm_watchdog_lps(struct PHY_DM_STRUCT * p_dm)1456 phydm_watchdog_lps(
1457 struct PHY_DM_STRUCT *p_dm
1458 )
1459 {
1460 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1461 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("%s ======>\n", __func__));
1462
1463 phydm_common_info_self_update(p_dm);
1464 phydm_rssi_monitor_check(p_dm);
1465 phydm_basic_dbg_message(p_dm);
1466 phydm_receiver_blocking(p_dm);
1467 odm_false_alarm_counter_statistics(p_dm);
1468 phydm_dig_by_rssi_lps(p_dm);
1469 phydm_cck_pd_th(p_dm);
1470 phydm_adaptivity(p_dm);
1471 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1472 odm_antenna_diversity(p_dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
1473 #endif
1474 phydm_common_info_self_reset(p_dm);
1475 #endif
1476 }
1477
1478 void
phydm_watchdog_mp(struct PHY_DM_STRUCT * p_dm)1479 phydm_watchdog_mp(
1480 struct PHY_DM_STRUCT *p_dm
1481 )
1482 {
1483 #ifdef CONFIG_DYNAMIC_RX_PATH
1484 phydm_dynamic_rx_path_caller(p_dm);
1485 #endif
1486 }
1487
1488 void
phydm_pause_dm_watchdog(void * p_dm_void,enum phydm_pause_type pause_type)1489 phydm_pause_dm_watchdog(
1490 void *p_dm_void,
1491 enum phydm_pause_type pause_type
1492 )
1493 {
1494 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1495
1496 if (pause_type == PHYDM_PAUSE) {
1497 p_dm->disable_phydm_watchdog = 1;
1498 PHYDM_DBG(p_dm, ODM_COMP_API, ("PHYDM Stop\n"));
1499 } else {
1500 p_dm->disable_phydm_watchdog = 0;
1501 PHYDM_DBG(p_dm, ODM_COMP_API, ("PHYDM Start\n"));
1502 }
1503 }
1504
1505 u8
phydm_pause_func(void * p_dm_void,enum phydm_func_idx_e pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)1506 phydm_pause_func(
1507 void *p_dm_void,
1508 enum phydm_func_idx_e pause_func,
1509 enum phydm_pause_type pause_type,
1510 enum phydm_pause_level pause_lv,
1511 u8 val_lehgth,
1512 u32 *val_buf
1513 )
1514 {
1515 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1516 s8 *pause_lv_pre = &(p_dm->s8_dummy);
1517 u32 *bkp_val = &(p_dm->u32_dummy);
1518 u32 ori_val[5] = {0};
1519 u64 pause_func_bitmap = (u64)BIT(pause_func);
1520 u8 i;
1521
1522
1523
1524 PHYDM_DBG(p_dm, ODM_COMP_API, ("[%s][%s] LV=%d, Len=%d\n", __func__,
1525 ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"), pause_lv, val_lehgth));
1526
1527 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
1528 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] Wrong LV=%d\n", pause_lv));
1529 return PAUSE_FAIL;
1530 }
1531
1532 if (pause_func == F00_DIG) {
1533
1534 PHYDM_DBG(p_dm, ODM_COMP_API, ("[DIG]\n"));
1535
1536 if (val_lehgth != 1) {
1537 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] val_length != 1\n"));
1538 return PAUSE_FAIL;
1539 }
1540
1541 ori_val[0] = (u32)(p_dm->dm_dig_table.cur_ig_value); /*0xc50*/
1542 pause_lv_pre = &(p_dm->pause_lv_table.lv_dig);
1543 bkp_val = (u32*)(&(p_dm->dm_dig_table.rvrt_val));
1544 p_dm->phydm_func_handler.pause_phydm_handler = phydm_set_dig_val; /*function pointer hook*/
1545
1546 } else
1547
1548 #ifdef PHYDM_SUPPORT_CCKPD
1549 if (pause_func == F05_CCK_PD) {
1550
1551 PHYDM_DBG(p_dm, ODM_COMP_API, ("[CCK_PD]\n"));
1552
1553 if (val_lehgth != 2) {
1554 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] val_length != 2\n"));
1555 return PAUSE_FAIL;
1556 }
1557
1558 ori_val[0] = p_dm->dm_cckpd_table.cur_cck_cca_thres; /*0xa0a*/
1559 ori_val[1] = p_dm->dm_cckpd_table.cck_cca_th_aaa; /*0xaaa*/
1560 pause_lv_pre = &(p_dm->pause_lv_table.lv_cckpd);
1561 bkp_val = &(p_dm->dm_cckpd_table.rvrt_val[0]);
1562 p_dm->phydm_func_handler.pause_phydm_handler = phydm_set_cckpd_val; /*function pointer hook*/
1563
1564 } else
1565 #endif
1566
1567 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1568 if (pause_func == F06_ANT_DIV) {
1569
1570 PHYDM_DBG(p_dm, ODM_COMP_API, ("[AntDiv]\n"));
1571
1572 if (val_lehgth != 1) {
1573 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] val_length != 1\n"));
1574 return PAUSE_FAIL;
1575 }
1576
1577 ori_val[0] = (u32)(p_dm->dm_fat_table.rx_idle_ant); /*default antenna*/
1578 pause_lv_pre = &(p_dm->pause_lv_table.lv_antdiv);
1579 bkp_val = (u32*)(&(p_dm->dm_fat_table.rvrt_val));
1580 p_dm->phydm_func_handler.pause_phydm_handler = phydm_set_antdiv_val; /*function pointer hook*/
1581
1582 } else
1583 #endif
1584
1585 if (pause_func == F13_ADPTVTY) {
1586
1587 PHYDM_DBG(p_dm, ODM_COMP_API, ("[Adaptivity]\n"));
1588
1589 if (val_lehgth != 2) {
1590 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] val_length != 2\n"));
1591 return PAUSE_FAIL;
1592 }
1593
1594 ori_val[0] = (u32)(p_dm->adaptivity.th_l2h); /*th_l2h*/
1595 ori_val[1] = (u32)(p_dm->adaptivity.th_h2l); /*th_h2l*/
1596 pause_lv_pre = &(p_dm->pause_lv_table.lv_adapt);
1597 bkp_val = (u32 *)(&(p_dm->adaptivity.rvrt_val));
1598 p_dm->phydm_func_handler.pause_phydm_handler = phydm_set_edcca_val; /*function pointer hook*/
1599
1600 } else
1601
1602 {
1603 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] error func idx\n"));
1604 return PAUSE_FAIL;
1605 }
1606
1607 PHYDM_DBG(p_dm, ODM_COMP_API, ("Pause_LV{new , pre} = {%d ,%d}\n", pause_lv, *pause_lv_pre));
1608
1609 if ((pause_type == PHYDM_PAUSE) || (pause_type == PHYDM_PAUSE_NO_SET)) {
1610
1611 if (pause_lv > *pause_lv_pre) {
1612
1613 if (!(p_dm->pause_ability & pause_func_bitmap)) {
1614
1615 for (i = 0; i < val_lehgth; i ++)
1616 bkp_val[i] = ori_val[i];
1617 }
1618
1619 p_dm->pause_ability |= pause_func_bitmap;
1620 PHYDM_DBG(p_dm, ODM_COMP_API, ("pause_ability=0x%llx\n", p_dm->pause_ability));
1621
1622 if (pause_type == PHYDM_PAUSE) {
1623
1624 for (i = 0; i < val_lehgth; i ++) {
1625 PHYDM_DBG(p_dm, ODM_COMP_API, ("[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",i, val_buf[i], bkp_val[i]));
1626 /**/
1627 }
1628 p_dm->phydm_func_handler.pause_phydm_handler(p_dm, val_buf, val_lehgth);
1629 } else {
1630
1631 for (i = 0; i < val_lehgth; i ++) {
1632 PHYDM_DBG(p_dm, ODM_COMP_API, ("[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",i, bkp_val[i]));
1633 /**/
1634 }
1635 }
1636
1637 *pause_lv_pre = pause_lv;
1638 return PAUSE_SUCCESS;
1639
1640 } else {
1641 PHYDM_DBG(p_dm, ODM_COMP_API, ("[PAUSE FAIL] Pre_LV >= Curr_LV\n"));
1642 return PAUSE_FAIL;
1643 }
1644
1645 } else if (pause_type == PHYDM_RESUME) {
1646 p_dm->pause_ability &= ~pause_func_bitmap;
1647 PHYDM_DBG(p_dm, ODM_COMP_API, ("pause_ability=0x%llx\n", p_dm->pause_ability));
1648
1649 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
1650
1651 for (i = 0; i < val_lehgth; i ++) {
1652 PHYDM_DBG(p_dm, ODM_COMP_API, ("[RESUME] val_idx[%d]={0x%x}\n", i, bkp_val[i]));
1653 }
1654
1655 p_dm->phydm_func_handler.pause_phydm_handler(p_dm, bkp_val, val_lehgth);
1656
1657 return PAUSE_SUCCESS;
1658 } else {
1659 PHYDM_DBG(p_dm, ODM_COMP_API, ("[WARNING] error pause_type\n"));
1660 return PAUSE_FAIL;
1661 }
1662
1663 }
1664
1665 void
phydm_pause_func_console(void * p_dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len,u32 input_num)1666 phydm_pause_func_console(
1667 void *p_dm_void,
1668 char input[][16],
1669 u32 *_used,
1670 char *output,
1671 u32 *_out_len,
1672 u32 input_num
1673 )
1674 {
1675 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1676 char help[] = "-h";
1677 u32 var1[10] = {0};
1678 u32 used = *_used;
1679 u32 out_len = *_out_len;
1680 u32 i;
1681 u8 val_length = 0;
1682 u32 val_buf[5] = {0};
1683 u8 set_result = 0;
1684 enum phydm_func_idx_e func = 0;
1685 enum phydm_pause_type pause_type = 0;
1686 enum phydm_pause_level pause_lv = 0;
1687
1688 if ((strcmp(input[1], help) == 0)) {
1689 PHYDM_SNPRINTF((output + used, out_len - used, "{Func} {1:pause, 2:Resume} {lv} Val[5:0]\n"));
1690
1691 } else {
1692
1693 for (i = 0; i < 10; i++) {
1694 if (input[i + 1]) {
1695 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
1696 }
1697 }
1698
1699 func = (enum phydm_func_idx_e)var1[0];
1700 pause_type = (enum phydm_pause_type)var1[1];
1701 pause_lv = (enum phydm_pause_level)var1[2];
1702
1703
1704 for (i = 0; i < 5; i++) {
1705 val_buf[i] = var1[3 + i];
1706 }
1707
1708 if (func == F00_DIG) {
1709 PHYDM_SNPRINTF((output + used, out_len - used, "[DIG]\n"));
1710 val_length = 1;
1711
1712 } else if (func == F05_CCK_PD) {
1713 PHYDM_SNPRINTF((output + used, out_len - used, "[CCK_PD]\n"));
1714 val_length = 2;
1715 } else if (func == F06_ANT_DIV) {
1716 PHYDM_SNPRINTF((output + used, out_len - used, "[Ant_Div]\n"));
1717 val_length = 1;
1718 } else if (func == F13_ADPTVTY) {
1719 PHYDM_SNPRINTF((output + used, out_len - used, "[Adaptivity]\n"));
1720 val_length = 2;
1721 } else {
1722 PHYDM_SNPRINTF((output + used, out_len - used, "[Set Function Error]\n"));
1723 val_length = 0;
1724 }
1725
1726 if (val_length != 0) {
1727
1728 PHYDM_SNPRINTF((output + used, out_len - used, "{%s, lv=%d} val = %d, %d}\n",
1729 ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"), pause_lv, var1[3], var1[4]));
1730
1731 set_result= phydm_pause_func(p_dm, func, pause_type, pause_lv, val_length, val_buf);
1732 }
1733
1734 PHYDM_SNPRINTF((output + used, out_len - used, "set_result = %d\n", set_result));
1735 }
1736
1737
1738 *_used = used;
1739 *_out_len = out_len;
1740 }
1741
1742 u8
phydm_stop_dm_watchdog_check(void * p_dm_void)1743 phydm_stop_dm_watchdog_check(
1744 void *p_dm_void
1745 )
1746 {
1747 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
1748
1749 if (p_dm->disable_phydm_watchdog == 1) {
1750
1751 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("Disable phydm\n"));
1752 return true;
1753
1754 } else if (phydm_acs_check(p_dm) == true) {
1755
1756 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("Disable phydm by ACS\n"));
1757 return true;
1758
1759 } else
1760 return false;
1761
1762 }
1763
1764 /*
1765 * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
1766 * You can not add any dummy function here, be care, you can only use DM structure
1767 * to perform any new ODM_DM.
1768 * */
1769 void
phydm_watchdog(struct PHY_DM_STRUCT * p_dm)1770 phydm_watchdog(
1771 struct PHY_DM_STRUCT *p_dm
1772 )
1773 {
1774 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("%s ======>\n", __func__));
1775
1776 phydm_common_info_self_update(p_dm);
1777 phydm_rssi_monitor_check(p_dm);
1778 phydm_basic_dbg_message(p_dm);
1779 phydm_auto_dbg_engine(p_dm);
1780 phydm_receiver_blocking(p_dm);
1781
1782 if (phydm_stop_dm_watchdog_check(p_dm) == true)
1783 return;
1784
1785 phydm_hw_setting(p_dm);
1786
1787 #if 0 /*(DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))*/
1788 if (*(p_dm->p_is_power_saving) == true) {
1789
1790 PHYDM_DBG(p_dm, DBG_COMMON_FLOW, ("PHYDM power saving mode\n"));
1791 phydm_dig_by_rssi_lps(p_dm);
1792 phydm_adaptivity(p_dm);
1793
1794 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1795 odm_antenna_diversity(p_dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
1796 #endif
1797 return;
1798 }
1799 #endif
1800
1801 #ifdef PHYDM_TDMA_DIG_SUPPORT
1802 if (p_dm->original_dig_restore == 0)
1803 phydm_tdma_dig_timer_check(p_dm);
1804 else
1805 #endif
1806 {
1807 odm_false_alarm_counter_statistics(p_dm);
1808 phydm_noisy_detection(p_dm);
1809 phydm_dig(p_dm);
1810 phydm_cck_pd_th(p_dm);
1811 }
1812
1813 phydm_adaptivity(p_dm);
1814 phydm_ra_info_watchdog(p_dm);
1815 odm_path_diversity(p_dm);
1816 odm_cfo_tracking(p_dm);
1817 odm_dynamic_tx_power(p_dm);
1818 odm_antenna_diversity(p_dm);
1819 phydm_adaptive_soml(p_dm);
1820 #ifdef CONFIG_DYNAMIC_RX_PATH
1821 phydm_dynamic_rx_path(p_dm);
1822 #endif
1823
1824 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1825 phydm_beamforming_watchdog(p_dm);
1826 #endif
1827
1828 halrf_watchdog(p_dm);
1829 phydm_primary_cca(p_dm);
1830
1831 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1832 odm_dtc(p_dm);
1833 #endif
1834
1835 phydm_ccx_monitor(p_dm);
1836
1837 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1838 phydm_lna_sat_chk_watchdog(p_dm);
1839 #endif
1840
1841 #ifdef PHYDM_POWER_TRAINING_SUPPORT
1842 phydm_update_power_training_state(p_dm);
1843 #endif
1844
1845 phydm_common_info_self_reset(p_dm);
1846
1847 }
1848
1849
1850 /*
1851 * Init /.. Fixed HW value. Only init time.
1852 * */
1853 void
odm_cmn_info_init(struct PHY_DM_STRUCT * p_dm,enum odm_cmninfo_e cmn_info,u64 value)1854 odm_cmn_info_init(
1855 struct PHY_DM_STRUCT *p_dm,
1856 enum odm_cmninfo_e cmn_info,
1857 u64 value
1858 )
1859 {
1860 /* */
1861 /* This section is used for init value */
1862 /* */
1863 switch (cmn_info) {
1864 /* */
1865 /* Fixed ODM value. */
1866 /* */
1867 case ODM_CMNINFO_ABILITY:
1868 p_dm->support_ability = (u64)value;
1869 break;
1870
1871 case ODM_CMNINFO_RF_TYPE:
1872 p_dm->rf_type = (u8)value;
1873 break;
1874
1875 case ODM_CMNINFO_PLATFORM:
1876 p_dm->support_platform = (u8)value;
1877 break;
1878
1879 case ODM_CMNINFO_INTERFACE:
1880 p_dm->support_interface = (u8)value;
1881 break;
1882
1883 case ODM_CMNINFO_MP_TEST_CHIP:
1884 p_dm->is_mp_chip = (u8)value;
1885 break;
1886
1887 case ODM_CMNINFO_IC_TYPE:
1888 p_dm->support_ic_type = (u32)value;
1889 break;
1890
1891 case ODM_CMNINFO_CUT_VER:
1892 p_dm->cut_version = (u8)value;
1893 break;
1894
1895 case ODM_CMNINFO_FAB_VER:
1896 p_dm->fab_version = (u8)value;
1897 break;
1898
1899 case ODM_CMNINFO_RFE_TYPE:
1900 p_dm->rfe_type = (u8)value;
1901 phydm_init_hw_info_by_rfe(p_dm);
1902 break;
1903
1904 case ODM_CMNINFO_RF_ANTENNA_TYPE:
1905 p_dm->ant_div_type = (u8)value;
1906 break;
1907
1908 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
1909 p_dm->with_extenal_ant_switch = (u8)value;
1910 break;
1911
1912 case ODM_CMNINFO_BE_FIX_TX_ANT:
1913 p_dm->dm_fat_table.b_fix_tx_ant = (u8)value;
1914 break;
1915
1916 case ODM_CMNINFO_BOARD_TYPE:
1917 if (!p_dm->is_init_hw_info_by_rfe)
1918 p_dm->board_type = (u8)value;
1919 break;
1920
1921 case ODM_CMNINFO_PACKAGE_TYPE:
1922 if (!p_dm->is_init_hw_info_by_rfe)
1923 p_dm->package_type = (u8)value;
1924 break;
1925
1926 case ODM_CMNINFO_EXT_LNA:
1927 if (!p_dm->is_init_hw_info_by_rfe)
1928 p_dm->ext_lna = (u8)value;
1929 break;
1930
1931 case ODM_CMNINFO_5G_EXT_LNA:
1932 if (!p_dm->is_init_hw_info_by_rfe)
1933 p_dm->ext_lna_5g = (u8)value;
1934 break;
1935
1936 case ODM_CMNINFO_EXT_PA:
1937 if (!p_dm->is_init_hw_info_by_rfe)
1938 p_dm->ext_pa = (u8)value;
1939 break;
1940
1941 case ODM_CMNINFO_5G_EXT_PA:
1942 if (!p_dm->is_init_hw_info_by_rfe)
1943 p_dm->ext_pa_5g = (u8)value;
1944 break;
1945
1946 case ODM_CMNINFO_GPA:
1947 if (!p_dm->is_init_hw_info_by_rfe)
1948 p_dm->type_gpa = (u16)value;
1949 break;
1950
1951 case ODM_CMNINFO_APA:
1952 if (!p_dm->is_init_hw_info_by_rfe)
1953 p_dm->type_apa = (u16)value;
1954 break;
1955
1956 case ODM_CMNINFO_GLNA:
1957 if (!p_dm->is_init_hw_info_by_rfe)
1958 p_dm->type_glna = (u16)value;
1959 break;
1960
1961 case ODM_CMNINFO_ALNA:
1962 if (!p_dm->is_init_hw_info_by_rfe)
1963 p_dm->type_alna = (u16)value;
1964 break;
1965
1966 case ODM_CMNINFO_EXT_TRSW:
1967 if (!p_dm->is_init_hw_info_by_rfe)
1968 p_dm->ext_trsw = (u8)value;
1969 break;
1970 case ODM_CMNINFO_EXT_LNA_GAIN:
1971 p_dm->ext_lna_gain = (u8)value;
1972 break;
1973 case ODM_CMNINFO_PATCH_ID:
1974 p_dm->iot_table.win_patch_id = (u8)value;
1975 break;
1976 case ODM_CMNINFO_BINHCT_TEST:
1977 p_dm->is_in_hct_test = (boolean)value;
1978 break;
1979 case ODM_CMNINFO_BWIFI_TEST:
1980 p_dm->wifi_test = (u8)value;
1981 break;
1982 case ODM_CMNINFO_SMART_CONCURRENT:
1983 p_dm->is_dual_mac_smart_concurrent = (boolean)value;
1984 break;
1985 case ODM_CMNINFO_DOMAIN_CODE_2G:
1986 p_dm->odm_regulation_2_4g = (u8)value;
1987 break;
1988 case ODM_CMNINFO_DOMAIN_CODE_5G:
1989 p_dm->odm_regulation_5g = (u8)value;
1990 break;
1991 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1992 case ODM_CMNINFO_CONFIG_BB_RF:
1993 p_dm->config_bbrf = (boolean)value;
1994 break;
1995 #endif
1996 case ODM_CMNINFO_IQKPAOFF:
1997 p_dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
1998 break;
1999 case ODM_CMNINFO_REGRFKFREEENABLE:
2000 p_dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2001 break;
2002 case ODM_CMNINFO_RFKFREEENABLE:
2003 p_dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2004 break;
2005 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2006 p_dm->normal_rx_path = (u8)value;
2007 break;
2008 case ODM_CMNINFO_EFUSE0X3D8:
2009 p_dm->efuse0x3d8 = (u8)value;
2010 break;
2011 case ODM_CMNINFO_EFUSE0X3D7:
2012 p_dm->efuse0x3d7 = (u8)value;
2013 break;
2014 case ODM_CMNINFO_ADVANCE_OTA:
2015 p_dm->p_advance_ota = (u8)value;
2016 break;
2017
2018 #ifdef CONFIG_PHYDM_DFS_MASTER
2019 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2020 p_dm->dfs_region_domain = (u8)value;
2021 break;
2022 #endif
2023 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2024 p_dm->soft_ap_special_setting = (u32)value;
2025 break;
2026
2027 case ODM_CMNINFO_DPK_EN:
2028 /*p_dm->dpk_en = (u1Byte)value;*/
2029 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2030 break;
2031
2032 case ODM_CMNINFO_HP_HWID:
2033 p_dm->hp_hw_id = (boolean)value;
2034 break;
2035 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
2036 default:
2037 /* do nothing */
2038 break;
2039
2040 }
2041
2042 }
2043
2044
2045 void
odm_cmn_info_hook(struct PHY_DM_STRUCT * p_dm,enum odm_cmninfo_e cmn_info,void * p_value)2046 odm_cmn_info_hook(
2047 struct PHY_DM_STRUCT *p_dm,
2048 enum odm_cmninfo_e cmn_info,
2049 void *p_value
2050 )
2051 {
2052 /* */
2053 /* Hook call by reference pointer. */
2054 /* */
2055 switch (cmn_info) {
2056 /* */
2057 /* Dynamic call by reference pointer. */
2058 /* */
2059 case ODM_CMNINFO_TX_UNI:
2060 p_dm->p_num_tx_bytes_unicast = (u64 *)p_value;
2061 break;
2062
2063 case ODM_CMNINFO_RX_UNI:
2064 p_dm->p_num_rx_bytes_unicast = (u64 *)p_value;
2065 break;
2066
2067 case ODM_CMNINFO_BAND:
2068 p_dm->p_band_type = (u8 *)p_value;
2069 break;
2070
2071 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2072 p_dm->p_sec_ch_offset = (u8 *)p_value;
2073 break;
2074
2075 case ODM_CMNINFO_SEC_MODE:
2076 p_dm->p_security = (u8 *)p_value;
2077 break;
2078
2079 case ODM_CMNINFO_BW:
2080 p_dm->p_band_width = (u8 *)p_value;
2081 break;
2082
2083 case ODM_CMNINFO_CHNL:
2084 p_dm->p_channel = (u8 *)p_value;
2085 break;
2086
2087 case ODM_CMNINFO_SCAN:
2088 p_dm->p_is_scan_in_process = (boolean *)p_value;
2089 break;
2090
2091 case ODM_CMNINFO_POWER_SAVING:
2092 p_dm->p_is_power_saving = (boolean *)p_value;
2093 break;
2094
2095 case ODM_CMNINFO_ONE_PATH_CCA:
2096 p_dm->p_one_path_cca = (u8 *)p_value;
2097 break;
2098
2099 case ODM_CMNINFO_DRV_STOP:
2100 p_dm->p_is_driver_stopped = (boolean *)p_value;
2101 break;
2102
2103 case ODM_CMNINFO_PNP_IN:
2104 p_dm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value;
2105 break;
2106
2107 case ODM_CMNINFO_INIT_ON:
2108 p_dm->pinit_adpt_in_progress = (boolean *)p_value;
2109 break;
2110
2111 case ODM_CMNINFO_ANT_TEST:
2112 p_dm->p_antenna_test = (u8 *)p_value;
2113 break;
2114
2115 case ODM_CMNINFO_NET_CLOSED:
2116 p_dm->p_is_net_closed = (boolean *)p_value;
2117 break;
2118
2119 case ODM_CMNINFO_FORCED_RATE:
2120 p_dm->p_forced_data_rate = (u16 *)p_value;
2121 break;
2122 case ODM_CMNINFO_ANT_DIV:
2123 p_dm->p_enable_antdiv = (u8 *)p_value;
2124 break;
2125 case ODM_CMNINFO_ADAPTIVITY:
2126 p_dm->p_enable_adaptivity = (u8 *)p_value;
2127 break;
2128
2129 case ODM_CMNINFO_P2P_LINK:
2130 p_dm->dm_dig_table.is_p2p_in_process = (u8 *)p_value;
2131 break;
2132
2133 case ODM_CMNINFO_IS1ANTENNA:
2134 p_dm->p_is_1_antenna = (boolean *)p_value;
2135 break;
2136
2137 case ODM_CMNINFO_RFDEFAULTPATH:
2138 p_dm->p_rf_default_path = (u8 *)p_value;
2139 break;
2140
2141 case ODM_CMNINFO_FCS_MODE:
2142 p_dm->p_is_fcs_mode_enable = (boolean *)p_value;
2143 break;
2144 /*add by YuChen for beamforming PhyDM*/
2145 case ODM_CMNINFO_HUBUSBMODE:
2146 p_dm->hub_usb_mode = (u8 *)p_value;
2147 break;
2148 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2149 p_dm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value;
2150 break;
2151 case ODM_CMNINFO_TX_TP:
2152 p_dm->p_current_tx_tp = (u32 *)p_value;
2153 break;
2154 case ODM_CMNINFO_RX_TP:
2155 p_dm->p_current_rx_tp = (u32 *)p_value;
2156 break;
2157 case ODM_CMNINFO_SOUNDING_SEQ:
2158 p_dm->p_sounding_seq = (u8 *)p_value;
2159 break;
2160 #ifdef CONFIG_PHYDM_DFS_MASTER
2161 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2162 p_dm->dfs_master_enabled = (u8 *)p_value;
2163 break;
2164 #endif
2165 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2166 p_dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value;
2167 break;
2168 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2169 p_dm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value;
2170 break;
2171 case ODM_CMNINFO_SOFT_AP_MODE:
2172 p_dm->p_soft_ap_mode = (u32 *)p_value;
2173 break;
2174 case ODM_CMNINFO_MP_MODE:
2175 p_dm->p_mp_mode = (u8 *)p_value;
2176 break;
2177 case ODM_CMNINFO_INTERRUPT_MASK:
2178 p_dm->p_interrupt_mask = (u32 *)p_value;
2179 break;
2180 case ODM_CMNINFO_BB_OPERATION_MODE:
2181 p_dm->p_bb_op_mode = (u8 *)p_value;
2182 break;
2183
2184 default:
2185 /*do nothing*/
2186 break;
2187
2188 }
2189
2190 }
2191 /*
2192 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2193 * */
2194 void
odm_cmn_info_update(struct PHY_DM_STRUCT * p_dm,u32 cmn_info,u64 value)2195 odm_cmn_info_update(
2196 struct PHY_DM_STRUCT *p_dm,
2197 u32 cmn_info,
2198 u64 value
2199 )
2200 {
2201 /* */
2202 /* This init variable may be changed in run time. */
2203 /* */
2204 switch (cmn_info) {
2205 case ODM_CMNINFO_LINK_IN_PROGRESS:
2206 p_dm->is_link_in_process = (boolean)value;
2207 break;
2208
2209 case ODM_CMNINFO_ABILITY:
2210 p_dm->support_ability = (u64)value;
2211 break;
2212
2213 case ODM_CMNINFO_RF_TYPE:
2214 p_dm->rf_type = (u8)value;
2215 break;
2216
2217 case ODM_CMNINFO_WIFI_DIRECT:
2218 p_dm->is_wifi_direct = (boolean)value;
2219 break;
2220
2221 case ODM_CMNINFO_WIFI_DISPLAY:
2222 p_dm->is_wifi_display = (boolean)value;
2223 break;
2224
2225 case ODM_CMNINFO_LINK:
2226 p_dm->is_linked = (boolean)value;
2227 break;
2228
2229 case ODM_CMNINFO_CMW500LINK:
2230 p_dm->iot_table.is_linked_cmw500 = (boolean)value;
2231 break;
2232
2233 case ODM_CMNINFO_STATION_STATE:
2234 p_dm->bsta_state = (boolean)value;
2235 break;
2236
2237 case ODM_CMNINFO_RSSI_MIN:
2238 p_dm->rssi_min = (u8)value;
2239 break;
2240
2241 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2242 p_dm->rssi_min_by_path = (u8)value;
2243 break;
2244
2245 case ODM_CMNINFO_DBG_COMP:
2246 p_dm->debug_components = (u64)value;
2247 break;
2248
2249 case ODM_CMNINFO_DBG_LEVEL:
2250 p_dm->debug_level = (u32)value;
2251 break;
2252
2253 #ifdef ODM_CONFIG_BT_COEXIST
2254 /* The following is for BT HS mode and BT coexist mechanism. */
2255 case ODM_CMNINFO_BT_ENABLED:
2256 p_dm->bt_info_table.is_bt_enabled = (boolean)value;
2257 break;
2258
2259 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2260 p_dm->bt_info_table.is_bt_connect_process = (boolean)value;
2261 break;
2262
2263 case ODM_CMNINFO_BT_HS_RSSI:
2264 p_dm->bt_info_table.bt_hs_rssi = (u8)value;
2265 break;
2266
2267 case ODM_CMNINFO_BT_OPERATION:
2268 p_dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2269 break;
2270
2271 case ODM_CMNINFO_BT_LIMITED_DIG:
2272 p_dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2273 break;
2274 #endif
2275
2276 case ODM_CMNINFO_AP_TOTAL_NUM:
2277 p_dm->ap_total_num = (u8)value;
2278 break;
2279
2280 case ODM_CMNINFO_POWER_TRAINING:
2281 p_dm->is_disable_power_training = (boolean)value;
2282 break;
2283
2284 #ifdef CONFIG_PHYDM_DFS_MASTER
2285 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2286 p_dm->dfs_region_domain = (u8)value;
2287 break;
2288 #endif
2289
2290 #if 0
2291 case ODM_CMNINFO_OP_MODE:
2292 p_dm->op_mode = (u8)value;
2293 break;
2294
2295 case ODM_CMNINFO_BAND:
2296 p_dm->band_type = (u8)value;
2297 break;
2298
2299 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2300 p_dm->sec_ch_offset = (u8)value;
2301 break;
2302
2303 case ODM_CMNINFO_SEC_MODE:
2304 p_dm->security = (u8)value;
2305 break;
2306
2307 case ODM_CMNINFO_BW:
2308 p_dm->band_width = (u8)value;
2309 break;
2310
2311 case ODM_CMNINFO_CHNL:
2312 p_dm->channel = (u8)value;
2313 break;
2314 #endif
2315 default:
2316 /* do nothing */
2317 break;
2318 }
2319
2320
2321 }
2322
2323 u32
phydm_cmn_info_query(struct PHY_DM_STRUCT * p_dm,enum phydm_info_query_e info_type)2324 phydm_cmn_info_query(
2325 struct PHY_DM_STRUCT *p_dm,
2326 enum phydm_info_query_e info_type
2327 )
2328 {
2329 struct phydm_fa_struct *p_fa_t = &(p_dm->false_alm_cnt);
2330 struct phydm_dig_struct *p_dig_t = &p_dm->dm_dig_table;
2331 struct _CCX_INFO *ccx_info = &p_dm->dm_ccx_info;
2332
2333 switch (info_type) {
2334
2335 /*=== [FA Relative] ===========================================*/
2336 case PHYDM_INFO_FA_OFDM:
2337 return p_fa_t->cnt_ofdm_fail;
2338
2339 case PHYDM_INFO_FA_CCK:
2340 return p_fa_t->cnt_cck_fail;
2341
2342 case PHYDM_INFO_FA_TOTAL:
2343 return p_fa_t->cnt_all;
2344
2345 case PHYDM_INFO_CCA_OFDM:
2346 return p_fa_t->cnt_ofdm_cca;
2347
2348 case PHYDM_INFO_CCA_CCK:
2349 return p_fa_t->cnt_cck_cca;
2350
2351 case PHYDM_INFO_CCA_ALL:
2352 return p_fa_t->cnt_cca_all;
2353
2354 case PHYDM_INFO_CRC32_OK_VHT:
2355 return p_fa_t->cnt_vht_crc32_ok;
2356
2357 case PHYDM_INFO_CRC32_OK_HT:
2358 return p_fa_t->cnt_ht_crc32_ok;
2359
2360 case PHYDM_INFO_CRC32_OK_LEGACY:
2361 return p_fa_t->cnt_ofdm_crc32_ok;
2362
2363 case PHYDM_INFO_CRC32_OK_CCK:
2364 return p_fa_t->cnt_cck_crc32_ok;
2365
2366 case PHYDM_INFO_CRC32_ERROR_VHT:
2367 return p_fa_t->cnt_vht_crc32_error;
2368
2369 case PHYDM_INFO_CRC32_ERROR_HT:
2370 return p_fa_t->cnt_ht_crc32_error;
2371
2372 case PHYDM_INFO_CRC32_ERROR_LEGACY:
2373 return p_fa_t->cnt_ofdm_crc32_error;
2374
2375 case PHYDM_INFO_CRC32_ERROR_CCK:
2376 return p_fa_t->cnt_cck_crc32_error;
2377
2378 case PHYDM_INFO_EDCCA_FLAG:
2379 return p_fa_t->edcca_flag;
2380
2381 case PHYDM_INFO_OFDM_ENABLE:
2382 return p_fa_t->ofdm_block_enable;
2383
2384 case PHYDM_INFO_CCK_ENABLE:
2385 return p_fa_t->cck_block_enable;
2386
2387 case PHYDM_INFO_DBG_PORT_0:
2388 return p_fa_t->dbg_port0;
2389
2390 case PHYDM_INFO_CRC32_OK_HT_AGG:
2391 return p_fa_t->cnt_ht_crc32_ok_agg;
2392
2393 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
2394 return p_fa_t->cnt_ht_crc32_error_agg;
2395
2396 /*=== [DIG] ================================================*/
2397
2398 case PHYDM_INFO_CURR_IGI:
2399 return p_dig_t->cur_ig_value;
2400
2401 /*=== [RSSI] ===============================================*/
2402 case PHYDM_INFO_RSSI_MIN:
2403 return (u32)p_dm->rssi_min;
2404
2405 case PHYDM_INFO_RSSI_MAX:
2406 return (u32)p_dm->rssi_max;
2407
2408 case PHYDM_INFO_CLM_RATIO :
2409 return (u32)ccx_info->clm_ratio;
2410 case PHYDM_INFO_NHM_RATIO :
2411 return (u32)ccx_info->nhm_ratio;
2412 default:
2413 return 0xffffffff;
2414
2415 }
2416 }
2417
2418
2419 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2420 void
odm_init_all_work_items(struct PHY_DM_STRUCT * p_dm)2421 odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm)
2422 {
2423
2424 struct _ADAPTER *p_adapter = p_dm->adapter;
2425 #if USE_WORKITEM
2426
2427 #ifdef CONFIG_DYNAMIC_RX_PATH
2428 odm_initialize_work_item(p_dm,
2429 &p_dm->dm_drp_table.phydm_dynamic_rx_path_workitem,
2430 (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback,
2431 (void *)p_adapter,
2432 "DynamicRxPathWorkitem");
2433
2434 #endif
2435
2436 #ifdef CONFIG_ADAPTIVE_SOML
2437 odm_initialize_work_item(p_dm,
2438 &p_dm->dm_soml_table.phydm_adaptive_soml_workitem,
2439 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
2440 (void *)p_adapter,
2441 "AdaptiveSOMLWorkitem");
2442 #endif
2443
2444 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2445 odm_initialize_work_item(p_dm,
2446 &p_dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2447 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2448 (void *)p_adapter,
2449 "AntennaSwitchWorkitem");
2450 #endif
2451 #if (defined(CONFIG_HL_SMART_ANTENNA))
2452 odm_initialize_work_item(p_dm,
2453 &p_dm->dm_sat_table.hl_smart_antenna_workitem,
2454 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
2455 (void *)p_adapter,
2456 "hl_smart_ant_workitem");
2457
2458 odm_initialize_work_item(p_dm,
2459 &p_dm->dm_sat_table.hl_smart_antenna_decision_workitem,
2460 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
2461 (void *)p_adapter,
2462 "hl_smart_ant_decision_workitem");
2463 #endif
2464
2465 odm_initialize_work_item(
2466 p_dm,
2467 &(p_dm->path_div_switch_workitem),
2468 (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback,
2469 (void *)p_adapter,
2470 "SWAS_WorkItem");
2471
2472 odm_initialize_work_item(
2473 p_dm,
2474 &(p_dm->cck_path_diversity_workitem),
2475 (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback,
2476 (void *)p_adapter,
2477 "CCKTXPathDiversityWorkItem");
2478
2479 odm_initialize_work_item(
2480 p_dm,
2481 &(p_dm->ra_rpt_workitem),
2482 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
2483 (void *)p_adapter,
2484 "ra_rpt_workitem");
2485
2486 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2487 odm_initialize_work_item(
2488 p_dm,
2489 &(p_dm->fast_ant_training_workitem),
2490 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
2491 (void *)p_adapter,
2492 "fast_ant_training_workitem");
2493 #endif
2494
2495 #endif /*#if USE_WORKITEM*/
2496
2497 #if (BEAMFORMING_SUPPORT == 1)
2498 odm_initialize_work_item(
2499 p_dm,
2500 &(p_dm->beamforming_info.txbf_info.txbf_enter_work_item),
2501 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
2502 (void *)p_adapter,
2503 "txbf_enter_work_item");
2504
2505 odm_initialize_work_item(
2506 p_dm,
2507 &(p_dm->beamforming_info.txbf_info.txbf_leave_work_item),
2508 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
2509 (void *)p_adapter,
2510 "txbf_leave_work_item");
2511
2512 odm_initialize_work_item(
2513 p_dm,
2514 &(p_dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item),
2515 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
2516 (void *)p_adapter,
2517 "txbf_fw_ndpa_work_item");
2518
2519 odm_initialize_work_item(
2520 p_dm,
2521 &(p_dm->beamforming_info.txbf_info.txbf_clk_work_item),
2522 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
2523 (void *)p_adapter,
2524 "txbf_clk_work_item");
2525
2526 odm_initialize_work_item(
2527 p_dm,
2528 &(p_dm->beamforming_info.txbf_info.txbf_rate_work_item),
2529 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
2530 (void *)p_adapter,
2531 "txbf_rate_work_item");
2532
2533 odm_initialize_work_item(
2534 p_dm,
2535 &(p_dm->beamforming_info.txbf_info.txbf_status_work_item),
2536 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
2537 (void *)p_adapter,
2538 "txbf_status_work_item");
2539
2540 odm_initialize_work_item(
2541 p_dm,
2542 &(p_dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item),
2543 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
2544 (void *)p_adapter,
2545 "txbf_reset_tx_path_work_item");
2546
2547 odm_initialize_work_item(
2548 p_dm,
2549 &(p_dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item),
2550 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
2551 (void *)p_adapter,
2552 "txbf_get_tx_rate_work_item");
2553 #endif
2554
2555 odm_initialize_work_item(
2556 p_dm,
2557 &(p_dm->adaptivity.phydm_pause_edcca_work_item),
2558 (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback,
2559 (void *)p_adapter,
2560 "phydm_pause_edcca_work_item");
2561
2562 odm_initialize_work_item(
2563 p_dm,
2564 &(p_dm->adaptivity.phydm_resume_edcca_work_item),
2565 (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback,
2566 (void *)p_adapter,
2567 "phydm_resume_edcca_work_item");
2568
2569 #if (PHYDM_LA_MODE_SUPPORT == 1)
2570 odm_initialize_work_item(
2571 p_dm,
2572 &(p_dm->adcsmp.adc_smp_work_item),
2573 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2574 (void *)p_adapter,
2575 "adc_smp_work_item");
2576
2577 odm_initialize_work_item(
2578 p_dm,
2579 &(p_dm->adcsmp.adc_smp_work_item_1),
2580 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2581 (void *)p_adapter,
2582 "adc_smp_work_item_1");
2583 #endif
2584
2585 }
2586
2587 void
odm_free_all_work_items(struct PHY_DM_STRUCT * p_dm)2588 odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm)
2589 {
2590 #if USE_WORKITEM
2591
2592 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2593 odm_free_work_item(&(p_dm->dm_swat_table.phydm_sw_antenna_switch_workitem));
2594 #endif
2595
2596 #ifdef CONFIG_DYNAMIC_RX_PATH
2597 odm_free_work_item(&(p_dm->dm_drp_table.phydm_dynamic_rx_path_workitem));
2598 #endif
2599
2600 #ifdef CONFIG_ADAPTIVE_SOML
2601 odm_free_work_item(&(p_dm->dm_soml_table.phydm_adaptive_soml_workitem));
2602 #endif
2603
2604
2605 #if (defined(CONFIG_HL_SMART_ANTENNA))
2606 odm_free_work_item(&(p_dm->dm_sat_table.hl_smart_antenna_workitem));
2607 odm_free_work_item(&(p_dm->dm_sat_table.hl_smart_antenna_decision_workitem));
2608 #endif
2609
2610 odm_free_work_item(&(p_dm->path_div_switch_workitem));
2611 odm_free_work_item(&(p_dm->cck_path_diversity_workitem));
2612 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2613 odm_free_work_item(&(p_dm->fast_ant_training_workitem));
2614 #endif
2615 odm_free_work_item(&(p_dm->ra_rpt_workitem));
2616 /*odm_free_work_item((&p_dm->sbdcnt_workitem));*/
2617 #endif
2618
2619 #if (BEAMFORMING_SUPPORT == 1)
2620 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_enter_work_item));
2621 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_leave_work_item));
2622 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
2623 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_clk_work_item));
2624 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_rate_work_item));
2625 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_status_work_item));
2626 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
2627 odm_free_work_item((&p_dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
2628 #endif
2629
2630 odm_free_work_item((&p_dm->adaptivity.phydm_pause_edcca_work_item));
2631 odm_free_work_item((&p_dm->adaptivity.phydm_resume_edcca_work_item));
2632
2633 #if (PHYDM_LA_MODE_SUPPORT == 1)
2634 odm_free_work_item((&p_dm->adcsmp.adc_smp_work_item));
2635 odm_free_work_item((&p_dm->adcsmp.adc_smp_work_item_1));
2636 #endif
2637
2638 }
2639 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
2640
2641 void
odm_init_all_timers(struct PHY_DM_STRUCT * p_dm)2642 odm_init_all_timers(
2643 struct PHY_DM_STRUCT *p_dm
2644 )
2645 {
2646 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2647 odm_ant_div_timers(p_dm, INIT_ANTDIV_TIMMER);
2648 #endif
2649
2650 phydm_adaptive_soml_timers(p_dm, INIT_SOML_TIMMER);
2651
2652 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2653 phydm_lna_sat_chk_timers(p_dm, INIT_LNA_SAT_CHK_TIMMER);
2654 #endif
2655
2656 #ifdef CONFIG_DYNAMIC_RX_PATH
2657 phydm_dynamic_rx_path_timers(p_dm, INIT_DRP_TIMMER);
2658 #endif
2659
2660 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2661 odm_initialize_timer(p_dm, &p_dm->path_div_switch_timer,
2662 (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer");
2663 odm_initialize_timer(p_dm, &p_dm->cck_path_diversity_timer,
2664 (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer");
2665 odm_initialize_timer(p_dm, &p_dm->sbdcnt_timer,
2666 (void *)phydm_sbd_callback, NULL, "SbdTimer");
2667 #if (BEAMFORMING_SUPPORT == 1)
2668 odm_initialize_timer(p_dm, &p_dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
2669 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer");
2670 #endif
2671 #endif
2672
2673 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2674 #if (BEAMFORMING_SUPPORT == 1)
2675 odm_initialize_timer(p_dm, &p_dm->beamforming_info.beamforming_timer,
2676 (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer");
2677 #endif
2678 #endif
2679 }
2680
2681 void
odm_cancel_all_timers(struct PHY_DM_STRUCT * p_dm)2682 odm_cancel_all_timers(
2683 struct PHY_DM_STRUCT *p_dm
2684 )
2685 {
2686 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2687 /* */
2688 /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */
2689 /* win7 platform. */
2690 /* */
2691 HAL_ADAPTER_STS_CHK(p_dm);
2692 #endif
2693
2694 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2695 odm_ant_div_timers(p_dm, CANCEL_ANTDIV_TIMMER);
2696 #endif
2697
2698 phydm_adaptive_soml_timers(p_dm, CANCEL_SOML_TIMMER);
2699
2700 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2701 phydm_lna_sat_chk_timers(p_dm, CANCEL_LNA_SAT_CHK_TIMMER);
2702 #endif
2703
2704
2705 #ifdef CONFIG_DYNAMIC_RX_PATH
2706 phydm_dynamic_rx_path_timers(p_dm, CANCEL_DRP_TIMMER);
2707 #endif
2708
2709 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2710 odm_cancel_timer(p_dm, &p_dm->path_div_switch_timer);
2711 odm_cancel_timer(p_dm, &p_dm->cck_path_diversity_timer);
2712 odm_cancel_timer(p_dm, &p_dm->sbdcnt_timer);
2713 #if (BEAMFORMING_SUPPORT == 1)
2714 odm_cancel_timer(p_dm, &p_dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2715 #endif
2716 #endif
2717
2718 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2719 #if (BEAMFORMING_SUPPORT == 1)
2720 odm_cancel_timer(p_dm, &p_dm->beamforming_info.beamforming_timer);
2721 #endif
2722 #endif
2723
2724 }
2725
2726
2727 void
odm_release_all_timers(struct PHY_DM_STRUCT * p_dm)2728 odm_release_all_timers(
2729 struct PHY_DM_STRUCT *p_dm
2730 )
2731 {
2732 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2733 odm_ant_div_timers(p_dm, RELEASE_ANTDIV_TIMMER);
2734 #endif
2735 phydm_adaptive_soml_timers(p_dm, RELEASE_SOML_TIMMER);
2736
2737 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2738 phydm_lna_sat_chk_timers(p_dm, RELEASE_LNA_SAT_CHK_TIMMER);
2739 #endif
2740
2741 #ifdef CONFIG_DYNAMIC_RX_PATH
2742 phydm_dynamic_rx_path_timers(p_dm, RELEASE_DRP_TIMMER);
2743 #endif
2744
2745 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2746 odm_release_timer(p_dm, &p_dm->path_div_switch_timer);
2747 odm_release_timer(p_dm, &p_dm->cck_path_diversity_timer);
2748 odm_release_timer(p_dm, &p_dm->sbdcnt_timer);
2749 #if (BEAMFORMING_SUPPORT == 1)
2750 odm_release_timer(p_dm, &p_dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2751 #endif
2752 #endif
2753
2754 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2755 #if (BEAMFORMING_SUPPORT == 1)
2756 odm_release_timer(p_dm, &p_dm->beamforming_info.beamforming_timer);
2757 #endif
2758 #endif
2759 }
2760
2761
2762 /* 3============================================================
2763 * 3 Tx Power Tracking
2764 * 3============================================================ */
2765
2766
2767
2768
2769 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2770 void
odm_init_all_threads(struct PHY_DM_STRUCT * p_dm)2771 odm_init_all_threads(
2772 struct PHY_DM_STRUCT *p_dm
2773 )
2774 {
2775 #ifdef TPT_THREAD
2776 k_tpt_task_init(p_dm->priv);
2777 #endif
2778 }
2779
2780 void
odm_stop_all_threads(struct PHY_DM_STRUCT * p_dm)2781 odm_stop_all_threads(
2782 struct PHY_DM_STRUCT *p_dm
2783 )
2784 {
2785 #ifdef TPT_THREAD
2786 k_tpt_task_stop(p_dm->priv);
2787 #endif
2788 }
2789 #endif
2790
2791 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2792 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
odm_dtc(struct PHY_DM_STRUCT * p_dm)2793 void odm_dtc(struct PHY_DM_STRUCT *p_dm)
2794 {
2795 #ifdef CONFIG_DM_RESP_TXAGC
2796 #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */
2797 #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
2798
2799 /* RSSI vs TX power step mapping: decade TX power */
2800 static const u8 dtc_table_down[] = {
2801 DTC_BASE,
2802 (DTC_BASE + 5),
2803 (DTC_BASE + 10),
2804 (DTC_BASE + 15),
2805 (DTC_BASE + 20),
2806 (DTC_BASE + 25)
2807 };
2808
2809 /* RSSI vs TX power step mapping: increase TX power */
2810 static const u8 dtc_table_up[] = {
2811 DTC_DWN_BASE,
2812 (DTC_DWN_BASE - 5),
2813 (DTC_DWN_BASE - 10),
2814 (DTC_DWN_BASE - 15),
2815 (DTC_DWN_BASE - 15),
2816 (DTC_DWN_BASE - 20),
2817 (DTC_DWN_BASE - 20),
2818 (DTC_DWN_BASE - 25),
2819 (DTC_DWN_BASE - 25),
2820 (DTC_DWN_BASE - 30),
2821 (DTC_DWN_BASE - 35)
2822 };
2823
2824 u8 i;
2825 u8 dtc_steps = 0;
2826 u8 sign;
2827 u8 resp_txagc = 0;
2828
2829 #if 0
2830 /* As DIG is disabled, DTC is also disable */
2831 if (!(p_dm->support_ability & ODM_XXXXXX))
2832 return;
2833 #endif
2834
2835 if (p_dm->rssi_min > DTC_BASE) {
2836 /* need to decade the CTS TX power */
2837 sign = 1;
2838 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
2839 if ((dtc_table_down[i] >= p_dm->rssi_min) || (dtc_steps >= 6))
2840 break;
2841 else
2842 dtc_steps++;
2843 }
2844 }
2845 #if 0
2846 else if (p_dm->rssi_min > DTC_DWN_BASE) {
2847 /* needs to increase the CTS TX power */
2848 sign = 0;
2849 dtc_steps = 1;
2850 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
2851 if ((dtc_table_up[i] <= p_dm->rssi_min) || (dtc_steps >= 10))
2852 break;
2853 else
2854 dtc_steps++;
2855 }
2856 }
2857 #endif
2858 else {
2859 sign = 0;
2860 dtc_steps = 0;
2861 }
2862
2863 resp_txagc = dtc_steps | (sign << 4);
2864 resp_txagc = resp_txagc | (resp_txagc << 5);
2865 odm_write_1byte(p_dm, 0x06d9, resp_txagc);
2866
2867 PHYDM_DBG(p_dm, ODM_COMP_PWR_TRAIN, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n",
2868 __func__, p_dm->rssi_min, sign ? "minus" : "plus", dtc_steps));
2869 #endif /* CONFIG_RESP_TXAGC_ADJUST */
2870 }
2871
2872 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
2873
2874
2875 /*<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
2876 void
phydm_dc_cancellation(struct PHY_DM_STRUCT * p_dm)2877 phydm_dc_cancellation(
2878 struct PHY_DM_STRUCT *p_dm
2879
2880 )
2881 {
2882 #ifdef PHYDM_DC_CANCELLATION
2883 u32 offset_i_hex[ODM_RF_PATH_MAX] = {0};
2884 u32 offset_q_hex[ODM_RF_PATH_MAX] = {0};
2885 u32 reg_value32[ODM_RF_PATH_MAX] = {0};
2886 u8 path = RF_PATH_A;
2887
2888 if (!(p_dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
2889 return;
2890
2891 if ((p_dm->support_ic_type & ODM_RTL8188F) && (p_dm->cut_version < ODM_CUT_D))
2892 return;
2893
2894 /*DC_Estimation (only for 2x2 ic now) */
2895
2896 for (path = RF_PATH_A; path < ODM_RF_PATH_MAX; path++) {
2897 if (p_dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
2898 if (!phydm_set_bb_dbg_port(p_dm,
2899 BB_DBGPORT_PRIORITY_2, 0x235)) {/*set debug port to 0x235*/
2900 PHYDM_DBG(p_dm, ODM_COMP_API,
2901 ("[DC Cancellation] Set Debug port Fail"));
2902 return;
2903 }
2904 } else if (p_dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
2905 if (!phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_2, 0x200)) {
2906 /*set debug port to 0x200*/
2907 PHYDM_DBG(p_dm, ODM_COMP_API,
2908 ("[DC Cancellation] Set Debug port Fail"));
2909 return;
2910 }
2911 phydm_bb_dbg_port_header_sel(p_dm, 0x0);
2912 if (p_dm->rf_type > RF_1T1R) {
2913 if (!phydm_set_bb_dbg_port(p_dm, BB_DBGPORT_PRIORITY_2, 0x202)) {
2914 /*set debug port to 0x200*/
2915 PHYDM_DBG(p_dm, ODM_COMP_API,
2916 ("[DC Cancellation] Set Debug port Fail"));
2917 return;
2918 }
2919 phydm_bb_dbg_port_header_sel(p_dm, 0x0);
2920 }
2921 }
2922
2923 odm_write_dig(p_dm, 0x7E);
2924
2925 if (p_dm->support_ic_type & ODM_IC_11N_SERIES)
2926 odm_set_bb_reg(p_dm, 0x88c, BIT(21)|BIT(20), 0x3);
2927 else {
2928 odm_set_bb_reg(p_dm, 0xc00, BIT(1)|BIT(0), 0x0);
2929 if (p_dm->rf_type > RF_1T1R)
2930 odm_set_bb_reg(p_dm, 0xe00, BIT(1)|BIT(0), 0x0);
2931 }
2932 odm_set_bb_reg(p_dm, 0xa78, MASKBYTE1, 0x0); /*disable CCK DCNF*/
2933
2934 PHYDM_DBG(p_dm, ODM_COMP_API, ("DC cancellation Begin!!!"));
2935
2936 phydm_stop_ck320(p_dm, true); /*stop ck320*/
2937
2938 /* the same debug port both for path-a and path-b*/
2939 reg_value32[path] = phydm_get_bb_dbg_port_value(p_dm);
2940
2941 phydm_stop_ck320(p_dm, false); /*start ck320*/
2942
2943 if (p_dm->support_ic_type & ODM_IC_11N_SERIES) {
2944 odm_set_bb_reg(p_dm, 0x88c, BIT(21)|BIT(20), 0x0);
2945 } else {
2946 odm_set_bb_reg(p_dm, 0xc00, BIT(1)|BIT(0), 0x3);
2947 odm_set_bb_reg(p_dm, 0xe00, BIT(1)|BIT(0), 0x3);
2948 }
2949 odm_write_dig(p_dm, 0x20);
2950 phydm_release_bb_dbg_port(p_dm);
2951
2952 PHYDM_DBG(p_dm, ODM_COMP_API, ("DC cancellation OK!!!"));
2953 }
2954
2955 /*DC_Cancellation*/
2956 odm_set_bb_reg(p_dm, 0xa9c, BIT(20), 0x1); /*DC compensation to CCK data path*/
2957 if (p_dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
2958 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
2959 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
2960
2961 /*Before filling into registers, offset should be multiplexed (-1)*/
2962 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? (0x400 - offset_i_hex[1]) : (0x1ff - offset_i_hex[1]);
2963 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? (0x400 - offset_q_hex[1]) : (0x1ff - offset_q_hex[1]);
2964
2965 odm_set_bb_reg(p_dm, 0x950, 0x1ff, offset_i_hex[1]);
2966 odm_set_bb_reg(p_dm, 0x950, 0x1ff0000, offset_q_hex[1]);
2967 } else if (p_dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
2968
2969 /* Path-a */
2970 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
2971 offset_q_hex[0] = reg_value32[0] & 0x3ff;
2972
2973 /*Before filling into registers, offset should be multiplexed (-1)*/
2974 offset_i_hex[0] = 0x400 - offset_i_hex[0];
2975 offset_q_hex[0] = 0x400 - offset_q_hex[0];
2976
2977 odm_set_bb_reg(p_dm, 0xc10, 0x3c000000, ((0x3c0 & offset_i_hex[0]) >> 6));
2978 odm_set_bb_reg(p_dm, 0xc10, 0xfc00, (0x3f & offset_i_hex[0]));
2979 odm_set_bb_reg(p_dm, 0xc14, 0x3c000000, ((0x3c0 & offset_q_hex[0]) >> 6));
2980 odm_set_bb_reg(p_dm, 0xc14, 0xfc00, (0x3f & offset_q_hex[0]));
2981
2982 /* Path-b */
2983 if (p_dm->rf_type > RF_1T1R) {
2984
2985 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
2986 offset_q_hex[1] = reg_value32[1] & 0x3ff;
2987
2988 /*Before filling into registers, offset should be multiplexed (-1)*/
2989 offset_i_hex[1] = 0x400 - offset_i_hex[1];
2990 offset_q_hex[1] = 0x400 - offset_q_hex[1];
2991
2992 odm_set_bb_reg(p_dm, 0xe10, 0x3c000000, ((0x3c0 & offset_i_hex[1]) >> 6));
2993 odm_set_bb_reg(p_dm, 0xe10, 0xfc00, (0x3f & offset_i_hex[1]));
2994 odm_set_bb_reg(p_dm, 0xe14, 0x3c000000, ((0x3c0 & offset_q_hex[1]) >> 6));
2995 odm_set_bb_reg(p_dm, 0xe14, 0xfc00, (0x3f & offset_q_hex[1]));
2996 }
2997 }
2998 #endif
2999 }
3000
3001 void
phydm_receiver_blocking(void * p_dm_void)3002 phydm_receiver_blocking(
3003 void *p_dm_void
3004 )
3005 {
3006 #ifdef CONFIG_RECEIVER_BLOCKING
3007 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
3008 u32 channel = *p_dm->p_channel;
3009 u8 bw = *p_dm->p_band_width;
3010 u32 bb_regf0 = odm_get_bb_reg(p_dm, 0xf0, MASKDWORD);
3011
3012 if (!(p_dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT))
3013 return;
3014
3015 if ((p_dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) < 8) ||
3016 p_dm->support_ic_type & ODM_RTL8192E) { /*8188E_T version*/
3017 if (p_dm->consecutive_idlel_time > 10 && *p_dm->p_mp_mode == false && p_dm->adaptivity_enable == true) {
3018 if ((bw == CHANNEL_WIDTH_20) && (channel == 1)) {
3019 phydm_nbi_setting(p_dm, FUNC_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE);
3020 p_dm->is_receiver_blocking_en = true;
3021 } else if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) {
3022 phydm_nbi_setting(p_dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE);
3023 p_dm->is_receiver_blocking_en = true;
3024 } else if (p_dm->is_receiver_blocking_en && channel != 1 && channel != 13) {
3025 phydm_nbi_enable(p_dm, FUNC_DISABLE);
3026 odm_set_bb_reg(p_dm, 0xc40, 0x1f000000, 0x1f);
3027 p_dm->is_receiver_blocking_en = false;
3028 }
3029 return;
3030 }
3031 } else if ((p_dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) >= 8)) { /*8188E_S version*/
3032 if (p_dm->consecutive_idlel_time > 10 && *p_dm->p_mp_mode == false && p_dm->adaptivity_enable == true) {
3033 if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) {
3034 phydm_nbi_setting(p_dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE);
3035 p_dm->is_receiver_blocking_en = true;
3036 } else if (p_dm->is_receiver_blocking_en && channel != 13) {
3037 phydm_nbi_enable(p_dm, FUNC_DISABLE);
3038 odm_set_bb_reg(p_dm, 0xc40, 0x1f000000, 0x1f);
3039 p_dm->is_receiver_blocking_en = false;
3040 }
3041 return;
3042 }
3043 }
3044
3045 if (p_dm->is_receiver_blocking_en) {
3046 phydm_nbi_enable(p_dm, FUNC_DISABLE);
3047 odm_set_bb_reg(p_dm, 0xc40, 0x1f000000, 0x1f);
3048 p_dm->is_receiver_blocking_en = false;
3049 }
3050
3051 #endif
3052 }
3053