1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 #ifndef __HAL_PG_H__ 22 #define __HAL_PG_H__ 23 24 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F 25 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F 26 #define PPG_THERMAL_OFFSET_MASK 0x1F 27 #define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? (_ppg_v >> 1) : (-((_ppg_v) >> 1)))) 28 #define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) 29 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) 30 31 //==================================================== 32 // EEPROM/Efuse PG Offset for 88EE/88EU/88ES 33 //==================================================== 34 #define EEPROM_TX_PWR_INX_88E 0x10 35 36 #define EEPROM_ChannelPlan_88E 0xB8 37 #define EEPROM_XTAL_88E 0xB9 38 #define EEPROM_THERMAL_METER_88E 0xBA 39 #define EEPROM_IQK_LCK_88E 0xBB 40 41 #define EEPROM_RF_BOARD_OPTION_88E 0xC1 42 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 43 #define EEPROM_RF_BT_SETTING_88E 0xC3 44 #define EEPROM_VERSION_88E 0xC4 45 #define EEPROM_CustomID_88E 0xC5 46 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9 47 48 // RTL88EE 49 #define EEPROM_MAC_ADDR_88EE 0xD0 50 #define EEPROM_VID_88EE 0xD6 51 #define EEPROM_DID_88EE 0xD8 52 #define EEPROM_SVID_88EE 0xDA 53 #define EEPROM_SMID_88EE 0xDC 54 55 //RTL88EU 56 #define EEPROM_MAC_ADDR_88EU 0xD7 57 #define EEPROM_VID_88EU 0xD0 58 #define EEPROM_PID_88EU 0xD2 59 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8188EU,8192EU, 8812AU is the same 60 #define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104 61 62 // RTL88ES 63 #define EEPROM_MAC_ADDR_88ES 0x11A 64 //==================================================== 65 // EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES 66 //==================================================== 67 // 0x10 ~ 0x63 = TX power area. 68 #define EEPROM_TX_PWR_INX_8192E 0x10 69 70 #define EEPROM_ChannelPlan_8192E 0xB8 71 #define EEPROM_XTAL_8192E 0xB9 72 #define EEPROM_THERMAL_METER_8192E 0xBA 73 #define EEPROM_IQK_LCK_8192E 0xBB 74 #define EEPROM_2G_5G_PA_TYPE_8192E 0xBC 75 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD 76 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF 77 78 #define EEPROM_RF_BOARD_OPTION_8192E 0xC1 79 #define EEPROM_RF_FEATURE_OPTION_8192E 0xC2 80 #define EEPROM_RF_BT_SETTING_8192E 0xC3 81 #define EEPROM_VERSION_8192E 0xC4 82 #define EEPROM_CustomID_8192E 0xC5 83 #define EEPROM_TX_BBSWING_2G_8192E 0xC6 84 #define EEPROM_TX_BBSWING_5G_8192E 0xC7 85 #define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8 86 #define EEPROM_RF_ANTENNA_OPT_8192E 0xC9 87 #define EEPROM_RFE_OPTION_8192E 0xCA 88 89 // RTL8192EE 90 #define EEPROM_MAC_ADDR_8192EE 0xD0 91 #define EEPROM_VID_8192EE 0xD6 92 #define EEPROM_DID_8192EE 0xD8 93 #define EEPROM_SVID_8192EE 0xDA 94 #define EEPROM_SMID_8192EE 0xDC 95 96 //RTL8192EU 97 #define EEPROM_MAC_ADDR_8192EU 0xD7 98 #define EEPROM_VID_8192EU 0xD0 99 #define EEPROM_PID_8192EU 0xD2 100 #define EEPROM_PA_TYPE_8192EU 0xBC 101 #define EEPROM_LNA_TYPE_2G_8192EU 0xBD 102 #define EEPROM_LNA_TYPE_5G_8192EU 0xBF 103 104 // RTL8192ES 105 #define EEPROM_MAC_ADDR_8192ES 0x11A 106 //==================================================== 107 // EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS 108 //==================================================== 109 // 0x10 ~ 0x63 = TX power area. 110 #define EEPROM_USB_MODE_8812 0x08 111 #define EEPROM_TX_PWR_INX_8812 0x10 112 113 #define EEPROM_ChannelPlan_8812 0xB8 114 #define EEPROM_XTAL_8812 0xB9 115 #define EEPROM_THERMAL_METER_8812 0xBA 116 #define EEPROM_IQK_LCK_8812 0xBB 117 #define EEPROM_2G_5G_PA_TYPE_8812 0xBC 118 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD 119 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF 120 121 #define EEPROM_RF_BOARD_OPTION_8812 0xC1 122 #define EEPROM_RF_FEATURE_OPTION_8812 0xC2 123 #define EEPROM_RF_BT_SETTING_8812 0xC3 124 #define EEPROM_VERSION_8812 0xC4 125 #define EEPROM_CustomID_8812 0xC5 126 #define EEPROM_TX_BBSWING_2G_8812 0xC6 127 #define EEPROM_TX_BBSWING_5G_8812 0xC7 128 #define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8 129 #define EEPROM_RF_ANTENNA_OPT_8812 0xC9 130 #define EEPROM_RFE_OPTION_8812 0xCA 131 132 // RTL8812AE 133 #define EEPROM_MAC_ADDR_8812AE 0xD0 134 #define EEPROM_VID_8812AE 0xD6 135 #define EEPROM_DID_8812AE 0xD8 136 #define EEPROM_SVID_8812AE 0xDA 137 #define EEPROM_SMID_8812AE 0xDC 138 139 //RTL8812AU 140 #define EEPROM_MAC_ADDR_8812AU 0xD7 141 #define EEPROM_VID_8812AU 0xD0 142 #define EEPROM_PID_8812AU 0xD2 143 #define EEPROM_PA_TYPE_8812AU 0xBC 144 #define EEPROM_LNA_TYPE_2G_8812AU 0xBD 145 #define EEPROM_LNA_TYPE_5G_8812AU 0xBF 146 147 //RTL8814AU 148 #define EEPROM_MAC_ADDR_8814AU 0xD8 149 #define EEPROM_VID_8814AU 0xD0 150 #define EEPROM_PID_8814AU 0xD2 151 #define EEPROM_PA_TYPE_8814AU 0xBC 152 #define EEPROM_LNA_TYPE_2G_8814AU 0xBD 153 #define EEPROM_LNA_TYPE_5G_8814AU 0xBF 154 155 /* RTL8814AE */ 156 #define EEPROM_MAC_ADDR_8814AE 0xD0 157 #define EEPROM_VID_8814AE 0xD6 158 #define EEPROM_DID_8814AE 0xD8 159 #define EEPROM_SVID_8814AE 0xDA 160 #define EEPROM_SMID_8814AE 0xDC 161 162 //==================================================== 163 // EEPROM/Efuse PG Offset for 8814AU 164 //==================================================== 165 #define EEPROM_TX_PWR_INX_8814 0x10 166 #define EEPROM_ChannelPlan_8814 0xB8 167 #define EEPROM_XTAL_8814 0xB9 168 #define EEPROM_THERMAL_METER_8814 0xBA 169 #define EEPROM_IQK_LCK_8814 0xBB 170 171 172 #define EEPROM_PA_TYPE_8814 0xBC 173 #define EEPROM_LNA_TYPE_AB_2G_8814 0xBD 174 #define EEPROM_LNA_TYPE_CD_2G_8814 0xBE 175 #define EEPROM_LNA_TYPE_AB_5G_8814 0xBF 176 #define EEPROM_LNA_TYPE_CD_5G_8814 0xC0 177 #define EEPROM_RF_BOARD_OPTION_8814 0xC1 178 #define EEPROM_RF_BT_SETTING_8814 0xC3 179 #define EEPROM_VERSION_8814 0xC4 180 #define EEPROM_CustomID_8814 0xC5 181 #define EEPROM_TX_BBSWING_2G_8814 0xC6 182 #define EEPROM_TX_BBSWING_5G_8814 0xC7 183 #define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9 184 #define EEPROM_RFE_OPTION_8814 0xCA 185 186 //==================================================== 187 // EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS 188 //==================================================== 189 190 #define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) 191 #define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 192 193 #define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6 194 #define PPG_THERMAL_OFFSET_8821A 0x1F5 195 #define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4 196 #define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3 197 #define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2 198 #define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 199 #define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 200 201 #define EEPROM_TX_PWR_INX_8821 0x10 202 203 #define EEPROM_ChannelPlan_8821 0xB8 204 #define EEPROM_XTAL_8821 0xB9 205 #define EEPROM_THERMAL_METER_8821 0xBA 206 #define EEPROM_IQK_LCK_8821 0xBB 207 208 209 #define EEPROM_RF_BOARD_OPTION_8821 0xC1 210 #define EEPROM_RF_FEATURE_OPTION_8821 0xC2 211 #define EEPROM_RF_BT_SETTING_8821 0xC3 212 #define EEPROM_VERSION_8821 0xC4 213 #define EEPROM_CustomID_8821 0xC5 214 #define EEPROM_RF_ANTENNA_OPT_8821 0xC9 215 216 // RTL8821AE 217 #define EEPROM_MAC_ADDR_8821AE 0xD0 218 #define EEPROM_VID_8821AE 0xD6 219 #define EEPROM_DID_8821AE 0xD8 220 #define EEPROM_SVID_8821AE 0xDA 221 #define EEPROM_SMID_8821AE 0xDC 222 223 //RTL8821AU 224 #define EEPROM_PA_TYPE_8821AU 0xBC 225 #define EEPROM_LNA_TYPE_8821AU 0xBF 226 227 // RTL8821AS 228 #define EEPROM_MAC_ADDR_8821AS 0x11A 229 230 //RTL8821AU 231 #define EEPROM_MAC_ADDR_8821AU 0x107 232 #define EEPROM_VID_8821AU 0x100 233 #define EEPROM_PID_8821AU 0x102 234 235 236 //==================================================== 237 // EEPROM/Efuse PG Offset for 8192 SE/SU 238 //==================================================== 239 #define EEPROM_VID_92SE 0x0A 240 #define EEPROM_DID_92SE 0x0C 241 #define EEPROM_SVID_92SE 0x0E 242 #define EEPROM_SMID_92SE 0x10 243 244 #define EEPROM_MAC_ADDR_92S 0x12 245 246 #define EEPROM_TSSI_A_92SE 0x74 247 #define EEPROM_TSSI_B_92SE 0x75 248 249 #define EEPROM_Version_92SE 0x7C 250 251 252 #define EEPROM_VID_92SU 0x08 253 #define EEPROM_PID_92SU 0x0A 254 255 #define EEPROM_Version_92SU 0x50 256 #define EEPROM_TSSI_A_92SU 0x6b 257 #define EEPROM_TSSI_B_92SU 0x6c 258 259 /* ==================================================== 260 EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS 261 ==================================================== 262 */ 263 264 #define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) 265 #define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 266 267 #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE 268 #define PPG_THERMAL_OFFSET_8188F 0xEF 269 270 /* 0x10 ~ 0x63 = TX power area. */ 271 #define EEPROM_TX_PWR_INX_8188F 0x10 272 273 #define EEPROM_ChannelPlan_8188F 0xB8 274 #define EEPROM_XTAL_8188F 0xB9 275 #define EEPROM_THERMAL_METER_8188F 0xBA 276 #define EEPROM_IQK_LCK_8188F 0xBB 277 #define EEPROM_2G_5G_PA_TYPE_8188F 0xBC 278 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD 279 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF 280 281 #define EEPROM_RF_BOARD_OPTION_8188F 0xC1 282 #define EEPROM_FEATURE_OPTION_8188F 0xC2 283 #define EEPROM_RF_BT_SETTING_8188F 0xC3 284 #define EEPROM_VERSION_8188F 0xC4 285 #define EEPROM_CustomID_8188F 0xC5 286 #define EEPROM_TX_BBSWING_2G_8188F 0xC6 287 #define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8 288 #define EEPROM_RF_ANTENNA_OPT_8188F 0xC9 289 #define EEPROM_RFE_OPTION_8188F 0xCA 290 #define EEPROM_CUSTOMER_ID_8188F 0x7F 291 #define EEPROM_SUBCUSTOMER_ID_8188F 0x59 292 293 /* RTL8188FU */ 294 #define EEPROM_MAC_ADDR_8188FU 0xD7 295 #define EEPROM_VID_8188FU 0xD0 296 #define EEPROM_PID_8188FU 0xD2 297 #define EEPROM_PA_TYPE_8188FU 0xBC 298 #define EEPROM_LNA_TYPE_2G_8188FU 0xBD 299 #define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4 300 301 /* RTL8188FS */ 302 #define EEPROM_MAC_ADDR_8188FS 0x11A 303 #define EEPROM_Voltage_ADDR_8188F 0x8 304 305 //==================================================== 306 // EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS 307 //==================================================== 308 // 0x10 ~ 0x63 = TX power area. 309 #define EEPROM_TX_PWR_INX_8723B 0x10 310 311 #define EEPROM_ChannelPlan_8723B 0xB8 312 #define EEPROM_XTAL_8723B 0xB9 313 #define EEPROM_THERMAL_METER_8723B 0xBA 314 #define EEPROM_IQK_LCK_8723B 0xBB 315 #define EEPROM_2G_5G_PA_TYPE_8723B 0xBC 316 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD 317 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF 318 319 #define EEPROM_RF_BOARD_OPTION_8723B 0xC1 320 #define EEPROM_FEATURE_OPTION_8723B 0xC2 321 #define EEPROM_RF_BT_SETTING_8723B 0xC3 322 #define EEPROM_VERSION_8723B 0xC4 323 #define EEPROM_CustomID_8723B 0xC5 324 #define EEPROM_TX_BBSWING_2G_8723B 0xC6 325 #define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8 326 #define EEPROM_RF_ANTENNA_OPT_8723B 0xC9 327 #define EEPROM_RFE_OPTION_8723B 0xCA 328 329 // RTL8723BE 330 #define EEPROM_MAC_ADDR_8723BE 0xD0 331 #define EEPROM_VID_8723BE 0xD6 332 #define EEPROM_DID_8723BE 0xD8 333 #define EEPROM_SVID_8723BE 0xDA 334 #define EEPROM_SMID_8723BE 0xDC 335 336 //RTL8723BU 337 #define EEPROM_MAC_ADDR_8723BU 0x107 338 #define EEPROM_VID_8723BU 0x100 339 #define EEPROM_PID_8723BU 0x102 340 #define EEPROM_PA_TYPE_8723BU 0xBC 341 #define EEPROM_LNA_TYPE_2G_8723BU 0xBD 342 343 344 //RTL8723BS 345 #define EEPROM_MAC_ADDR_8723BS 0x11A 346 #define EEPROM_Voltage_ADDR_8723B 0x8 347 348 //==================================================== 349 // EEPROM/Efuse PG Offset for 8703BS 350 //==================================================== 351 #define EEPROM_TX_PWR_INX_8703B 0x10 352 353 #define EEPROM_ChannelPlan_8703B 0xB8 354 #define EEPROM_XTAL_8703B 0xB9 355 #define EEPROM_THERMAL_METER_8703B 0xBA 356 #define EEPROM_IQK_LCK_8703B 0xBB 357 #define EEPROM_2G_5G_PA_TYPE_8703B 0xBC 358 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD 359 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF 360 361 #define EEPROM_RF_BOARD_OPTION_8703B 0xC1 362 #define EEPROM_FEATURE_OPTION_8703B 0xC2 363 #define EEPROM_RF_BT_SETTING_8703B 0xC3 364 #define EEPROM_VERSION_8703B 0xC4 365 #define EEPROM_CustomID_8703B 0xC5 366 #define EEPROM_TX_BBSWING_2G_8703B 0xC6 367 #define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8 368 #define EEPROM_RF_ANTENNA_OPT_8703B 0xC9 369 #define EEPROM_RFE_OPTION_8703B 0xCA 370 371 //RTL8703BS 372 #define EEPROM_MAC_ADDR_8703BS 0x11A 373 #define EEPROM_Voltage_ADDR_8703B 0x8 374 375 //==================================================== 376 // EEPROM/Efuse Value Type 377 //==================================================== 378 #define EETYPE_TX_PWR 0x0 379 //==================================================== 380 // EEPROM/Efuse Default Value 381 //==================================================== 382 #define EEPROM_CID_DEFAULT 0x0 383 #define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek 384 #define EEPROM_CID_TOSHIBA 0x4 385 #define EEPROM_CID_CCX 0x10 386 #define EEPROM_CID_QMI 0x0D 387 #define EEPROM_CID_WHQL 0xFE 388 389 #define EEPROM_CHANNEL_PLAN_FCC 0x0 390 #define EEPROM_CHANNEL_PLAN_IC 0x1 391 #define EEPROM_CHANNEL_PLAN_ETSI 0x2 392 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 393 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 394 #define EEPROM_CHANNEL_PLAN_MKK 0x5 395 #define EEPROM_CHANNEL_PLAN_MKK1 0x6 396 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 397 #define EEPROM_CHANNEL_PLAN_TELEC 0x8 398 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 399 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 400 #define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB 401 #define EEPROM_CHANNEL_PLAN_CHIAN 0XC 402 #define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD 403 #define EEPROM_CHANNEL_PLAN_KOREA 0xE 404 #define EEPROM_CHANNEL_PLAN_TURKEY 0xF 405 #define EEPROM_CHANNEL_PLAN_JAPAN 0x10 406 #define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 407 #define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 408 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 409 #define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 410 411 #define EEPROM_USB_OPTIONAL1 0xE 412 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 413 414 #define RTL_EEPROM_ID 0x8129 415 #define EEPROM_Default_TSSI 0x0 416 #define EEPROM_Default_BoardType 0x02 417 #define EEPROM_Default_ThermalMeter 0x12 418 #define EEPROM_Default_ThermalMeter_92SU 0x7 419 #define EEPROM_Default_ThermalMeter_88E 0x18 420 #define EEPROM_Default_ThermalMeter_8812 0x18 421 #define EEPROM_Default_ThermalMeter_8192E 0x1A 422 #define EEPROM_Default_ThermalMeter_8723B 0x18 423 #define EEPROM_Default_ThermalMeter_8703B 0x18 424 #define EEPROM_Default_ThermalMeter_8188F 0x18 425 #define EEPROM_Default_ThermalMeter_8814A 0x18 426 427 428 #define EEPROM_Default_CrystalCap 0x0 429 #define EEPROM_Default_CrystalCap_8723A 0x20 430 #define EEPROM_Default_CrystalCap_88E 0x20 431 #define EEPROM_Default_CrystalCap_8812 0x20 432 #define EEPROM_Default_CrystalCap_8814 0x20 433 #define EEPROM_Default_CrystalCap_8192E 0x20 434 #define EEPROM_Default_CrystalCap_8723B 0x20 435 #define EEPROM_Default_CrystalCap_8703B 0x20 436 #define EEPROM_Default_CrystalCap_8188F 0x20 437 #define EEPROM_Default_CrystalFreq 0x0 438 #define EEPROM_Default_TxPowerLevel_92C 0x22 439 #define EEPROM_Default_TxPowerLevel_2G 0x2C 440 #define EEPROM_Default_TxPowerLevel_5G 0x22 441 #define EEPROM_Default_TxPowerLevel 0x22 442 #define EEPROM_Default_HT40_2SDiff 0x0 443 #define EEPROM_Default_HT20_Diff 2 444 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 445 #define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 446 #define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 447 #define EEPROM_Default_HT40_PwrMaxOffset 0 448 #define EEPROM_Default_HT20_PwrMaxOffset 0 449 450 #define EEPROM_Default_PID 0x1234 451 #define EEPROM_Default_VID 0x5678 452 #define EEPROM_Default_CustomerID 0xAB 453 #define EEPROM_Default_CustomerID_8188E 0x00 454 #define EEPROM_Default_SubCustomerID 0xCD 455 #define EEPROM_Default_Version 0 456 457 #define EEPROM_Default_externalPA_C9 0x00 458 #define EEPROM_Default_externalPA_CC 0xFF 459 #define EEPROM_Default_internalPA_SP3T_C9 0xAA 460 #define EEPROM_Default_internalPA_SP3T_CC 0xAF 461 #define EEPROM_Default_internalPA_SPDT_C9 0xAA 462 #ifdef CONFIG_PCI_HCI 463 #define EEPROM_Default_internalPA_SPDT_CC 0xA0 464 #else 465 #define EEPROM_Default_internalPA_SPDT_CC 0xFA 466 #endif 467 #define EEPROM_Default_PAType 0 468 #define EEPROM_Default_LNAType 0 469 470 //New EFUSE deafult value 471 #define EEPROM_DEFAULT_24G_INDEX 0x2D 472 #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 473 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 474 475 #define EEPROM_DEFAULT_5G_INDEX 0X2A 476 #define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 477 #define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 478 479 #define EEPROM_DEFAULT_DIFF 0XFE 480 #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F 481 #define EEPROM_DEFAULT_BOARD_OPTION 0x00 482 #define EEPROM_DEFAULT_RFE_OPTION_8192E 0x03 483 #define EEPROM_DEFAULT_RFE_OPTION 0x04 484 #define EEPROM_DEFAULT_FEATURE_OPTION 0x00 485 #define EEPROM_DEFAULT_BT_OPTION 0x10 486 487 488 #define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 489 490 // PCIe related 491 #define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74 492 #define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75 493 494 495 // 496 // For VHT series TX power by rate table. 497 // VHT TX power by rate off setArray = 498 // Band:-2G&5G = 0 / 1 499 // RF: at most 4*4 = ABCD=0/1/2/3 500 // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 501 // 502 #define TX_PWR_BY_RATE_NUM_BAND 2 503 #define TX_PWR_BY_RATE_NUM_RF 4 504 #define TX_PWR_BY_RATE_NUM_RATE 84 505 506 #define TXPWR_LMT_MAX_RF 4 507 508 //---------------------------------------------------------------------------- 509 // EEPROM/EFUSE data structure definition. 510 //---------------------------------------------------------------------------- 511 #define MAX_RF_PATH_NUM 2 512 #define MAX_CHNL_GROUP 3+9 513 typedef struct _TxPowerInfo{ 514 u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 515 u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 516 u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 517 s8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 518 u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 519 u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 520 u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; 521 u8 TSSI_A[3]; 522 u8 TSSI_B[3]; 523 u8 TSSI_A_5G[3]; //5GL/5GM/5GH 524 u8 TSSI_B_5G[3]; 525 }TxPowerInfo, *PTxPowerInfo; 526 527 528 //For 88E new structure 529 530 /* 531 2.4G: 532 { 533 {1,2}, 534 {3,4,5}, 535 {6,7,8}, 536 {9,10,11}, 537 {12,13}, 538 {14} 539 } 540 541 5G: 542 { 543 {36,38,40}, 544 {44,46,48}, 545 {52,54,56}, 546 {60,62,64}, 547 {100,102,104}, 548 {108,110,112}, 549 {116,118,120}, 550 {124,126,128}, 551 {132,134,136}, 552 {140,142,144}, 553 {149,151,153}, 554 {157,159,161}, 555 {173,175,177}, 556 } 557 */ 558 #define MAX_RF_PATH 4 559 #define RF_PATH_MAX MAX_RF_PATH 560 #define MAX_CHNL_GROUP_24G 6 561 #define MAX_CHNL_GROUP_5G 14 562 563 //It must always set to 4, otherwise read efuse table secquence will be wrong. 564 #define MAX_TX_COUNT 4 565 566 typedef struct _TxPowerInfo24G{ 567 u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 568 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 569 //If only one tx, only BW20 and OFDM are used. 570 s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 571 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 572 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 573 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 574 }TxPowerInfo24G, *PTxPowerInfo24G; 575 576 typedef struct _TxPowerInfo5G{ 577 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 578 //If only one tx, only BW20, OFDM, BW80 and BW160 are used. 579 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 580 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 581 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 582 s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 583 s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 584 }TxPowerInfo5G, *PTxPowerInfo5G; 585 586 587 typedef enum _BT_Ant_NUM{ 588 Ant_x2 = 0, 589 Ant_x1 = 1 590 } BT_Ant_NUM, *PBT_Ant_NUM; 591 592 typedef enum _BT_CoType{ 593 BT_2WIRE = 0, 594 BT_ISSC_3WIRE = 1, 595 BT_ACCEL = 2, 596 BT_CSR_BC4 = 3, 597 BT_CSR_BC8 = 4, 598 BT_RTL8756 = 5, 599 BT_RTL8723A = 6, 600 BT_RTL8821 = 7, 601 BT_RTL8723B = 8, 602 BT_RTL8192E = 9, 603 BT_RTL8814A = 10, 604 BT_RTL8812A = 11, 605 BT_RTL8703B = 12 606 } BT_CoType, *PBT_CoType; 607 608 typedef enum _BT_RadioShared{ 609 BT_Radio_Shared = 0, 610 BT_Radio_Individual = 1, 611 } BT_RadioShared, *PBT_RadioShared; 612 613 614 #endif 615