1 /* 2 * HND Run Time Environment ioctl. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _dngl_ioctl_h_ 25 #define _dngl_ioctl_h_ 26 27 /* ==== Dongle IOCTLs i.e. non-d11 IOCTLs ==== */ 28 29 #ifndef _rte_ioctl_h_ 30 /* ================================================================ */ 31 /* These are the existing ioctls moved from src/include/rte_ioctl.h */ 32 /* ================================================================ */ 33 34 /* RTE IOCTL definitions for generic ether devices */ 35 #define RTEIOCTLSTART 0x8901 36 #define RTEGHWADDR 0x8901 37 #define RTESHWADDR 0x8902 38 #define RTEGMTU 0x8903 39 #define RTEGSTATS 0x8904 40 #define RTEGALLMULTI 0x8905 41 #define RTESALLMULTI 0x8906 42 #define RTEGPROMISC 0x8907 43 #define RTESPROMISC 0x8908 44 #define RTESMULTILIST 0x8909 45 #define RTEGUP 0x890A 46 #define RTEGPERMADDR 0x890B 47 #define RTEDEVPWRSTCHG 0x890C /* Device pwr state change for PCIedev */ 48 #define RTEDEVPMETOGGLE 0x890D /* Toggle PME# to wake up the host */ 49 #define RTEDEVTIMESYNC 0x890E /* Device TimeSync */ 50 #define RTEDEVDSNOTIFY 0x890F /* Bus DS state notification */ 51 #define RTED11DMALPBK_INIT 0x8910 /* D11 DMA loopback init */ 52 #define RTED11DMALPBK_UNINIT 0x8911 /* D11 DMA loopback uninit */ 53 #define RTED11DMALPBK_RUN 0x8912 /* D11 DMA loopback run */ 54 #define RTEDEVTSBUFPOST 0x8913 /* Async interface for tsync buffer post */ 55 #define RTED11DMAHOSTLPBK_RUN 0x8914 /* D11 DMA host memory loopback run */ 56 #define RTEDEVGETTSF 0x8915 /* Get device TSF */ 57 #define RTEDURATIONUNIT 0x8916 /* Duration unit */ 58 #define RTEWRITE_WAR_REGS 0x8917 /* write workaround regs */ 59 #define RTEDEVRMPMK 0x8918 /* Remove PMK */ 60 #define RTEDEVDBGVAL 0x8919 /* Set debug val */ 61 /* Ensure last RTE IOCTL define val is assigned to RTEIOCTLEND */ 62 #define RTEIOCTLEND 0x8919 /* LAST RTE IOCTL value */ 63 64 #define RTE_IOCTL_QUERY 0x00 65 #define RTE_IOCTL_SET 0x01 66 #define RTE_IOCTL_OVL_IDX_MASK 0x1e 67 #define RTE_IOCTL_OVL_RSV 0x20 68 #define RTE_IOCTL_OVL 0x40 69 #define RTE_IOCTL_OVL_IDX_SHIFT 1 70 71 enum hnd_ioctl_cmd { 72 HND_RTE_DNGL_IS_SS = 1, /* true if device connected at super speed */ 73 74 /* PCIEDEV specific wl <--> bus ioctls */ 75 BUS_GET_VAR = 2, 76 BUS_SET_VAR = 3, 77 BUS_FLUSH_RXREORDER_Q = 4, 78 BUS_SET_LTR_STATE = 5, 79 BUS_FLUSH_CHAINED_PKTS = 6, 80 BUS_SET_COPY_COUNT = 7, 81 BUS_UPDATE_FLOW_PKTS_MAX = 8, 82 BUS_UPDATE_EXTRA_TXLFRAGS = 9, 83 BUS_UPDATE_FRWD_RESRV_BUFCNT = 10, 84 BUS_PCIE_CONFIG_ACCESS = 11, 85 BUS_HC_EVENT_MASK_UPDATE = 12, 86 BUS_SET_MAC_WAKE_STATE = 13, 87 BUS_FRWD_PKT_RXCMPLT = 14, 88 BUS_PCIE_LATENCY_ENAB = 15, /* to enable latency feature in pcie */ 89 BUS_GET_MAXITEMS = 16, 90 BUS_SET_BUS_CSO_CAP = 17, /* Update the CSO cap from wl layer to bus layer */ 91 BUS_DUMP_RX_DMA_STALL_RELATED_INFO = 18, 92 BUS_UPDATE_RESVPOOL_STATE = 19 /* Update resvpool state */ 93 }; 94 95 #define SDPCMDEV_SET_MAXTXPKTGLOM 1 96 #define RTE_MEMUSEINFO_VER 0x00 97 98 typedef struct memuse_info { 99 uint16 ver; /* version of this struct */ 100 uint16 len; /* length in bytes of this structure */ 101 uint32 tot; /* Total memory */ 102 uint32 text_len; /* Size of Text segment memory */ 103 uint32 data_len; /* Size of Data segment memory */ 104 uint32 bss_len; /* Size of BSS segment memory */ 105 106 uint32 arena_size; /* Total Heap size */ 107 uint32 arena_free; /* Heap memory available or free */ 108 uint32 inuse_size; /* Heap memory currently in use */ 109 uint32 inuse_hwm; /* High watermark of memory - reclaimed memory */ 110 uint32 inuse_overhead; /* tally of allocated mem_t blocks */ 111 uint32 inuse_total; /* Heap in-use + Heap overhead memory */ 112 uint32 free_lwm; /* Least free size since reclaim */ 113 uint32 mf_count; /* Malloc failure count */ 114 } memuse_info_t; 115 116 /* Different DMA loopback modes */ 117 #define M2M_DMA_LOOPBACK 0 /* PCIE M2M mode */ 118 #define D11_DMA_LOOPBACK 1 /* PCIE M2M and D11 mode without ucode */ 119 #define BMC_DMA_LOOPBACK 2 /* PCIE M2M and D11 mode with ucode */ 120 #define M2M_NON_DMA_LOOPBACK 3 /* Non DMA(indirect) mode */ 121 #define D11_DMA_HOST_MEM_LPBK 4 /* D11 mode */ 122 #define M2M_DMA_WRITE_TO_RAM 6 /* PCIE M2M write to specific memory mode */ 123 #define M2M_DMA_READ_FROM_RAM 7 /* PCIE M2M read from specific memory mode */ 124 #define D11_DMA_WRITE_TO_RAM 8 /* D11 write to specific memory mode */ 125 #define D11_DMA_READ_FROM_RAM 9 /* D11 read from specific memory mode */ 126 127 /* For D11 DMA loopback test */ 128 typedef struct d11_dmalpbk_init_args { 129 uint8 core_num; 130 uint8 lpbk_mode; 131 } d11_dmalpbk_init_args_t; 132 133 typedef struct d11_dmalpbk_args { 134 uint8 *buf; 135 int32 len; 136 void *p; 137 uint8 core_num; 138 uint8 pad[3]; 139 } d11_dmalpbk_args_t; 140 141 typedef enum wl_config_var { 142 WL_VAR_TX_PKTFETCH_INDUCE = 1, 143 WL_VAR_LAST 144 } wl_config_var_t; 145 146 typedef struct wl_config_buf { 147 wl_config_var_t var; 148 uint32 val; 149 } wl_config_buf_t; 150 151 /* ================================================================ */ 152 /* These are the existing ioctls moved from src/include/rte_ioctl.h */ 153 /* ================================================================ */ 154 #endif /* _rte_ioctl_h_ */ 155 156 /* MPU test iovar version */ 157 #define MPU_TEST_STRUCT_VER 0 158 159 /* MPU test OP */ 160 #define MPU_TEST_OP_READ 0 161 #define MPU_TEST_OP_WRITE 1 162 #define MPU_TEST_OP_EXECUTE 2 163 164 /* Debug iovar for MPU testing */ 165 typedef struct mpu_test_args { 166 /* version control */ 167 uint16 ver; 168 uint16 len; /* the length of this structure */ 169 /* data */ 170 uint32 addr; 171 uint8 op; /* see MPU_TEST_OP_XXXX */ 172 uint8 rsvd; 173 uint16 size; /* valid for read/write */ 174 uint8 val[]; 175 } mpu_test_args_t; 176 177 #endif /* _dngl_ioctl_h_ */ 178