1 /* 2 * HND OOBR interface header 3 * 4 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: hndoobr.h 772387 2018-07-17 00:58:05Z $ 30 */ 31 32 #ifndef _hndoobr_h_ 33 #define _hndoobr_h_ 34 35 #include <typedefs.h> 36 #include <siutils.h> 37 38 /* for 'srcpidx' of hnd_oobr_get_intr_config() */ 39 #define HND_CORE_MAIN_INTR 0 40 #define HND_CORE_ALT_INTR 1 41 42 uint32 hnd_oobr_get_intstatus(si_t *sih); 43 int hnd_oobr_get_intr_config(si_t *sih, uint srccidx, uint srcpidx, uint dstcidx, uint *dstpidx); 44 int hnd_oobr_set_intr_src(si_t *sih, uint dstcidx, uint dstpidx, uint intrnum); 45 void hnd_oobr_init(si_t *sih); 46 47 #define OOBR_INVALID_PORT 0xFFu 48 49 /* per core source/dest sel reg */ 50 #define OOBR_INTR_PER_CONFREG 4u /* 4 interrupts per configure reg */ 51 #define OOBR_INTR_NUM_MASK 0x7Fu 52 #define OOBR_INTR_EN 0x80u 53 /* per core config reg */ 54 #define OOBR_CORECNF_OUTPUT_MASK 0x0000FF00u 55 #define OOBR_CORECNF_OUTPUT_SHIFT 8u 56 #define OOBR_CORECNF_INPUT_MASK 0x00FF0000u 57 #define OOBR_CORECNF_INPUT_SHIFT 16u 58 59 typedef volatile struct hndoobr_percore_reg { 60 uint32 sourcesel[OOBR_INTR_PER_CONFREG]; /* 0x00 - 0x0c */ 61 uint32 destsel[OOBR_INTR_PER_CONFREG]; /* 0x10 - 0x1c */ 62 uint32 reserved[6]; 63 uint32 config; /* 0x38 */ 64 uint32 reserved1[17]; /* 0x3c to 0x7c */ 65 } hndoobr_percore_reg_t; 66 67 /* capability reg */ 68 #define OOBR_CAP_CORECNT_MASK 0x1fu 69 typedef volatile struct hndoobr_reg { 70 uint32 capability; /* 0x00 */ 71 uint32 reserved[3]; 72 uint32 intstatus[4]; /* 0x10 - 0x1c */ 73 uint32 reserved1[56]; /* 0x20 - 0xfc */ 74 hndoobr_percore_reg_t percore_reg[1]; /* 0x100 */ 75 } hndoobr_reg_t; 76 77 #endif /* _hndoobr_h_ */ 78