1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __RTW_SEC_H_ 6*4882a593Smuzhiyun #define __RTW_SEC_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define RTW_SEC_CMD_REG 0x670 9*4882a593Smuzhiyun #define RTW_SEC_WRITE_REG 0x674 10*4882a593Smuzhiyun #define RTW_SEC_READ_REG 0x678 11*4882a593Smuzhiyun #define RTW_SEC_CONFIG 0x680 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define RTW_SEC_CAM_ENTRY_SHIFT 3 14*4882a593Smuzhiyun #define RTW_SEC_DEFAULT_KEY_NUM 4 15*4882a593Smuzhiyun #define RTW_SEC_CMD_WRITE_ENABLE BIT(16) 16*4882a593Smuzhiyun #define RTW_SEC_CMD_CLEAR BIT(30) 17*4882a593Smuzhiyun #define RTW_SEC_CMD_POLLING BIT(31) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RTW_SEC_TX_UNI_USE_DK BIT(0) 20*4882a593Smuzhiyun #define RTW_SEC_RX_UNI_USE_DK BIT(1) 21*4882a593Smuzhiyun #define RTW_SEC_TX_DEC_EN BIT(2) 22*4882a593Smuzhiyun #define RTW_SEC_RX_DEC_EN BIT(3) 23*4882a593Smuzhiyun #define RTW_SEC_TX_BC_USE_DK BIT(6) 24*4882a593Smuzhiyun #define RTW_SEC_RX_BC_USE_DK BIT(7) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define RTW_SEC_ENGINE_EN BIT(9) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun int rtw_sec_get_free_cam(struct rtw_sec_desc *sec); 29*4882a593Smuzhiyun void rtw_sec_write_cam(struct rtw_dev *rtwdev, 30*4882a593Smuzhiyun struct rtw_sec_desc *sec, 31*4882a593Smuzhiyun struct ieee80211_sta *sta, 32*4882a593Smuzhiyun struct ieee80211_key_conf *key, 33*4882a593Smuzhiyun u8 hw_key_type, u8 hw_key_idx); 34*4882a593Smuzhiyun void rtw_sec_clear_cam(struct rtw_dev *rtwdev, 35*4882a593Smuzhiyun struct rtw_sec_desc *sec, 36*4882a593Smuzhiyun u8 hw_key_idx); 37*4882a593Smuzhiyun u8 rtw_sec_cam_pg_backup(struct rtw_dev *rtwdev, u8 *used_cam); 38*4882a593Smuzhiyun void rtw_sec_enable_sec_engine(struct rtw_dev *rtwdev); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif 41