1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include "main.h"
6*4882a593Smuzhiyun #include "sec.h"
7*4882a593Smuzhiyun #include "reg.h"
8*4882a593Smuzhiyun
rtw_sec_get_free_cam(struct rtw_sec_desc * sec)9*4882a593Smuzhiyun int rtw_sec_get_free_cam(struct rtw_sec_desc *sec)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun /* if default key search is enabled, the first 4 cam entries
12*4882a593Smuzhiyun * are used to direct map to group key with its key->key_idx, so
13*4882a593Smuzhiyun * driver should use cam entries after 4 to install pairwise key
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun if (sec->default_key_search)
16*4882a593Smuzhiyun return find_next_zero_bit(sec->cam_map, RTW_MAX_SEC_CAM_NUM,
17*4882a593Smuzhiyun RTW_SEC_DEFAULT_KEY_NUM);
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun return find_first_zero_bit(sec->cam_map, RTW_MAX_SEC_CAM_NUM);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
rtw_sec_write_cam(struct rtw_dev * rtwdev,struct rtw_sec_desc * sec,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,u8 hw_key_type,u8 hw_key_idx)22*4882a593Smuzhiyun void rtw_sec_write_cam(struct rtw_dev *rtwdev,
23*4882a593Smuzhiyun struct rtw_sec_desc *sec,
24*4882a593Smuzhiyun struct ieee80211_sta *sta,
25*4882a593Smuzhiyun struct ieee80211_key_conf *key,
26*4882a593Smuzhiyun u8 hw_key_type, u8 hw_key_idx)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun struct rtw_cam_entry *cam = &sec->cam_table[hw_key_idx];
29*4882a593Smuzhiyun u32 write_cmd;
30*4882a593Smuzhiyun u32 command;
31*4882a593Smuzhiyun u32 content;
32*4882a593Smuzhiyun u32 addr;
33*4882a593Smuzhiyun int i, j;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun set_bit(hw_key_idx, sec->cam_map);
36*4882a593Smuzhiyun cam->valid = true;
37*4882a593Smuzhiyun cam->group = !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE);
38*4882a593Smuzhiyun cam->hw_key_type = hw_key_type;
39*4882a593Smuzhiyun cam->key = key;
40*4882a593Smuzhiyun if (sta)
41*4882a593Smuzhiyun ether_addr_copy(cam->addr, sta->addr);
42*4882a593Smuzhiyun else
43*4882a593Smuzhiyun eth_broadcast_addr(cam->addr);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun write_cmd = RTW_SEC_CMD_WRITE_ENABLE | RTW_SEC_CMD_POLLING;
46*4882a593Smuzhiyun addr = hw_key_idx << RTW_SEC_CAM_ENTRY_SHIFT;
47*4882a593Smuzhiyun for (i = 7; i >= 0; i--) {
48*4882a593Smuzhiyun switch (i) {
49*4882a593Smuzhiyun case 0:
50*4882a593Smuzhiyun content = ((key->keyidx & 0x3)) |
51*4882a593Smuzhiyun ((hw_key_type & 0x7) << 2) |
52*4882a593Smuzhiyun (cam->group << 6) |
53*4882a593Smuzhiyun (cam->valid << 15) |
54*4882a593Smuzhiyun (cam->addr[0] << 16) |
55*4882a593Smuzhiyun (cam->addr[1] << 24);
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun case 1:
58*4882a593Smuzhiyun content = (cam->addr[2]) |
59*4882a593Smuzhiyun (cam->addr[3] << 8) |
60*4882a593Smuzhiyun (cam->addr[4] << 16) |
61*4882a593Smuzhiyun (cam->addr[5] << 24);
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun case 6:
64*4882a593Smuzhiyun case 7:
65*4882a593Smuzhiyun content = 0;
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun default:
68*4882a593Smuzhiyun j = (i - 2) << 2;
69*4882a593Smuzhiyun content = (key->key[j]) |
70*4882a593Smuzhiyun (key->key[j + 1] << 8) |
71*4882a593Smuzhiyun (key->key[j + 2] << 16) |
72*4882a593Smuzhiyun (key->key[j + 3] << 24);
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun command = write_cmd | (addr + i);
77*4882a593Smuzhiyun rtw_write32(rtwdev, RTW_SEC_WRITE_REG, content);
78*4882a593Smuzhiyun rtw_write32(rtwdev, RTW_SEC_CMD_REG, command);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
rtw_sec_clear_cam(struct rtw_dev * rtwdev,struct rtw_sec_desc * sec,u8 hw_key_idx)82*4882a593Smuzhiyun void rtw_sec_clear_cam(struct rtw_dev *rtwdev,
83*4882a593Smuzhiyun struct rtw_sec_desc *sec,
84*4882a593Smuzhiyun u8 hw_key_idx)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct rtw_cam_entry *cam = &sec->cam_table[hw_key_idx];
87*4882a593Smuzhiyun u32 write_cmd;
88*4882a593Smuzhiyun u32 command;
89*4882a593Smuzhiyun u32 addr;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun clear_bit(hw_key_idx, sec->cam_map);
92*4882a593Smuzhiyun cam->valid = false;
93*4882a593Smuzhiyun cam->key = NULL;
94*4882a593Smuzhiyun eth_zero_addr(cam->addr);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun write_cmd = RTW_SEC_CMD_WRITE_ENABLE | RTW_SEC_CMD_POLLING;
97*4882a593Smuzhiyun addr = hw_key_idx << RTW_SEC_CAM_ENTRY_SHIFT;
98*4882a593Smuzhiyun command = write_cmd | addr;
99*4882a593Smuzhiyun rtw_write32(rtwdev, RTW_SEC_WRITE_REG, 0);
100*4882a593Smuzhiyun rtw_write32(rtwdev, RTW_SEC_CMD_REG, command);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
rtw_sec_cam_pg_backup(struct rtw_dev * rtwdev,u8 * used_cam)103*4882a593Smuzhiyun u8 rtw_sec_cam_pg_backup(struct rtw_dev *rtwdev, u8 *used_cam)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct rtw_sec_desc *sec = &rtwdev->sec;
106*4882a593Smuzhiyun u8 offset = 0;
107*4882a593Smuzhiyun u8 count, n;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (!used_cam)
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun for (count = 0; count < MAX_PG_CAM_BACKUP_NUM; count++) {
113*4882a593Smuzhiyun n = find_next_bit(sec->cam_map, RTW_MAX_SEC_CAM_NUM, offset);
114*4882a593Smuzhiyun if (n == RTW_MAX_SEC_CAM_NUM)
115*4882a593Smuzhiyun break;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun used_cam[count] = n;
118*4882a593Smuzhiyun offset = n + 1;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return count;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
rtw_sec_enable_sec_engine(struct rtw_dev * rtwdev)124*4882a593Smuzhiyun void rtw_sec_enable_sec_engine(struct rtw_dev *rtwdev)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct rtw_sec_desc *sec = &rtwdev->sec;
127*4882a593Smuzhiyun u16 ctrl_reg;
128*4882a593Smuzhiyun u16 sec_config;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* default use default key search for now */
131*4882a593Smuzhiyun sec->default_key_search = true;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ctrl_reg = rtw_read16(rtwdev, REG_CR);
134*4882a593Smuzhiyun ctrl_reg |= RTW_SEC_ENGINE_EN;
135*4882a593Smuzhiyun rtw_write16(rtwdev, REG_CR, ctrl_reg);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun sec_config = rtw_read16(rtwdev, RTW_SEC_CONFIG);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun sec_config |= RTW_SEC_TX_DEC_EN | RTW_SEC_RX_DEC_EN;
140*4882a593Smuzhiyun if (sec->default_key_search)
141*4882a593Smuzhiyun sec_config |= RTW_SEC_TX_UNI_USE_DK | RTW_SEC_RX_UNI_USE_DK |
142*4882a593Smuzhiyun RTW_SEC_TX_BC_USE_DK | RTW_SEC_RX_BC_USE_DK;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun rtw_write16(rtwdev, RTW_SEC_CONFIG, sec_config);
145*4882a593Smuzhiyun }
146