1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __RTW_RX_H_ 6*4882a593Smuzhiyun #define __RTW_RX_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum rtw_rx_desc_enc { 9*4882a593Smuzhiyun RX_DESC_ENC_NONE = 0, 10*4882a593Smuzhiyun RX_DESC_ENC_WEP40 = 1, 11*4882a593Smuzhiyun RX_DESC_ENC_TKIP_WO_MIC = 2, 12*4882a593Smuzhiyun RX_DESC_ENC_TKIP_MIC = 3, 13*4882a593Smuzhiyun RX_DESC_ENC_AES = 4, 14*4882a593Smuzhiyun RX_DESC_ENC_WEP104 = 5, 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define GET_RX_DESC_PHYST(rxdesc) \ 18*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(26)) 19*4882a593Smuzhiyun #define GET_RX_DESC_ICV_ERR(rxdesc) \ 20*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(15)) 21*4882a593Smuzhiyun #define GET_RX_DESC_CRC32(rxdesc) \ 22*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(14)) 23*4882a593Smuzhiyun #define GET_RX_DESC_SWDEC(rxdesc) \ 24*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(27)) 25*4882a593Smuzhiyun #define GET_RX_DESC_C2H(rxdesc) \ 26*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x02), BIT(28)) 27*4882a593Smuzhiyun #define GET_RX_DESC_PKT_LEN(rxdesc) \ 28*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(13, 0)) 29*4882a593Smuzhiyun #define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \ 30*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(19, 16)) 31*4882a593Smuzhiyun #define GET_RX_DESC_SHIFT(rxdesc) \ 32*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(25, 24)) 33*4882a593Smuzhiyun #define GET_RX_DESC_ENC_TYPE(rxdesc) \ 34*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(22, 20)) 35*4882a593Smuzhiyun #define GET_RX_DESC_RX_RATE(rxdesc) \ 36*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x03), GENMASK(6, 0)) 37*4882a593Smuzhiyun #define GET_RX_DESC_MACID(rxdesc) \ 38*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x01), GENMASK(6, 0)) 39*4882a593Smuzhiyun #define GET_RX_DESC_PPDU_CNT(rxdesc) \ 40*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29)) 41*4882a593Smuzhiyun #define GET_RX_DESC_TSFL(rxdesc) \ 42*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0)) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 45*4882a593Smuzhiyun struct sk_buff *skb); 46*4882a593Smuzhiyun void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev, 47*4882a593Smuzhiyun struct rtw_rx_pkt_stat *pkt_stat, 48*4882a593Smuzhiyun struct ieee80211_hdr *hdr, 49*4882a593Smuzhiyun struct ieee80211_rx_status *rx_status, 50*4882a593Smuzhiyun u8 *phy_status); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53