1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include "main.h"
6*4882a593Smuzhiyun #include "regd.h"
7*4882a593Smuzhiyun #include "fw.h"
8*4882a593Smuzhiyun #include "ps.h"
9*4882a593Smuzhiyun #include "sec.h"
10*4882a593Smuzhiyun #include "mac.h"
11*4882a593Smuzhiyun #include "coex.h"
12*4882a593Smuzhiyun #include "phy.h"
13*4882a593Smuzhiyun #include "reg.h"
14*4882a593Smuzhiyun #include "efuse.h"
15*4882a593Smuzhiyun #include "tx.h"
16*4882a593Smuzhiyun #include "debug.h"
17*4882a593Smuzhiyun #include "bf.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun unsigned int rtw_fw_lps_deep_mode;
20*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_fw_lps_deep_mode);
21*4882a593Smuzhiyun bool rtw_bf_support = true;
22*4882a593Smuzhiyun unsigned int rtw_debug_mask;
23*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_debug_mask);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun module_param_named(lps_deep_mode, rtw_fw_lps_deep_mode, uint, 0644);
26*4882a593Smuzhiyun module_param_named(support_bf, rtw_bf_support, bool, 0644);
27*4882a593Smuzhiyun module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun MODULE_PARM_DESC(lps_deep_mode, "Deeper PS mode. If 0, deep PS is disabled");
30*4882a593Smuzhiyun MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
31*4882a593Smuzhiyun MODULE_PARM_DESC(debug_mask, "Debugging mask");
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static struct ieee80211_channel rtw_channeltable_2g[] = {
34*4882a593Smuzhiyun {.center_freq = 2412, .hw_value = 1,},
35*4882a593Smuzhiyun {.center_freq = 2417, .hw_value = 2,},
36*4882a593Smuzhiyun {.center_freq = 2422, .hw_value = 3,},
37*4882a593Smuzhiyun {.center_freq = 2427, .hw_value = 4,},
38*4882a593Smuzhiyun {.center_freq = 2432, .hw_value = 5,},
39*4882a593Smuzhiyun {.center_freq = 2437, .hw_value = 6,},
40*4882a593Smuzhiyun {.center_freq = 2442, .hw_value = 7,},
41*4882a593Smuzhiyun {.center_freq = 2447, .hw_value = 8,},
42*4882a593Smuzhiyun {.center_freq = 2452, .hw_value = 9,},
43*4882a593Smuzhiyun {.center_freq = 2457, .hw_value = 10,},
44*4882a593Smuzhiyun {.center_freq = 2462, .hw_value = 11,},
45*4882a593Smuzhiyun {.center_freq = 2467, .hw_value = 12,},
46*4882a593Smuzhiyun {.center_freq = 2472, .hw_value = 13,},
47*4882a593Smuzhiyun {.center_freq = 2484, .hw_value = 14,},
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static struct ieee80211_channel rtw_channeltable_5g[] = {
51*4882a593Smuzhiyun {.center_freq = 5180, .hw_value = 36,},
52*4882a593Smuzhiyun {.center_freq = 5200, .hw_value = 40,},
53*4882a593Smuzhiyun {.center_freq = 5220, .hw_value = 44,},
54*4882a593Smuzhiyun {.center_freq = 5240, .hw_value = 48,},
55*4882a593Smuzhiyun {.center_freq = 5260, .hw_value = 52,},
56*4882a593Smuzhiyun {.center_freq = 5280, .hw_value = 56,},
57*4882a593Smuzhiyun {.center_freq = 5300, .hw_value = 60,},
58*4882a593Smuzhiyun {.center_freq = 5320, .hw_value = 64,},
59*4882a593Smuzhiyun {.center_freq = 5500, .hw_value = 100,},
60*4882a593Smuzhiyun {.center_freq = 5520, .hw_value = 104,},
61*4882a593Smuzhiyun {.center_freq = 5540, .hw_value = 108,},
62*4882a593Smuzhiyun {.center_freq = 5560, .hw_value = 112,},
63*4882a593Smuzhiyun {.center_freq = 5580, .hw_value = 116,},
64*4882a593Smuzhiyun {.center_freq = 5600, .hw_value = 120,},
65*4882a593Smuzhiyun {.center_freq = 5620, .hw_value = 124,},
66*4882a593Smuzhiyun {.center_freq = 5640, .hw_value = 128,},
67*4882a593Smuzhiyun {.center_freq = 5660, .hw_value = 132,},
68*4882a593Smuzhiyun {.center_freq = 5680, .hw_value = 136,},
69*4882a593Smuzhiyun {.center_freq = 5700, .hw_value = 140,},
70*4882a593Smuzhiyun {.center_freq = 5745, .hw_value = 149,},
71*4882a593Smuzhiyun {.center_freq = 5765, .hw_value = 153,},
72*4882a593Smuzhiyun {.center_freq = 5785, .hw_value = 157,},
73*4882a593Smuzhiyun {.center_freq = 5805, .hw_value = 161,},
74*4882a593Smuzhiyun {.center_freq = 5825, .hw_value = 165,
75*4882a593Smuzhiyun .flags = IEEE80211_CHAN_NO_HT40MINUS},
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static struct ieee80211_rate rtw_ratetable[] = {
79*4882a593Smuzhiyun {.bitrate = 10, .hw_value = 0x00,},
80*4882a593Smuzhiyun {.bitrate = 20, .hw_value = 0x01,},
81*4882a593Smuzhiyun {.bitrate = 55, .hw_value = 0x02,},
82*4882a593Smuzhiyun {.bitrate = 110, .hw_value = 0x03,},
83*4882a593Smuzhiyun {.bitrate = 60, .hw_value = 0x04,},
84*4882a593Smuzhiyun {.bitrate = 90, .hw_value = 0x05,},
85*4882a593Smuzhiyun {.bitrate = 120, .hw_value = 0x06,},
86*4882a593Smuzhiyun {.bitrate = 180, .hw_value = 0x07,},
87*4882a593Smuzhiyun {.bitrate = 240, .hw_value = 0x08,},
88*4882a593Smuzhiyun {.bitrate = 360, .hw_value = 0x09,},
89*4882a593Smuzhiyun {.bitrate = 480, .hw_value = 0x0a,},
90*4882a593Smuzhiyun {.bitrate = 540, .hw_value = 0x0b,},
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
rtw_desc_to_bitrate(u8 desc_rate)93*4882a593Smuzhiyun u16 rtw_desc_to_bitrate(u8 desc_rate)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct ieee80211_rate rate;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun rate = rtw_ratetable[desc_rate];
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return rate.bitrate;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static struct ieee80211_supported_band rtw_band_2ghz = {
106*4882a593Smuzhiyun .band = NL80211_BAND_2GHZ,
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun .channels = rtw_channeltable_2g,
109*4882a593Smuzhiyun .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun .bitrates = rtw_ratetable,
112*4882a593Smuzhiyun .n_bitrates = ARRAY_SIZE(rtw_ratetable),
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun .ht_cap = {0},
115*4882a593Smuzhiyun .vht_cap = {0},
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct ieee80211_supported_band rtw_band_5ghz = {
119*4882a593Smuzhiyun .band = NL80211_BAND_5GHZ,
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun .channels = rtw_channeltable_5g,
122*4882a593Smuzhiyun .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* 5G has no CCK rates */
125*4882a593Smuzhiyun .bitrates = rtw_ratetable + 4,
126*4882a593Smuzhiyun .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun .ht_cap = {0},
129*4882a593Smuzhiyun .vht_cap = {0},
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun struct rtw_watch_dog_iter_data {
133*4882a593Smuzhiyun struct rtw_dev *rtwdev;
134*4882a593Smuzhiyun struct rtw_vif *rtwvif;
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
rtw_dynamic_csi_rate(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif)137*4882a593Smuzhiyun static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct rtw_bf_info *bf_info = &rtwdev->bf_info;
140*4882a593Smuzhiyun u8 fix_rate_enable = 0;
141*4882a593Smuzhiyun u8 new_csi_rate_idx;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (rtwvif->bfee.role != RTW_BFEE_SU &&
144*4882a593Smuzhiyun rtwvif->bfee.role != RTW_BFEE_MU)
145*4882a593Smuzhiyun return;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
148*4882a593Smuzhiyun bf_info->cur_csi_rpt_rate,
149*4882a593Smuzhiyun fix_rate_enable, &new_csi_rate_idx);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
152*4882a593Smuzhiyun bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
rtw_vif_watch_dog_iter(void * data,u8 * mac,struct ieee80211_vif * vif)155*4882a593Smuzhiyun static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
156*4882a593Smuzhiyun struct ieee80211_vif *vif)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct rtw_watch_dog_iter_data *iter_data = data;
159*4882a593Smuzhiyun struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (vif->type == NL80211_IFTYPE_STATION)
162*4882a593Smuzhiyun if (vif->bss_conf.assoc)
163*4882a593Smuzhiyun iter_data->rtwvif = rtwvif;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun rtwvif->stats.tx_unicast = 0;
168*4882a593Smuzhiyun rtwvif->stats.rx_unicast = 0;
169*4882a593Smuzhiyun rtwvif->stats.tx_cnt = 0;
170*4882a593Smuzhiyun rtwvif->stats.rx_cnt = 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* process TX/RX statistics periodically for hardware,
174*4882a593Smuzhiyun * the information helps hardware to enhance performance
175*4882a593Smuzhiyun */
rtw_watch_dog_work(struct work_struct * work)176*4882a593Smuzhiyun static void rtw_watch_dog_work(struct work_struct *work)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
179*4882a593Smuzhiyun watch_dog_work.work);
180*4882a593Smuzhiyun struct rtw_traffic_stats *stats = &rtwdev->stats;
181*4882a593Smuzhiyun struct rtw_watch_dog_iter_data data = {};
182*4882a593Smuzhiyun bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
183*4882a593Smuzhiyun bool ps_active;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun mutex_lock(&rtwdev->mutex);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
188*4882a593Smuzhiyun goto unlock;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
191*4882a593Smuzhiyun RTW_WATCH_DOG_DELAY_TIME);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
194*4882a593Smuzhiyun set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
195*4882a593Smuzhiyun else
196*4882a593Smuzhiyun clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
199*4882a593Smuzhiyun rtw_coex_wl_status_change_notify(rtwdev);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
202*4882a593Smuzhiyun stats->rx_cnt > RTW_LPS_THRESHOLD)
203*4882a593Smuzhiyun ps_active = true;
204*4882a593Smuzhiyun else
205*4882a593Smuzhiyun ps_active = false;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun ewma_tp_add(&stats->tx_ewma_tp,
208*4882a593Smuzhiyun (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
209*4882a593Smuzhiyun ewma_tp_add(&stats->rx_ewma_tp,
210*4882a593Smuzhiyun (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
211*4882a593Smuzhiyun stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
212*4882a593Smuzhiyun stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* reset tx/rx statictics */
215*4882a593Smuzhiyun stats->tx_unicast = 0;
216*4882a593Smuzhiyun stats->rx_unicast = 0;
217*4882a593Smuzhiyun stats->tx_cnt = 0;
218*4882a593Smuzhiyun stats->rx_cnt = 0;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
221*4882a593Smuzhiyun goto unlock;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* make sure BB/RF is working for dynamic mech */
224*4882a593Smuzhiyun rtw_leave_lps(rtwdev);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun rtw_phy_dynamic_mechanism(rtwdev);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun data.rtwdev = rtwdev;
229*4882a593Smuzhiyun /* use atomic version to avoid taking local->iflist_mtx mutex */
230*4882a593Smuzhiyun rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* fw supports only one station associated to enter lps, if there are
233*4882a593Smuzhiyun * more than two stations associated to the AP, then we can not enter
234*4882a593Smuzhiyun * lps, because fw does not handle the overlapped beacon interval
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * mac80211 should iterate vifs and determine if driver can enter
237*4882a593Smuzhiyun * ps by passing IEEE80211_CONF_PS to us, all we need to do is to
238*4882a593Smuzhiyun * get that vif and check if device is having traffic more than the
239*4882a593Smuzhiyun * threshold.
240*4882a593Smuzhiyun */
241*4882a593Smuzhiyun if (rtwdev->ps_enabled && data.rtwvif && !ps_active)
242*4882a593Smuzhiyun rtw_enter_lps(rtwdev, data.rtwvif->port);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun rtwdev->watch_dog_cnt++;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun unlock:
247*4882a593Smuzhiyun mutex_unlock(&rtwdev->mutex);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
rtw_c2h_work(struct work_struct * work)250*4882a593Smuzhiyun static void rtw_c2h_work(struct work_struct *work)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
253*4882a593Smuzhiyun struct sk_buff *skb, *tmp;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
256*4882a593Smuzhiyun skb_unlink(skb, &rtwdev->c2h_queue);
257*4882a593Smuzhiyun rtw_fw_c2h_cmd_handle(rtwdev, skb);
258*4882a593Smuzhiyun dev_kfree_skb_any(skb);
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
rtw_acquire_macid(struct rtw_dev * rtwdev)262*4882a593Smuzhiyun static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun unsigned long mac_id;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
267*4882a593Smuzhiyun if (mac_id < RTW_MAX_MAC_ID_NUM)
268*4882a593Smuzhiyun set_bit(mac_id, rtwdev->mac_id_map);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return mac_id;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
rtw_sta_add(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,struct ieee80211_vif * vif)273*4882a593Smuzhiyun int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
274*4882a593Smuzhiyun struct ieee80211_vif *vif)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
277*4882a593Smuzhiyun int i;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun si->mac_id = rtw_acquire_macid(rtwdev);
280*4882a593Smuzhiyun if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
281*4882a593Smuzhiyun return -ENOSPC;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun si->sta = sta;
284*4882a593Smuzhiyun si->vif = vif;
285*4882a593Smuzhiyun si->init_ra_lv = 1;
286*4882a593Smuzhiyun ewma_rssi_init(&si->avg_rssi);
287*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
288*4882a593Smuzhiyun rtw_txq_init(rtwdev, sta->txq[i]);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun rtw_update_sta_info(rtwdev, si);
291*4882a593Smuzhiyun rtw_fw_media_status_report(rtwdev, si->mac_id, true);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun rtwdev->sta_cnt++;
294*4882a593Smuzhiyun rtw_info(rtwdev, "sta %pM joined with macid %d\n",
295*4882a593Smuzhiyun sta->addr, si->mac_id);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
rtw_sta_remove(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,bool fw_exist)300*4882a593Smuzhiyun void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
301*4882a593Smuzhiyun bool fw_exist)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
304*4882a593Smuzhiyun int i;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun rtw_release_macid(rtwdev, si->mac_id);
307*4882a593Smuzhiyun if (fw_exist)
308*4882a593Smuzhiyun rtw_fw_media_status_report(rtwdev, si->mac_id, false);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
311*4882a593Smuzhiyun rtw_txq_cleanup(rtwdev, sta->txq[i]);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun kfree(si->mask);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun rtwdev->sta_cnt--;
316*4882a593Smuzhiyun rtw_info(rtwdev, "sta %pM with macid %d left\n",
317*4882a593Smuzhiyun sta->addr, si->mac_id);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
rtw_fw_dump_crash_log(struct rtw_dev * rtwdev)320*4882a593Smuzhiyun static bool rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun u32 size = rtwdev->chip->fw_rxff_size;
323*4882a593Smuzhiyun u32 *buf;
324*4882a593Smuzhiyun u8 seq;
325*4882a593Smuzhiyun bool ret = true;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun buf = vmalloc(size);
328*4882a593Smuzhiyun if (!buf)
329*4882a593Smuzhiyun goto exit;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
332*4882a593Smuzhiyun rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
333*4882a593Smuzhiyun goto free_buf;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (GET_FW_DUMP_LEN(buf) == 0) {
337*4882a593Smuzhiyun rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
338*4882a593Smuzhiyun goto free_buf;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun seq = GET_FW_DUMP_SEQ(buf);
342*4882a593Smuzhiyun if (seq > 0 && seq != (rtwdev->fw.prev_dump_seq + 1)) {
343*4882a593Smuzhiyun rtw_dbg(rtwdev, RTW_DBG_FW,
344*4882a593Smuzhiyun "fw crash dump's seq is wrong: %d\n", seq);
345*4882a593Smuzhiyun goto free_buf;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun if (seq == 0 &&
348*4882a593Smuzhiyun (GET_FW_DUMP_TLV_TYPE(buf) != FW_CD_TYPE ||
349*4882a593Smuzhiyun GET_FW_DUMP_TLV_LEN(buf) != FW_CD_LEN ||
350*4882a593Smuzhiyun GET_FW_DUMP_TLV_VAL(buf) != FW_CD_VAL)) {
351*4882a593Smuzhiyun rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's tlv is wrong\n");
352*4882a593Smuzhiyun goto free_buf;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun print_hex_dump_bytes("rtw88 fw dump: ", DUMP_PREFIX_OFFSET, buf, size);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun if (GET_FW_DUMP_MORE(buf) == 1) {
358*4882a593Smuzhiyun rtwdev->fw.prev_dump_seq = seq;
359*4882a593Smuzhiyun ret = false;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun free_buf:
363*4882a593Smuzhiyun vfree(buf);
364*4882a593Smuzhiyun exit:
365*4882a593Smuzhiyun rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
rtw_vif_assoc_changed(struct rtw_vif * rtwvif,struct ieee80211_bss_conf * conf)370*4882a593Smuzhiyun void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
371*4882a593Smuzhiyun struct ieee80211_bss_conf *conf)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun if (conf && conf->assoc) {
374*4882a593Smuzhiyun rtwvif->aid = conf->aid;
375*4882a593Smuzhiyun rtwvif->net_type = RTW_NET_MGD_LINKED;
376*4882a593Smuzhiyun } else {
377*4882a593Smuzhiyun rtwvif->aid = 0;
378*4882a593Smuzhiyun rtwvif->net_type = RTW_NET_NO_LINK;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
rtw_reset_key_iter(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)382*4882a593Smuzhiyun static void rtw_reset_key_iter(struct ieee80211_hw *hw,
383*4882a593Smuzhiyun struct ieee80211_vif *vif,
384*4882a593Smuzhiyun struct ieee80211_sta *sta,
385*4882a593Smuzhiyun struct ieee80211_key_conf *key,
386*4882a593Smuzhiyun void *data)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun struct rtw_dev *rtwdev = (struct rtw_dev *)data;
389*4882a593Smuzhiyun struct rtw_sec_desc *sec = &rtwdev->sec;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
rtw_reset_sta_iter(void * data,struct ieee80211_sta * sta)394*4882a593Smuzhiyun static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun struct rtw_dev *rtwdev = (struct rtw_dev *)data;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun if (rtwdev->sta_cnt == 0) {
399*4882a593Smuzhiyun rtw_warn(rtwdev, "sta count before reset should not be 0\n");
400*4882a593Smuzhiyun return;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun rtw_sta_remove(rtwdev, sta, false);
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
rtw_reset_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)405*4882a593Smuzhiyun static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun struct rtw_dev *rtwdev = (struct rtw_dev *)data;
408*4882a593Smuzhiyun struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun rtw_bf_disassoc(rtwdev, vif, NULL);
411*4882a593Smuzhiyun rtw_vif_assoc_changed(rtwvif, NULL);
412*4882a593Smuzhiyun rtw_txq_cleanup(rtwdev, vif->txq);
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
rtw_fw_recovery(struct rtw_dev * rtwdev)415*4882a593Smuzhiyun void rtw_fw_recovery(struct rtw_dev *rtwdev)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
418*4882a593Smuzhiyun ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
rtw_fw_recovery_work(struct work_struct * work)421*4882a593Smuzhiyun static void rtw_fw_recovery_work(struct work_struct *work)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
424*4882a593Smuzhiyun fw_recovery_work);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /* rtw_fw_dump_crash_log() returns false indicates that there are
427*4882a593Smuzhiyun * still more log to dump. Driver set 0x1cf[7:0] = 0x1 to tell firmware
428*4882a593Smuzhiyun * to dump the remaining part of the log, and firmware will trigger an
429*4882a593Smuzhiyun * IMR_C2HCMD interrupt to inform driver the log is ready.
430*4882a593Smuzhiyun */
431*4882a593Smuzhiyun if (!rtw_fw_dump_crash_log(rtwdev)) {
432*4882a593Smuzhiyun rtw_write8(rtwdev, REG_HRCV_MSG, 1);
433*4882a593Smuzhiyun return;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun rtwdev->fw.prev_dump_seq = 0;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun WARN(1, "firmware crash, start reset and recover\n");
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun mutex_lock(&rtwdev->mutex);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
442*4882a593Smuzhiyun rcu_read_lock();
443*4882a593Smuzhiyun rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
444*4882a593Smuzhiyun rcu_read_unlock();
445*4882a593Smuzhiyun rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
446*4882a593Smuzhiyun rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
447*4882a593Smuzhiyun rtw_enter_ips(rtwdev);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun mutex_unlock(&rtwdev->mutex);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun ieee80211_restart_hw(rtwdev->hw);
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun struct rtw_txq_ba_iter_data {
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun
rtw_txq_ba_iter(void * data,struct ieee80211_sta * sta)457*4882a593Smuzhiyun static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
460*4882a593Smuzhiyun int ret;
461*4882a593Smuzhiyun u8 tid;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
464*4882a593Smuzhiyun while (tid != IEEE80211_NUM_TIDS) {
465*4882a593Smuzhiyun clear_bit(tid, si->tid_ba);
466*4882a593Smuzhiyun ret = ieee80211_start_tx_ba_session(sta, tid, 0);
467*4882a593Smuzhiyun if (ret == -EINVAL) {
468*4882a593Smuzhiyun struct ieee80211_txq *txq;
469*4882a593Smuzhiyun struct rtw_txq *rtwtxq;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun txq = sta->txq[tid];
472*4882a593Smuzhiyun rtwtxq = (struct rtw_txq *)txq->drv_priv;
473*4882a593Smuzhiyun set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
rtw_txq_ba_work(struct work_struct * work)480*4882a593Smuzhiyun static void rtw_txq_ba_work(struct work_struct *work)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
483*4882a593Smuzhiyun struct rtw_txq_ba_iter_data data;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
rtw_get_channel_params(struct cfg80211_chan_def * chandef,struct rtw_channel_params * chan_params)488*4882a593Smuzhiyun void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
489*4882a593Smuzhiyun struct rtw_channel_params *chan_params)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct ieee80211_channel *channel = chandef->chan;
492*4882a593Smuzhiyun enum nl80211_chan_width width = chandef->width;
493*4882a593Smuzhiyun u8 *cch_by_bw = chan_params->cch_by_bw;
494*4882a593Smuzhiyun u32 primary_freq, center_freq;
495*4882a593Smuzhiyun u8 center_chan;
496*4882a593Smuzhiyun u8 bandwidth = RTW_CHANNEL_WIDTH_20;
497*4882a593Smuzhiyun u8 primary_chan_idx = 0;
498*4882a593Smuzhiyun u8 i;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun center_chan = channel->hw_value;
501*4882a593Smuzhiyun primary_freq = channel->center_freq;
502*4882a593Smuzhiyun center_freq = chandef->center_freq1;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /* assign the center channel used while 20M bw is selected */
505*4882a593Smuzhiyun cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun switch (width) {
508*4882a593Smuzhiyun case NL80211_CHAN_WIDTH_20_NOHT:
509*4882a593Smuzhiyun case NL80211_CHAN_WIDTH_20:
510*4882a593Smuzhiyun bandwidth = RTW_CHANNEL_WIDTH_20;
511*4882a593Smuzhiyun primary_chan_idx = RTW_SC_DONT_CARE;
512*4882a593Smuzhiyun break;
513*4882a593Smuzhiyun case NL80211_CHAN_WIDTH_40:
514*4882a593Smuzhiyun bandwidth = RTW_CHANNEL_WIDTH_40;
515*4882a593Smuzhiyun if (primary_freq > center_freq) {
516*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_UPPER;
517*4882a593Smuzhiyun center_chan -= 2;
518*4882a593Smuzhiyun } else {
519*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_LOWER;
520*4882a593Smuzhiyun center_chan += 2;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun break;
523*4882a593Smuzhiyun case NL80211_CHAN_WIDTH_80:
524*4882a593Smuzhiyun bandwidth = RTW_CHANNEL_WIDTH_80;
525*4882a593Smuzhiyun if (primary_freq > center_freq) {
526*4882a593Smuzhiyun if (primary_freq - center_freq == 10) {
527*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_UPPER;
528*4882a593Smuzhiyun center_chan -= 2;
529*4882a593Smuzhiyun } else {
530*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_UPMOST;
531*4882a593Smuzhiyun center_chan -= 6;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun /* assign the center channel used
534*4882a593Smuzhiyun * while 40M bw is selected
535*4882a593Smuzhiyun */
536*4882a593Smuzhiyun cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
537*4882a593Smuzhiyun } else {
538*4882a593Smuzhiyun if (center_freq - primary_freq == 10) {
539*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_LOWER;
540*4882a593Smuzhiyun center_chan += 2;
541*4882a593Smuzhiyun } else {
542*4882a593Smuzhiyun primary_chan_idx = RTW_SC_20_LOWEST;
543*4882a593Smuzhiyun center_chan += 6;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun /* assign the center channel used
546*4882a593Smuzhiyun * while 40M bw is selected
547*4882a593Smuzhiyun */
548*4882a593Smuzhiyun cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun break;
551*4882a593Smuzhiyun default:
552*4882a593Smuzhiyun center_chan = 0;
553*4882a593Smuzhiyun break;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun chan_params->center_chan = center_chan;
557*4882a593Smuzhiyun chan_params->bandwidth = bandwidth;
558*4882a593Smuzhiyun chan_params->primary_chan_idx = primary_chan_idx;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun /* assign the center channel used while current bw is selected */
561*4882a593Smuzhiyun cch_by_bw[bandwidth] = center_chan;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
564*4882a593Smuzhiyun cch_by_bw[i] = 0;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
rtw_set_channel(struct rtw_dev * rtwdev)567*4882a593Smuzhiyun void rtw_set_channel(struct rtw_dev *rtwdev)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun struct ieee80211_hw *hw = rtwdev->hw;
570*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
571*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
572*4882a593Smuzhiyun struct rtw_channel_params ch_param;
573*4882a593Smuzhiyun u8 center_chan, bandwidth, primary_chan_idx;
574*4882a593Smuzhiyun u8 i;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun rtw_get_channel_params(&hw->conf.chandef, &ch_param);
577*4882a593Smuzhiyun if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
578*4882a593Smuzhiyun return;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun center_chan = ch_param.center_chan;
581*4882a593Smuzhiyun bandwidth = ch_param.bandwidth;
582*4882a593Smuzhiyun primary_chan_idx = ch_param.primary_chan_idx;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun hal->current_band_width = bandwidth;
585*4882a593Smuzhiyun hal->current_channel = center_chan;
586*4882a593Smuzhiyun hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
589*4882a593Smuzhiyun hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun if (hal->current_band_type == RTW_BAND_5G) {
594*4882a593Smuzhiyun rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
595*4882a593Smuzhiyun } else {
596*4882a593Smuzhiyun if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
597*4882a593Smuzhiyun rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
598*4882a593Smuzhiyun else
599*4882a593Smuzhiyun rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun rtw_phy_set_tx_power_level(rtwdev, center_chan);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun /* if the channel isn't set for scanning, we will do RF calibration
605*4882a593Smuzhiyun * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
606*4882a593Smuzhiyun * during scanning on each channel takes too long.
607*4882a593Smuzhiyun */
608*4882a593Smuzhiyun if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
609*4882a593Smuzhiyun rtwdev->need_rfk = true;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
rtw_chip_prepare_tx(struct rtw_dev * rtwdev)612*4882a593Smuzhiyun void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun if (rtwdev->need_rfk) {
617*4882a593Smuzhiyun rtwdev->need_rfk = false;
618*4882a593Smuzhiyun chip->ops->phy_calibration(rtwdev);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
rtw_vif_write_addr(struct rtw_dev * rtwdev,u32 start,u8 * addr)622*4882a593Smuzhiyun static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun int i;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun for (i = 0; i < ETH_ALEN; i++)
627*4882a593Smuzhiyun rtw_write8(rtwdev, start + i, addr[i]);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
rtw_vif_port_config(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,u32 config)630*4882a593Smuzhiyun void rtw_vif_port_config(struct rtw_dev *rtwdev,
631*4882a593Smuzhiyun struct rtw_vif *rtwvif,
632*4882a593Smuzhiyun u32 config)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun u32 addr, mask;
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun if (config & PORT_SET_MAC_ADDR) {
637*4882a593Smuzhiyun addr = rtwvif->conf->mac_addr.addr;
638*4882a593Smuzhiyun rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun if (config & PORT_SET_BSSID) {
641*4882a593Smuzhiyun addr = rtwvif->conf->bssid.addr;
642*4882a593Smuzhiyun rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun if (config & PORT_SET_NET_TYPE) {
645*4882a593Smuzhiyun addr = rtwvif->conf->net_type.addr;
646*4882a593Smuzhiyun mask = rtwvif->conf->net_type.mask;
647*4882a593Smuzhiyun rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun if (config & PORT_SET_AID) {
650*4882a593Smuzhiyun addr = rtwvif->conf->aid.addr;
651*4882a593Smuzhiyun mask = rtwvif->conf->aid.mask;
652*4882a593Smuzhiyun rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun if (config & PORT_SET_BCN_CTRL) {
655*4882a593Smuzhiyun addr = rtwvif->conf->bcn_ctrl.addr;
656*4882a593Smuzhiyun mask = rtwvif->conf->bcn_ctrl.mask;
657*4882a593Smuzhiyun rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
hw_bw_cap_to_bitamp(u8 bw_cap)661*4882a593Smuzhiyun static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
662*4882a593Smuzhiyun {
663*4882a593Smuzhiyun u8 bw = 0;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun switch (bw_cap) {
666*4882a593Smuzhiyun case EFUSE_HW_CAP_IGNORE:
667*4882a593Smuzhiyun case EFUSE_HW_CAP_SUPP_BW80:
668*4882a593Smuzhiyun bw |= BIT(RTW_CHANNEL_WIDTH_80);
669*4882a593Smuzhiyun fallthrough;
670*4882a593Smuzhiyun case EFUSE_HW_CAP_SUPP_BW40:
671*4882a593Smuzhiyun bw |= BIT(RTW_CHANNEL_WIDTH_40);
672*4882a593Smuzhiyun fallthrough;
673*4882a593Smuzhiyun default:
674*4882a593Smuzhiyun bw |= BIT(RTW_CHANNEL_WIDTH_20);
675*4882a593Smuzhiyun break;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun return bw;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
rtw_hw_config_rf_ant_num(struct rtw_dev * rtwdev,u8 hw_ant_num)681*4882a593Smuzhiyun static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
684*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
687*4882a593Smuzhiyun hw_ant_num >= hal->rf_path_num)
688*4882a593Smuzhiyun return;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun switch (hw_ant_num) {
691*4882a593Smuzhiyun case 1:
692*4882a593Smuzhiyun hal->rf_type = RF_1T1R;
693*4882a593Smuzhiyun hal->rf_path_num = 1;
694*4882a593Smuzhiyun if (!chip->fix_rf_phy_num)
695*4882a593Smuzhiyun hal->rf_phy_num = hal->rf_path_num;
696*4882a593Smuzhiyun hal->antenna_tx = BB_PATH_A;
697*4882a593Smuzhiyun hal->antenna_rx = BB_PATH_A;
698*4882a593Smuzhiyun break;
699*4882a593Smuzhiyun default:
700*4882a593Smuzhiyun WARN(1, "invalid hw configuration from efuse\n");
701*4882a593Smuzhiyun break;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun
get_vht_ra_mask(struct ieee80211_sta * sta)705*4882a593Smuzhiyun static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun u64 ra_mask = 0;
708*4882a593Smuzhiyun u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
709*4882a593Smuzhiyun u8 vht_mcs_cap;
710*4882a593Smuzhiyun int i, nss;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun /* 4SS, every two bits for MCS7/8/9 */
713*4882a593Smuzhiyun for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
714*4882a593Smuzhiyun vht_mcs_cap = mcs_map & 0x3;
715*4882a593Smuzhiyun switch (vht_mcs_cap) {
716*4882a593Smuzhiyun case 2: /* MCS9 */
717*4882a593Smuzhiyun ra_mask |= 0x3ffULL << nss;
718*4882a593Smuzhiyun break;
719*4882a593Smuzhiyun case 1: /* MCS8 */
720*4882a593Smuzhiyun ra_mask |= 0x1ffULL << nss;
721*4882a593Smuzhiyun break;
722*4882a593Smuzhiyun case 0: /* MCS7 */
723*4882a593Smuzhiyun ra_mask |= 0x0ffULL << nss;
724*4882a593Smuzhiyun break;
725*4882a593Smuzhiyun default:
726*4882a593Smuzhiyun break;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun return ra_mask;
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun
get_rate_id(u8 wireless_set,enum rtw_bandwidth bw_mode,u8 tx_num)733*4882a593Smuzhiyun static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun u8 rate_id = 0;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun switch (wireless_set) {
738*4882a593Smuzhiyun case WIRELESS_CCK:
739*4882a593Smuzhiyun rate_id = RTW_RATEID_B_20M;
740*4882a593Smuzhiyun break;
741*4882a593Smuzhiyun case WIRELESS_OFDM:
742*4882a593Smuzhiyun rate_id = RTW_RATEID_G;
743*4882a593Smuzhiyun break;
744*4882a593Smuzhiyun case WIRELESS_CCK | WIRELESS_OFDM:
745*4882a593Smuzhiyun rate_id = RTW_RATEID_BG;
746*4882a593Smuzhiyun break;
747*4882a593Smuzhiyun case WIRELESS_OFDM | WIRELESS_HT:
748*4882a593Smuzhiyun if (tx_num == 1)
749*4882a593Smuzhiyun rate_id = RTW_RATEID_GN_N1SS;
750*4882a593Smuzhiyun else if (tx_num == 2)
751*4882a593Smuzhiyun rate_id = RTW_RATEID_GN_N2SS;
752*4882a593Smuzhiyun else if (tx_num == 3)
753*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR5_N_3SS;
754*4882a593Smuzhiyun break;
755*4882a593Smuzhiyun case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
756*4882a593Smuzhiyun if (bw_mode == RTW_CHANNEL_WIDTH_40) {
757*4882a593Smuzhiyun if (tx_num == 1)
758*4882a593Smuzhiyun rate_id = RTW_RATEID_BGN_40M_1SS;
759*4882a593Smuzhiyun else if (tx_num == 2)
760*4882a593Smuzhiyun rate_id = RTW_RATEID_BGN_40M_2SS;
761*4882a593Smuzhiyun else if (tx_num == 3)
762*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR5_N_3SS;
763*4882a593Smuzhiyun else if (tx_num == 4)
764*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR7_N_4SS;
765*4882a593Smuzhiyun } else {
766*4882a593Smuzhiyun if (tx_num == 1)
767*4882a593Smuzhiyun rate_id = RTW_RATEID_BGN_20M_1SS;
768*4882a593Smuzhiyun else if (tx_num == 2)
769*4882a593Smuzhiyun rate_id = RTW_RATEID_BGN_20M_2SS;
770*4882a593Smuzhiyun else if (tx_num == 3)
771*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR5_N_3SS;
772*4882a593Smuzhiyun else if (tx_num == 4)
773*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR7_N_4SS;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun break;
776*4882a593Smuzhiyun case WIRELESS_OFDM | WIRELESS_VHT:
777*4882a593Smuzhiyun if (tx_num == 1)
778*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR1_AC_1SS;
779*4882a593Smuzhiyun else if (tx_num == 2)
780*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR0_AC_2SS;
781*4882a593Smuzhiyun else if (tx_num == 3)
782*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR4_AC_3SS;
783*4882a593Smuzhiyun else if (tx_num == 4)
784*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR6_AC_4SS;
785*4882a593Smuzhiyun break;
786*4882a593Smuzhiyun case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
787*4882a593Smuzhiyun if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
788*4882a593Smuzhiyun if (tx_num == 1)
789*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR1_AC_1SS;
790*4882a593Smuzhiyun else if (tx_num == 2)
791*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR0_AC_2SS;
792*4882a593Smuzhiyun else if (tx_num == 3)
793*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR4_AC_3SS;
794*4882a593Smuzhiyun else if (tx_num == 4)
795*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR6_AC_4SS;
796*4882a593Smuzhiyun } else {
797*4882a593Smuzhiyun if (tx_num == 1)
798*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
799*4882a593Smuzhiyun else if (tx_num == 2)
800*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
801*4882a593Smuzhiyun else if (tx_num == 3)
802*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR4_AC_3SS;
803*4882a593Smuzhiyun else if (tx_num == 4)
804*4882a593Smuzhiyun rate_id = RTW_RATEID_ARFR6_AC_4SS;
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun break;
807*4882a593Smuzhiyun default:
808*4882a593Smuzhiyun break;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun return rate_id;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun #define RA_MASK_CCK_RATES 0x0000f
815*4882a593Smuzhiyun #define RA_MASK_OFDM_RATES 0x00ff0
816*4882a593Smuzhiyun #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
817*4882a593Smuzhiyun #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
818*4882a593Smuzhiyun #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
819*4882a593Smuzhiyun #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
820*4882a593Smuzhiyun RA_MASK_HT_RATES_2SS | \
821*4882a593Smuzhiyun RA_MASK_HT_RATES_3SS)
822*4882a593Smuzhiyun #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
823*4882a593Smuzhiyun #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
824*4882a593Smuzhiyun #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
825*4882a593Smuzhiyun #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
826*4882a593Smuzhiyun RA_MASK_VHT_RATES_2SS | \
827*4882a593Smuzhiyun RA_MASK_VHT_RATES_3SS)
828*4882a593Smuzhiyun #define RA_MASK_CCK_IN_HT 0x00005
829*4882a593Smuzhiyun #define RA_MASK_CCK_IN_VHT 0x00005
830*4882a593Smuzhiyun #define RA_MASK_OFDM_IN_VHT 0x00010
831*4882a593Smuzhiyun #define RA_MASK_OFDM_IN_HT_2G 0x00010
832*4882a593Smuzhiyun #define RA_MASK_OFDM_IN_HT_5G 0x00030
833*4882a593Smuzhiyun
rtw_update_rate_mask(struct rtw_dev * rtwdev,struct rtw_sta_info * si,u64 ra_mask,bool is_vht_enable,u8 wireless_set)834*4882a593Smuzhiyun static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev,
835*4882a593Smuzhiyun struct rtw_sta_info *si,
836*4882a593Smuzhiyun u64 ra_mask, bool is_vht_enable,
837*4882a593Smuzhiyun u8 wireless_set)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
840*4882a593Smuzhiyun const struct cfg80211_bitrate_mask *mask = si->mask;
841*4882a593Smuzhiyun u64 cfg_mask = GENMASK_ULL(63, 0);
842*4882a593Smuzhiyun u8 rssi_level, band;
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun if (wireless_set != WIRELESS_CCK) {
845*4882a593Smuzhiyun rssi_level = si->rssi_level;
846*4882a593Smuzhiyun if (rssi_level == 0)
847*4882a593Smuzhiyun ra_mask &= 0xffffffffffffffffULL;
848*4882a593Smuzhiyun else if (rssi_level == 1)
849*4882a593Smuzhiyun ra_mask &= 0xfffffffffffffff0ULL;
850*4882a593Smuzhiyun else if (rssi_level == 2)
851*4882a593Smuzhiyun ra_mask &= 0xffffffffffffefe0ULL;
852*4882a593Smuzhiyun else if (rssi_level == 3)
853*4882a593Smuzhiyun ra_mask &= 0xffffffffffffcfc0ULL;
854*4882a593Smuzhiyun else if (rssi_level == 4)
855*4882a593Smuzhiyun ra_mask &= 0xffffffffffff8f80ULL;
856*4882a593Smuzhiyun else if (rssi_level >= 5)
857*4882a593Smuzhiyun ra_mask &= 0xffffffffffff0f00ULL;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun if (!si->use_cfg_mask)
861*4882a593Smuzhiyun return ra_mask;
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun band = hal->current_band_type;
864*4882a593Smuzhiyun if (band == RTW_BAND_2G) {
865*4882a593Smuzhiyun band = NL80211_BAND_2GHZ;
866*4882a593Smuzhiyun cfg_mask = mask->control[band].legacy;
867*4882a593Smuzhiyun } else if (band == RTW_BAND_5G) {
868*4882a593Smuzhiyun band = NL80211_BAND_5GHZ;
869*4882a593Smuzhiyun cfg_mask = u64_encode_bits(mask->control[band].legacy,
870*4882a593Smuzhiyun RA_MASK_OFDM_RATES);
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun if (!is_vht_enable) {
874*4882a593Smuzhiyun if (ra_mask & RA_MASK_HT_RATES_1SS)
875*4882a593Smuzhiyun cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
876*4882a593Smuzhiyun RA_MASK_HT_RATES_1SS);
877*4882a593Smuzhiyun if (ra_mask & RA_MASK_HT_RATES_2SS)
878*4882a593Smuzhiyun cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
879*4882a593Smuzhiyun RA_MASK_HT_RATES_2SS);
880*4882a593Smuzhiyun } else {
881*4882a593Smuzhiyun if (ra_mask & RA_MASK_VHT_RATES_1SS)
882*4882a593Smuzhiyun cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
883*4882a593Smuzhiyun RA_MASK_VHT_RATES_1SS);
884*4882a593Smuzhiyun if (ra_mask & RA_MASK_VHT_RATES_2SS)
885*4882a593Smuzhiyun cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
886*4882a593Smuzhiyun RA_MASK_VHT_RATES_2SS);
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun ra_mask &= cfg_mask;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun return ra_mask;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
rtw_update_sta_info(struct rtw_dev * rtwdev,struct rtw_sta_info * si)894*4882a593Smuzhiyun void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun struct ieee80211_sta *sta = si->sta;
897*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
898*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
899*4882a593Smuzhiyun u8 wireless_set;
900*4882a593Smuzhiyun u8 bw_mode;
901*4882a593Smuzhiyun u8 rate_id;
902*4882a593Smuzhiyun u8 rf_type = RF_1T1R;
903*4882a593Smuzhiyun u8 stbc_en = 0;
904*4882a593Smuzhiyun u8 ldpc_en = 0;
905*4882a593Smuzhiyun u8 tx_num = 1;
906*4882a593Smuzhiyun u64 ra_mask = 0;
907*4882a593Smuzhiyun bool is_vht_enable = false;
908*4882a593Smuzhiyun bool is_support_sgi = false;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
911*4882a593Smuzhiyun is_vht_enable = true;
912*4882a593Smuzhiyun ra_mask |= get_vht_ra_mask(sta);
913*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
914*4882a593Smuzhiyun stbc_en = VHT_STBC_EN;
915*4882a593Smuzhiyun if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
916*4882a593Smuzhiyun ldpc_en = VHT_LDPC_EN;
917*4882a593Smuzhiyun } else if (sta->ht_cap.ht_supported) {
918*4882a593Smuzhiyun ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) |
919*4882a593Smuzhiyun (sta->ht_cap.mcs.rx_mask[0] << 12);
920*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
921*4882a593Smuzhiyun stbc_en = HT_STBC_EN;
922*4882a593Smuzhiyun if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
923*4882a593Smuzhiyun ldpc_en = HT_LDPC_EN;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (efuse->hw_cap.nss == 1)
927*4882a593Smuzhiyun ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun if (hal->current_band_type == RTW_BAND_5G) {
930*4882a593Smuzhiyun ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4;
931*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
932*4882a593Smuzhiyun ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
933*4882a593Smuzhiyun wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
934*4882a593Smuzhiyun } else if (sta->ht_cap.ht_supported) {
935*4882a593Smuzhiyun ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
936*4882a593Smuzhiyun wireless_set = WIRELESS_OFDM | WIRELESS_HT;
937*4882a593Smuzhiyun } else {
938*4882a593Smuzhiyun wireless_set = WIRELESS_OFDM;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun } else if (hal->current_band_type == RTW_BAND_2G) {
941*4882a593Smuzhiyun ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
942*4882a593Smuzhiyun if (sta->vht_cap.vht_supported) {
943*4882a593Smuzhiyun ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
944*4882a593Smuzhiyun RA_MASK_OFDM_IN_VHT;
945*4882a593Smuzhiyun wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
946*4882a593Smuzhiyun WIRELESS_HT | WIRELESS_VHT;
947*4882a593Smuzhiyun } else if (sta->ht_cap.ht_supported) {
948*4882a593Smuzhiyun ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
949*4882a593Smuzhiyun RA_MASK_OFDM_IN_HT_2G;
950*4882a593Smuzhiyun wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
951*4882a593Smuzhiyun WIRELESS_HT;
952*4882a593Smuzhiyun } else if (sta->supp_rates[0] <= 0xf) {
953*4882a593Smuzhiyun wireless_set = WIRELESS_CCK;
954*4882a593Smuzhiyun } else {
955*4882a593Smuzhiyun wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun } else {
958*4882a593Smuzhiyun rtw_err(rtwdev, "Unknown band type\n");
959*4882a593Smuzhiyun wireless_set = 0;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun switch (sta->bandwidth) {
963*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_80:
964*4882a593Smuzhiyun bw_mode = RTW_CHANNEL_WIDTH_80;
965*4882a593Smuzhiyun is_support_sgi = sta->vht_cap.vht_supported &&
966*4882a593Smuzhiyun (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
967*4882a593Smuzhiyun break;
968*4882a593Smuzhiyun case IEEE80211_STA_RX_BW_40:
969*4882a593Smuzhiyun bw_mode = RTW_CHANNEL_WIDTH_40;
970*4882a593Smuzhiyun is_support_sgi = sta->ht_cap.ht_supported &&
971*4882a593Smuzhiyun (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
972*4882a593Smuzhiyun break;
973*4882a593Smuzhiyun default:
974*4882a593Smuzhiyun bw_mode = RTW_CHANNEL_WIDTH_20;
975*4882a593Smuzhiyun is_support_sgi = sta->ht_cap.ht_supported &&
976*4882a593Smuzhiyun (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
977*4882a593Smuzhiyun break;
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) {
981*4882a593Smuzhiyun tx_num = 2;
982*4882a593Smuzhiyun rf_type = RF_2T2R;
983*4882a593Smuzhiyun } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) {
984*4882a593Smuzhiyun tx_num = 2;
985*4882a593Smuzhiyun rf_type = RF_2T2R;
986*4882a593Smuzhiyun }
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable,
991*4882a593Smuzhiyun wireless_set);
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun si->bw_mode = bw_mode;
994*4882a593Smuzhiyun si->stbc_en = stbc_en;
995*4882a593Smuzhiyun si->ldpc_en = ldpc_en;
996*4882a593Smuzhiyun si->rf_type = rf_type;
997*4882a593Smuzhiyun si->wireless_set = wireless_set;
998*4882a593Smuzhiyun si->sgi_enable = is_support_sgi;
999*4882a593Smuzhiyun si->vht_enable = is_vht_enable;
1000*4882a593Smuzhiyun si->ra_mask = ra_mask;
1001*4882a593Smuzhiyun si->rate_id = rate_id;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun rtw_fw_send_ra_info(rtwdev, si);
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
rtw_wait_firmware_completion(struct rtw_dev * rtwdev)1006*4882a593Smuzhiyun static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1007*4882a593Smuzhiyun {
1008*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
1009*4882a593Smuzhiyun struct rtw_fw_state *fw;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun fw = &rtwdev->fw;
1012*4882a593Smuzhiyun wait_for_completion(&fw->completion);
1013*4882a593Smuzhiyun if (!fw->firmware)
1014*4882a593Smuzhiyun return -EINVAL;
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun if (chip->wow_fw_name) {
1017*4882a593Smuzhiyun fw = &rtwdev->wow_fw;
1018*4882a593Smuzhiyun wait_for_completion(&fw->completion);
1019*4882a593Smuzhiyun if (!fw->firmware)
1020*4882a593Smuzhiyun return -EINVAL;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun return 0;
1024*4882a593Smuzhiyun }
1025*4882a593Smuzhiyun
rtw_power_on(struct rtw_dev * rtwdev)1026*4882a593Smuzhiyun static int rtw_power_on(struct rtw_dev *rtwdev)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
1029*4882a593Smuzhiyun struct rtw_fw_state *fw = &rtwdev->fw;
1030*4882a593Smuzhiyun bool wifi_only;
1031*4882a593Smuzhiyun int ret;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun ret = rtw_hci_setup(rtwdev);
1034*4882a593Smuzhiyun if (ret) {
1035*4882a593Smuzhiyun rtw_err(rtwdev, "failed to setup hci\n");
1036*4882a593Smuzhiyun goto err;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun /* power on MAC before firmware downloaded */
1040*4882a593Smuzhiyun ret = rtw_mac_power_on(rtwdev);
1041*4882a593Smuzhiyun if (ret) {
1042*4882a593Smuzhiyun rtw_err(rtwdev, "failed to power on mac\n");
1043*4882a593Smuzhiyun goto err;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun ret = rtw_wait_firmware_completion(rtwdev);
1047*4882a593Smuzhiyun if (ret) {
1048*4882a593Smuzhiyun rtw_err(rtwdev, "failed to wait firmware completion\n");
1049*4882a593Smuzhiyun goto err_off;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun ret = rtw_download_firmware(rtwdev, fw);
1053*4882a593Smuzhiyun if (ret) {
1054*4882a593Smuzhiyun rtw_err(rtwdev, "failed to download firmware\n");
1055*4882a593Smuzhiyun goto err_off;
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun /* config mac after firmware downloaded */
1059*4882a593Smuzhiyun ret = rtw_mac_init(rtwdev);
1060*4882a593Smuzhiyun if (ret) {
1061*4882a593Smuzhiyun rtw_err(rtwdev, "failed to configure mac\n");
1062*4882a593Smuzhiyun goto err_off;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun chip->ops->phy_set_param(rtwdev);
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun ret = rtw_hci_start(rtwdev);
1068*4882a593Smuzhiyun if (ret) {
1069*4882a593Smuzhiyun rtw_err(rtwdev, "failed to start hci\n");
1070*4882a593Smuzhiyun goto err_off;
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun /* send H2C after HCI has started */
1074*4882a593Smuzhiyun rtw_fw_send_general_info(rtwdev);
1075*4882a593Smuzhiyun rtw_fw_send_phydm_info(rtwdev);
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun wifi_only = !rtwdev->efuse.btcoex;
1078*4882a593Smuzhiyun rtw_coex_power_on_setting(rtwdev);
1079*4882a593Smuzhiyun rtw_coex_init_hw_config(rtwdev, wifi_only);
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun return 0;
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun err_off:
1084*4882a593Smuzhiyun rtw_mac_power_off(rtwdev);
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun err:
1087*4882a593Smuzhiyun return ret;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
rtw_core_start(struct rtw_dev * rtwdev)1090*4882a593Smuzhiyun int rtw_core_start(struct rtw_dev *rtwdev)
1091*4882a593Smuzhiyun {
1092*4882a593Smuzhiyun int ret;
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun ret = rtw_power_on(rtwdev);
1095*4882a593Smuzhiyun if (ret)
1096*4882a593Smuzhiyun return ret;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun rtw_sec_enable_sec_engine(rtwdev);
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun /* rcr reset after powered on */
1101*4882a593Smuzhiyun rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1104*4882a593Smuzhiyun RTW_WATCH_DOG_DELAY_TIME);
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun return 0;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
rtw_power_off(struct rtw_dev * rtwdev)1111*4882a593Smuzhiyun static void rtw_power_off(struct rtw_dev *rtwdev)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun rtw_hci_stop(rtwdev);
1114*4882a593Smuzhiyun rtw_mac_power_off(rtwdev);
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
rtw_core_stop(struct rtw_dev * rtwdev)1117*4882a593Smuzhiyun void rtw_core_stop(struct rtw_dev *rtwdev)
1118*4882a593Smuzhiyun {
1119*4882a593Smuzhiyun struct rtw_coex *coex = &rtwdev->coex;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1122*4882a593Smuzhiyun clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun mutex_unlock(&rtwdev->mutex);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun cancel_work_sync(&rtwdev->c2h_work);
1127*4882a593Smuzhiyun cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1128*4882a593Smuzhiyun cancel_delayed_work_sync(&coex->bt_relink_work);
1129*4882a593Smuzhiyun cancel_delayed_work_sync(&coex->bt_reenable_work);
1130*4882a593Smuzhiyun cancel_delayed_work_sync(&coex->defreeze_work);
1131*4882a593Smuzhiyun cancel_delayed_work_sync(&coex->wl_remain_work);
1132*4882a593Smuzhiyun cancel_delayed_work_sync(&coex->bt_remain_work);
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun mutex_lock(&rtwdev->mutex);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun rtw_power_off(rtwdev);
1137*4882a593Smuzhiyun }
1138*4882a593Smuzhiyun
rtw_init_ht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)1139*4882a593Smuzhiyun static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1140*4882a593Smuzhiyun struct ieee80211_sta_ht_cap *ht_cap)
1141*4882a593Smuzhiyun {
1142*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun ht_cap->ht_supported = true;
1145*4882a593Smuzhiyun ht_cap->cap = 0;
1146*4882a593Smuzhiyun ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1147*4882a593Smuzhiyun IEEE80211_HT_CAP_MAX_AMSDU |
1148*4882a593Smuzhiyun (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun if (rtw_chip_has_rx_ldpc(rtwdev))
1151*4882a593Smuzhiyun ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1154*4882a593Smuzhiyun ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1155*4882a593Smuzhiyun IEEE80211_HT_CAP_DSSSCCK40 |
1156*4882a593Smuzhiyun IEEE80211_HT_CAP_SGI_40;
1157*4882a593Smuzhiyun ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1158*4882a593Smuzhiyun ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
1159*4882a593Smuzhiyun ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1160*4882a593Smuzhiyun if (efuse->hw_cap.nss > 1) {
1161*4882a593Smuzhiyun ht_cap->mcs.rx_mask[0] = 0xFF;
1162*4882a593Smuzhiyun ht_cap->mcs.rx_mask[1] = 0xFF;
1163*4882a593Smuzhiyun ht_cap->mcs.rx_mask[4] = 0x01;
1164*4882a593Smuzhiyun ht_cap->mcs.rx_highest = cpu_to_le16(300);
1165*4882a593Smuzhiyun } else {
1166*4882a593Smuzhiyun ht_cap->mcs.rx_mask[0] = 0xFF;
1167*4882a593Smuzhiyun ht_cap->mcs.rx_mask[1] = 0x00;
1168*4882a593Smuzhiyun ht_cap->mcs.rx_mask[4] = 0x01;
1169*4882a593Smuzhiyun ht_cap->mcs.rx_highest = cpu_to_le16(150);
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun
rtw_init_vht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)1173*4882a593Smuzhiyun static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1174*4882a593Smuzhiyun struct ieee80211_sta_vht_cap *vht_cap)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
1177*4882a593Smuzhiyun u16 mcs_map;
1178*4882a593Smuzhiyun __le16 highest;
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1181*4882a593Smuzhiyun efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1182*4882a593Smuzhiyun return;
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun vht_cap->vht_supported = true;
1185*4882a593Smuzhiyun vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1186*4882a593Smuzhiyun IEEE80211_VHT_CAP_SHORT_GI_80 |
1187*4882a593Smuzhiyun IEEE80211_VHT_CAP_RXSTBC_1 |
1188*4882a593Smuzhiyun IEEE80211_VHT_CAP_HTC_VHT |
1189*4882a593Smuzhiyun IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1190*4882a593Smuzhiyun 0;
1191*4882a593Smuzhiyun if (rtwdev->hal.rf_path_num > 1)
1192*4882a593Smuzhiyun vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1193*4882a593Smuzhiyun vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1194*4882a593Smuzhiyun IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1195*4882a593Smuzhiyun vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1196*4882a593Smuzhiyun IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun if (rtw_chip_has_rx_ldpc(rtwdev))
1199*4882a593Smuzhiyun vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1202*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1203*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1204*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1205*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1206*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1207*4882a593Smuzhiyun IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1208*4882a593Smuzhiyun if (efuse->hw_cap.nss > 1) {
1209*4882a593Smuzhiyun highest = cpu_to_le16(780);
1210*4882a593Smuzhiyun mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1211*4882a593Smuzhiyun } else {
1212*4882a593Smuzhiyun highest = cpu_to_le16(390);
1213*4882a593Smuzhiyun mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1217*4882a593Smuzhiyun vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1218*4882a593Smuzhiyun vht_cap->vht_mcs.rx_highest = highest;
1219*4882a593Smuzhiyun vht_cap->vht_mcs.tx_highest = highest;
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun
rtw_set_supported_band(struct ieee80211_hw * hw,struct rtw_chip_info * chip)1222*4882a593Smuzhiyun static void rtw_set_supported_band(struct ieee80211_hw *hw,
1223*4882a593Smuzhiyun struct rtw_chip_info *chip)
1224*4882a593Smuzhiyun {
1225*4882a593Smuzhiyun struct rtw_dev *rtwdev = hw->priv;
1226*4882a593Smuzhiyun struct ieee80211_supported_band *sband;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun if (chip->band & RTW_BAND_2G) {
1229*4882a593Smuzhiyun sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1230*4882a593Smuzhiyun if (!sband)
1231*4882a593Smuzhiyun goto err_out;
1232*4882a593Smuzhiyun if (chip->ht_supported)
1233*4882a593Smuzhiyun rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1234*4882a593Smuzhiyun hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun if (chip->band & RTW_BAND_5G) {
1238*4882a593Smuzhiyun sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1239*4882a593Smuzhiyun if (!sband)
1240*4882a593Smuzhiyun goto err_out;
1241*4882a593Smuzhiyun if (chip->ht_supported)
1242*4882a593Smuzhiyun rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1243*4882a593Smuzhiyun if (chip->vht_supported)
1244*4882a593Smuzhiyun rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1245*4882a593Smuzhiyun hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun return;
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun err_out:
1251*4882a593Smuzhiyun rtw_err(rtwdev, "failed to set supported band\n");
1252*4882a593Smuzhiyun kfree(sband);
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
rtw_unset_supported_band(struct ieee80211_hw * hw,struct rtw_chip_info * chip)1255*4882a593Smuzhiyun static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1256*4882a593Smuzhiyun struct rtw_chip_info *chip)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1259*4882a593Smuzhiyun kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
__update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1262*4882a593Smuzhiyun static void __update_firmware_info(struct rtw_dev *rtwdev,
1263*4882a593Smuzhiyun struct rtw_fw_state *fw)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun const struct rtw_fw_hdr *fw_hdr =
1266*4882a593Smuzhiyun (const struct rtw_fw_hdr *)fw->firmware->data;
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1269*4882a593Smuzhiyun fw->version = le16_to_cpu(fw_hdr->version);
1270*4882a593Smuzhiyun fw->sub_version = fw_hdr->subversion;
1271*4882a593Smuzhiyun fw->sub_index = fw_hdr->subindex;
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun
__update_firmware_info_legacy(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1274*4882a593Smuzhiyun static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1275*4882a593Smuzhiyun struct rtw_fw_state *fw)
1276*4882a593Smuzhiyun {
1277*4882a593Smuzhiyun struct rtw_fw_hdr_legacy *legacy =
1278*4882a593Smuzhiyun (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun fw->h2c_version = 0;
1281*4882a593Smuzhiyun fw->version = le16_to_cpu(legacy->version);
1282*4882a593Smuzhiyun fw->sub_version = legacy->subversion1;
1283*4882a593Smuzhiyun fw->sub_index = legacy->subversion2;
1284*4882a593Smuzhiyun }
1285*4882a593Smuzhiyun
update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1286*4882a593Smuzhiyun static void update_firmware_info(struct rtw_dev *rtwdev,
1287*4882a593Smuzhiyun struct rtw_fw_state *fw)
1288*4882a593Smuzhiyun {
1289*4882a593Smuzhiyun if (rtw_chip_wcpu_11n(rtwdev))
1290*4882a593Smuzhiyun __update_firmware_info_legacy(rtwdev, fw);
1291*4882a593Smuzhiyun else
1292*4882a593Smuzhiyun __update_firmware_info(rtwdev, fw);
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
rtw_load_firmware_cb(const struct firmware * firmware,void * context)1295*4882a593Smuzhiyun static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1296*4882a593Smuzhiyun {
1297*4882a593Smuzhiyun struct rtw_fw_state *fw = context;
1298*4882a593Smuzhiyun struct rtw_dev *rtwdev = fw->rtwdev;
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun if (!firmware || !firmware->data) {
1301*4882a593Smuzhiyun rtw_err(rtwdev, "failed to request firmware\n");
1302*4882a593Smuzhiyun complete_all(&fw->completion);
1303*4882a593Smuzhiyun return;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun fw->firmware = firmware;
1307*4882a593Smuzhiyun update_firmware_info(rtwdev, fw);
1308*4882a593Smuzhiyun complete_all(&fw->completion);
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1311*4882a593Smuzhiyun fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun
rtw_load_firmware(struct rtw_dev * rtwdev,enum rtw_fw_type type)1314*4882a593Smuzhiyun static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1315*4882a593Smuzhiyun {
1316*4882a593Smuzhiyun const char *fw_name;
1317*4882a593Smuzhiyun struct rtw_fw_state *fw;
1318*4882a593Smuzhiyun int ret;
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun switch (type) {
1321*4882a593Smuzhiyun case RTW_WOWLAN_FW:
1322*4882a593Smuzhiyun fw = &rtwdev->wow_fw;
1323*4882a593Smuzhiyun fw_name = rtwdev->chip->wow_fw_name;
1324*4882a593Smuzhiyun break;
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun case RTW_NORMAL_FW:
1327*4882a593Smuzhiyun fw = &rtwdev->fw;
1328*4882a593Smuzhiyun fw_name = rtwdev->chip->fw_name;
1329*4882a593Smuzhiyun break;
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun default:
1332*4882a593Smuzhiyun rtw_warn(rtwdev, "unsupported firmware type\n");
1333*4882a593Smuzhiyun return -ENOENT;
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun fw->rtwdev = rtwdev;
1337*4882a593Smuzhiyun init_completion(&fw->completion);
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1340*4882a593Smuzhiyun GFP_KERNEL, fw, rtw_load_firmware_cb);
1341*4882a593Smuzhiyun if (ret) {
1342*4882a593Smuzhiyun rtw_err(rtwdev, "failed to async firmware request\n");
1343*4882a593Smuzhiyun return ret;
1344*4882a593Smuzhiyun }
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun return 0;
1347*4882a593Smuzhiyun }
1348*4882a593Smuzhiyun
rtw_chip_parameter_setup(struct rtw_dev * rtwdev)1349*4882a593Smuzhiyun static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1350*4882a593Smuzhiyun {
1351*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
1352*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
1353*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
1354*4882a593Smuzhiyun int ret = 0;
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun switch (rtw_hci_type(rtwdev)) {
1357*4882a593Smuzhiyun case RTW_HCI_TYPE_PCIE:
1358*4882a593Smuzhiyun rtwdev->hci.rpwm_addr = 0x03d9;
1359*4882a593Smuzhiyun rtwdev->hci.cpwm_addr = 0x03da;
1360*4882a593Smuzhiyun break;
1361*4882a593Smuzhiyun default:
1362*4882a593Smuzhiyun rtw_err(rtwdev, "unsupported hci type\n");
1363*4882a593Smuzhiyun return -EINVAL;
1364*4882a593Smuzhiyun }
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1367*4882a593Smuzhiyun hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1368*4882a593Smuzhiyun hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1369*4882a593Smuzhiyun if (hal->chip_version & BIT_RF_TYPE_ID) {
1370*4882a593Smuzhiyun hal->rf_type = RF_2T2R;
1371*4882a593Smuzhiyun hal->rf_path_num = 2;
1372*4882a593Smuzhiyun hal->antenna_tx = BB_PATH_AB;
1373*4882a593Smuzhiyun hal->antenna_rx = BB_PATH_AB;
1374*4882a593Smuzhiyun } else {
1375*4882a593Smuzhiyun hal->rf_type = RF_1T1R;
1376*4882a593Smuzhiyun hal->rf_path_num = 1;
1377*4882a593Smuzhiyun hal->antenna_tx = BB_PATH_A;
1378*4882a593Smuzhiyun hal->antenna_rx = BB_PATH_A;
1379*4882a593Smuzhiyun }
1380*4882a593Smuzhiyun hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1381*4882a593Smuzhiyun hal->rf_path_num;
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun efuse->physical_size = chip->phy_efuse_size;
1384*4882a593Smuzhiyun efuse->logical_size = chip->log_efuse_size;
1385*4882a593Smuzhiyun efuse->protect_size = chip->ptct_efuse_size;
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun /* default use ack */
1388*4882a593Smuzhiyun rtwdev->hal.rcr |= BIT_VHT_DACK;
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun hal->bfee_sts_cap = 3;
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun return ret;
1393*4882a593Smuzhiyun }
1394*4882a593Smuzhiyun
rtw_chip_efuse_enable(struct rtw_dev * rtwdev)1395*4882a593Smuzhiyun static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1396*4882a593Smuzhiyun {
1397*4882a593Smuzhiyun struct rtw_fw_state *fw = &rtwdev->fw;
1398*4882a593Smuzhiyun int ret;
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun ret = rtw_hci_setup(rtwdev);
1401*4882a593Smuzhiyun if (ret) {
1402*4882a593Smuzhiyun rtw_err(rtwdev, "failed to setup hci\n");
1403*4882a593Smuzhiyun goto err;
1404*4882a593Smuzhiyun }
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun ret = rtw_mac_power_on(rtwdev);
1407*4882a593Smuzhiyun if (ret) {
1408*4882a593Smuzhiyun rtw_err(rtwdev, "failed to power on mac\n");
1409*4882a593Smuzhiyun goto err;
1410*4882a593Smuzhiyun }
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun wait_for_completion(&fw->completion);
1415*4882a593Smuzhiyun if (!fw->firmware) {
1416*4882a593Smuzhiyun ret = -EINVAL;
1417*4882a593Smuzhiyun rtw_err(rtwdev, "failed to load firmware\n");
1418*4882a593Smuzhiyun goto err;
1419*4882a593Smuzhiyun }
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun ret = rtw_download_firmware(rtwdev, fw);
1422*4882a593Smuzhiyun if (ret) {
1423*4882a593Smuzhiyun rtw_err(rtwdev, "failed to download firmware\n");
1424*4882a593Smuzhiyun goto err_off;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun return 0;
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun err_off:
1430*4882a593Smuzhiyun rtw_mac_power_off(rtwdev);
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun err:
1433*4882a593Smuzhiyun return ret;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun
rtw_dump_hw_feature(struct rtw_dev * rtwdev)1436*4882a593Smuzhiyun static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1437*4882a593Smuzhiyun {
1438*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
1439*4882a593Smuzhiyun u8 hw_feature[HW_FEATURE_LEN];
1440*4882a593Smuzhiyun u8 id;
1441*4882a593Smuzhiyun u8 bw;
1442*4882a593Smuzhiyun int i;
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun id = rtw_read8(rtwdev, REG_C2HEVT);
1445*4882a593Smuzhiyun if (id != C2H_HW_FEATURE_REPORT) {
1446*4882a593Smuzhiyun rtw_err(rtwdev, "failed to read hw feature report\n");
1447*4882a593Smuzhiyun return -EBUSY;
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun for (i = 0; i < HW_FEATURE_LEN; i++)
1451*4882a593Smuzhiyun hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1452*4882a593Smuzhiyun
1453*4882a593Smuzhiyun rtw_write8(rtwdev, REG_C2HEVT, 0);
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1456*4882a593Smuzhiyun efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1457*4882a593Smuzhiyun efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1458*4882a593Smuzhiyun efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1459*4882a593Smuzhiyun efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1460*4882a593Smuzhiyun efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1465*4882a593Smuzhiyun efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1466*4882a593Smuzhiyun efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1469*4882a593Smuzhiyun "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1470*4882a593Smuzhiyun efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1471*4882a593Smuzhiyun efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun return 0;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun
rtw_chip_efuse_disable(struct rtw_dev * rtwdev)1476*4882a593Smuzhiyun static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1477*4882a593Smuzhiyun {
1478*4882a593Smuzhiyun rtw_hci_stop(rtwdev);
1479*4882a593Smuzhiyun rtw_mac_power_off(rtwdev);
1480*4882a593Smuzhiyun }
1481*4882a593Smuzhiyun
rtw_chip_efuse_info_setup(struct rtw_dev * rtwdev)1482*4882a593Smuzhiyun static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1483*4882a593Smuzhiyun {
1484*4882a593Smuzhiyun struct rtw_efuse *efuse = &rtwdev->efuse;
1485*4882a593Smuzhiyun int ret;
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun mutex_lock(&rtwdev->mutex);
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun /* power on mac to read efuse */
1490*4882a593Smuzhiyun ret = rtw_chip_efuse_enable(rtwdev);
1491*4882a593Smuzhiyun if (ret)
1492*4882a593Smuzhiyun goto out_unlock;
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun ret = rtw_parse_efuse_map(rtwdev);
1495*4882a593Smuzhiyun if (ret)
1496*4882a593Smuzhiyun goto out_disable;
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun ret = rtw_dump_hw_feature(rtwdev);
1499*4882a593Smuzhiyun if (ret)
1500*4882a593Smuzhiyun goto out_disable;
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun ret = rtw_check_supported_rfe(rtwdev);
1503*4882a593Smuzhiyun if (ret)
1504*4882a593Smuzhiyun goto out_disable;
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun if (efuse->crystal_cap == 0xff)
1507*4882a593Smuzhiyun efuse->crystal_cap = 0;
1508*4882a593Smuzhiyun if (efuse->pa_type_2g == 0xff)
1509*4882a593Smuzhiyun efuse->pa_type_2g = 0;
1510*4882a593Smuzhiyun if (efuse->pa_type_5g == 0xff)
1511*4882a593Smuzhiyun efuse->pa_type_5g = 0;
1512*4882a593Smuzhiyun if (efuse->lna_type_2g == 0xff)
1513*4882a593Smuzhiyun efuse->lna_type_2g = 0;
1514*4882a593Smuzhiyun if (efuse->lna_type_5g == 0xff)
1515*4882a593Smuzhiyun efuse->lna_type_5g = 0;
1516*4882a593Smuzhiyun if (efuse->channel_plan == 0xff)
1517*4882a593Smuzhiyun efuse->channel_plan = 0x7f;
1518*4882a593Smuzhiyun if (efuse->rf_board_option == 0xff)
1519*4882a593Smuzhiyun efuse->rf_board_option = 0;
1520*4882a593Smuzhiyun if (efuse->bt_setting & BIT(0))
1521*4882a593Smuzhiyun efuse->share_ant = true;
1522*4882a593Smuzhiyun if (efuse->regd == 0xff)
1523*4882a593Smuzhiyun efuse->regd = 0;
1524*4882a593Smuzhiyun if (efuse->tx_bb_swing_setting_2g == 0xff)
1525*4882a593Smuzhiyun efuse->tx_bb_swing_setting_2g = 0;
1526*4882a593Smuzhiyun if (efuse->tx_bb_swing_setting_5g == 0xff)
1527*4882a593Smuzhiyun efuse->tx_bb_swing_setting_5g = 0;
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1530*4882a593Smuzhiyun efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1531*4882a593Smuzhiyun efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1532*4882a593Smuzhiyun efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1533*4882a593Smuzhiyun efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun out_disable:
1536*4882a593Smuzhiyun rtw_chip_efuse_disable(rtwdev);
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun out_unlock:
1539*4882a593Smuzhiyun mutex_unlock(&rtwdev->mutex);
1540*4882a593Smuzhiyun return ret;
1541*4882a593Smuzhiyun }
1542*4882a593Smuzhiyun
rtw_chip_board_info_setup(struct rtw_dev * rtwdev)1543*4882a593Smuzhiyun static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1544*4882a593Smuzhiyun {
1545*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
1546*4882a593Smuzhiyun const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun if (!rfe_def)
1549*4882a593Smuzhiyun return -ENODEV;
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun rtw_phy_setup_phy_cond(rtwdev, 0);
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun rtw_phy_init_tx_power(rtwdev);
1554*4882a593Smuzhiyun rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1555*4882a593Smuzhiyun rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1556*4882a593Smuzhiyun rtw_phy_tx_power_by_rate_config(hal);
1557*4882a593Smuzhiyun rtw_phy_tx_power_limit_config(hal);
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun return 0;
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun
rtw_chip_info_setup(struct rtw_dev * rtwdev)1562*4882a593Smuzhiyun int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun int ret;
1565*4882a593Smuzhiyun
1566*4882a593Smuzhiyun ret = rtw_chip_parameter_setup(rtwdev);
1567*4882a593Smuzhiyun if (ret) {
1568*4882a593Smuzhiyun rtw_err(rtwdev, "failed to setup chip parameters\n");
1569*4882a593Smuzhiyun goto err_out;
1570*4882a593Smuzhiyun }
1571*4882a593Smuzhiyun
1572*4882a593Smuzhiyun ret = rtw_chip_efuse_info_setup(rtwdev);
1573*4882a593Smuzhiyun if (ret) {
1574*4882a593Smuzhiyun rtw_err(rtwdev, "failed to setup chip efuse info\n");
1575*4882a593Smuzhiyun goto err_out;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun ret = rtw_chip_board_info_setup(rtwdev);
1579*4882a593Smuzhiyun if (ret) {
1580*4882a593Smuzhiyun rtw_err(rtwdev, "failed to setup chip board info\n");
1581*4882a593Smuzhiyun goto err_out;
1582*4882a593Smuzhiyun }
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun return 0;
1585*4882a593Smuzhiyun
1586*4882a593Smuzhiyun err_out:
1587*4882a593Smuzhiyun return ret;
1588*4882a593Smuzhiyun }
1589*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_chip_info_setup);
1590*4882a593Smuzhiyun
rtw_stats_init(struct rtw_dev * rtwdev)1591*4882a593Smuzhiyun static void rtw_stats_init(struct rtw_dev *rtwdev)
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun struct rtw_traffic_stats *stats = &rtwdev->stats;
1594*4882a593Smuzhiyun struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1595*4882a593Smuzhiyun int i;
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun ewma_tp_init(&stats->tx_ewma_tp);
1598*4882a593Smuzhiyun ewma_tp_init(&stats->rx_ewma_tp);
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun for (i = 0; i < RTW_EVM_NUM; i++)
1601*4882a593Smuzhiyun ewma_evm_init(&dm_info->ewma_evm[i]);
1602*4882a593Smuzhiyun for (i = 0; i < RTW_SNR_NUM; i++)
1603*4882a593Smuzhiyun ewma_snr_init(&dm_info->ewma_snr[i]);
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
rtw_core_init(struct rtw_dev * rtwdev)1606*4882a593Smuzhiyun int rtw_core_init(struct rtw_dev *rtwdev)
1607*4882a593Smuzhiyun {
1608*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
1609*4882a593Smuzhiyun struct rtw_coex *coex = &rtwdev->coex;
1610*4882a593Smuzhiyun int ret;
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
1613*4882a593Smuzhiyun INIT_LIST_HEAD(&rtwdev->txqs);
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun timer_setup(&rtwdev->tx_report.purge_timer,
1616*4882a593Smuzhiyun rtw_tx_report_purge_timer, 0);
1617*4882a593Smuzhiyun tasklet_setup(&rtwdev->tx_tasklet, rtw_tx_tasklet);
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
1620*4882a593Smuzhiyun INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
1621*4882a593Smuzhiyun INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
1622*4882a593Smuzhiyun INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
1623*4882a593Smuzhiyun INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
1624*4882a593Smuzhiyun INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
1625*4882a593Smuzhiyun INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
1626*4882a593Smuzhiyun INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
1627*4882a593Smuzhiyun INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
1628*4882a593Smuzhiyun skb_queue_head_init(&rtwdev->c2h_queue);
1629*4882a593Smuzhiyun skb_queue_head_init(&rtwdev->coex.queue);
1630*4882a593Smuzhiyun skb_queue_head_init(&rtwdev->tx_report.queue);
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun spin_lock_init(&rtwdev->rf_lock);
1633*4882a593Smuzhiyun spin_lock_init(&rtwdev->h2c.lock);
1634*4882a593Smuzhiyun spin_lock_init(&rtwdev->txq_lock);
1635*4882a593Smuzhiyun spin_lock_init(&rtwdev->tx_report.q_lock);
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun mutex_init(&rtwdev->mutex);
1638*4882a593Smuzhiyun mutex_init(&rtwdev->coex.mutex);
1639*4882a593Smuzhiyun mutex_init(&rtwdev->hal.tx_power_mutex);
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun init_waitqueue_head(&rtwdev->coex.wait);
1642*4882a593Smuzhiyun
1643*4882a593Smuzhiyun rtwdev->sec.total_cam_num = 32;
1644*4882a593Smuzhiyun rtwdev->hal.current_channel = 1;
1645*4882a593Smuzhiyun set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
1646*4882a593Smuzhiyun if (!(BIT(rtw_fw_lps_deep_mode) & chip->lps_deep_mode_supported))
1647*4882a593Smuzhiyun rtwdev->lps_conf.deep_mode = LPS_DEEP_MODE_NONE;
1648*4882a593Smuzhiyun else
1649*4882a593Smuzhiyun rtwdev->lps_conf.deep_mode = rtw_fw_lps_deep_mode;
1650*4882a593Smuzhiyun
1651*4882a593Smuzhiyun rtw_stats_init(rtwdev);
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun /* default rx filter setting */
1654*4882a593Smuzhiyun rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
1655*4882a593Smuzhiyun BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
1656*4882a593Smuzhiyun BIT_AB | BIT_AM | BIT_APM;
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
1659*4882a593Smuzhiyun if (ret) {
1660*4882a593Smuzhiyun rtw_warn(rtwdev, "no firmware loaded\n");
1661*4882a593Smuzhiyun return ret;
1662*4882a593Smuzhiyun }
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun if (chip->wow_fw_name) {
1665*4882a593Smuzhiyun ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
1666*4882a593Smuzhiyun if (ret) {
1667*4882a593Smuzhiyun rtw_warn(rtwdev, "no wow firmware loaded\n");
1668*4882a593Smuzhiyun wait_for_completion(&rtwdev->fw.completion);
1669*4882a593Smuzhiyun if (rtwdev->fw.firmware)
1670*4882a593Smuzhiyun release_firmware(rtwdev->fw.firmware);
1671*4882a593Smuzhiyun return ret;
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun return 0;
1675*4882a593Smuzhiyun }
1676*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_core_init);
1677*4882a593Smuzhiyun
rtw_core_deinit(struct rtw_dev * rtwdev)1678*4882a593Smuzhiyun void rtw_core_deinit(struct rtw_dev *rtwdev)
1679*4882a593Smuzhiyun {
1680*4882a593Smuzhiyun struct rtw_fw_state *fw = &rtwdev->fw;
1681*4882a593Smuzhiyun struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
1682*4882a593Smuzhiyun struct rtw_rsvd_page *rsvd_pkt, *tmp;
1683*4882a593Smuzhiyun unsigned long flags;
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun rtw_wait_firmware_completion(rtwdev);
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun if (fw->firmware)
1688*4882a593Smuzhiyun release_firmware(fw->firmware);
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun if (wow_fw->firmware)
1691*4882a593Smuzhiyun release_firmware(wow_fw->firmware);
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun tasklet_kill(&rtwdev->tx_tasklet);
1694*4882a593Smuzhiyun spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
1695*4882a593Smuzhiyun skb_queue_purge(&rtwdev->tx_report.queue);
1696*4882a593Smuzhiyun spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
1699*4882a593Smuzhiyun build_list) {
1700*4882a593Smuzhiyun list_del(&rsvd_pkt->build_list);
1701*4882a593Smuzhiyun kfree(rsvd_pkt);
1702*4882a593Smuzhiyun }
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun mutex_destroy(&rtwdev->mutex);
1705*4882a593Smuzhiyun mutex_destroy(&rtwdev->coex.mutex);
1706*4882a593Smuzhiyun mutex_destroy(&rtwdev->hal.tx_power_mutex);
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_core_deinit);
1709*4882a593Smuzhiyun
rtw_register_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)1710*4882a593Smuzhiyun int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1711*4882a593Smuzhiyun {
1712*4882a593Smuzhiyun struct rtw_hal *hal = &rtwdev->hal;
1713*4882a593Smuzhiyun int max_tx_headroom = 0;
1714*4882a593Smuzhiyun int ret;
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun /* TODO: USB & SDIO may need extra room? */
1717*4882a593Smuzhiyun max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
1718*4882a593Smuzhiyun
1719*4882a593Smuzhiyun hw->extra_tx_headroom = max_tx_headroom;
1720*4882a593Smuzhiyun hw->queues = IEEE80211_NUM_ACS;
1721*4882a593Smuzhiyun hw->txq_data_size = sizeof(struct rtw_txq);
1722*4882a593Smuzhiyun hw->sta_data_size = sizeof(struct rtw_sta_info);
1723*4882a593Smuzhiyun hw->vif_data_size = sizeof(struct rtw_vif);
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun ieee80211_hw_set(hw, SIGNAL_DBM);
1726*4882a593Smuzhiyun ieee80211_hw_set(hw, RX_INCLUDES_FCS);
1727*4882a593Smuzhiyun ieee80211_hw_set(hw, AMPDU_AGGREGATION);
1728*4882a593Smuzhiyun ieee80211_hw_set(hw, MFP_CAPABLE);
1729*4882a593Smuzhiyun ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
1730*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_PS);
1731*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
1732*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
1733*4882a593Smuzhiyun ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
1734*4882a593Smuzhiyun ieee80211_hw_set(hw, HAS_RATE_CONTROL);
1735*4882a593Smuzhiyun ieee80211_hw_set(hw, TX_AMSDU);
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1738*4882a593Smuzhiyun BIT(NL80211_IFTYPE_AP) |
1739*4882a593Smuzhiyun BIT(NL80211_IFTYPE_ADHOC) |
1740*4882a593Smuzhiyun BIT(NL80211_IFTYPE_MESH_POINT);
1741*4882a593Smuzhiyun hw->wiphy->available_antennas_tx = hal->antenna_tx;
1742*4882a593Smuzhiyun hw->wiphy->available_antennas_rx = hal->antenna_rx;
1743*4882a593Smuzhiyun
1744*4882a593Smuzhiyun hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
1745*4882a593Smuzhiyun WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1750*4882a593Smuzhiyun
1751*4882a593Smuzhiyun #ifdef CONFIG_PM
1752*4882a593Smuzhiyun hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
1753*4882a593Smuzhiyun hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
1754*4882a593Smuzhiyun #endif
1755*4882a593Smuzhiyun rtw_set_supported_band(hw, rtwdev->chip);
1756*4882a593Smuzhiyun SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun rtw_regd_init(rtwdev, rtw_regd_notifier);
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun ret = ieee80211_register_hw(hw);
1761*4882a593Smuzhiyun if (ret) {
1762*4882a593Smuzhiyun rtw_err(rtwdev, "failed to register hw\n");
1763*4882a593Smuzhiyun return ret;
1764*4882a593Smuzhiyun }
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2))
1767*4882a593Smuzhiyun rtw_err(rtwdev, "regulatory_hint fail\n");
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun rtw_debugfs_init(rtwdev);
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun rtwdev->bf_info.bfer_mu_cnt = 0;
1772*4882a593Smuzhiyun rtwdev->bf_info.bfer_su_cnt = 0;
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun return 0;
1775*4882a593Smuzhiyun }
1776*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_register_hw);
1777*4882a593Smuzhiyun
rtw_unregister_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)1778*4882a593Smuzhiyun void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1779*4882a593Smuzhiyun {
1780*4882a593Smuzhiyun struct rtw_chip_info *chip = rtwdev->chip;
1781*4882a593Smuzhiyun
1782*4882a593Smuzhiyun ieee80211_unregister_hw(hw);
1783*4882a593Smuzhiyun rtw_unset_supported_band(hw, chip);
1784*4882a593Smuzhiyun }
1785*4882a593Smuzhiyun EXPORT_SYMBOL(rtw_unregister_hw);
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun MODULE_AUTHOR("Realtek Corporation");
1788*4882a593Smuzhiyun MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
1789*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
1790