1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __RTW_EFUSE_H__ 6*4882a593Smuzhiyun #define __RTW_EFUSE_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define EFUSE_HW_CAP_IGNORE 0 9*4882a593Smuzhiyun #define EFUSE_HW_CAP_PTCL_VHT 3 10*4882a593Smuzhiyun #define EFUSE_HW_CAP_SUPP_BW80 7 11*4882a593Smuzhiyun #define EFUSE_HW_CAP_SUPP_BW40 6 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define EFUSE_READ_FAIL 0xff 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define GET_EFUSE_HW_CAP_HCI(hw_cap) \ 16*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(3, 0)) 17*4882a593Smuzhiyun #define GET_EFUSE_HW_CAP_BW(hw_cap) \ 18*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(18, 16)) 19*4882a593Smuzhiyun #define GET_EFUSE_HW_CAP_NSS(hw_cap) \ 20*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(20, 19)) 21*4882a593Smuzhiyun #define GET_EFUSE_HW_CAP_ANT_NUM(hw_cap) \ 22*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(23, 21)) 23*4882a593Smuzhiyun #define GET_EFUSE_HW_CAP_PTCL(hw_cap) \ 24*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(27, 26)) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun int rtw_parse_efuse_map(struct rtw_dev *rtwdev); 27*4882a593Smuzhiyun int rtw_read8_physical_efuse(struct rtw_dev *rtwdev, u16 addr, u8 *data); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif 30