1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation.
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifndef __RTW_BF_H_
6*4882a593Smuzhiyun #define __RTW_BF_H_
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #define REG_TXBF_CTRL 0x042C
9*4882a593Smuzhiyun #define REG_RRSR 0x0440
10*4882a593Smuzhiyun #define REG_NDPA_OPT_CTRL 0x045F
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define REG_ASSOCIATED_BFMER0_INFO 0x06E4
13*4882a593Smuzhiyun #define REG_ASSOCIATED_BFMER1_INFO 0x06EC
14*4882a593Smuzhiyun #define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
15*4882a593Smuzhiyun #define REG_SND_PTCL_CTRL 0x0718
16*4882a593Smuzhiyun #define REG_MU_TX_CTL 0x14C0
17*4882a593Smuzhiyun #define REG_MU_STA_GID_VLD 0x14C4
18*4882a593Smuzhiyun #define REG_MU_STA_USER_POS_INFO 0x14C8
19*4882a593Smuzhiyun #define REG_CSI_RRSR 0x1678
20*4882a593Smuzhiyun #define REG_WMAC_MU_BF_OPTION 0x167C
21*4882a593Smuzhiyun #define REG_WMAC_MU_BF_CTL 0x1680
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define BIT_WMAC_USE_NDPARATE BIT(30)
24*4882a593Smuzhiyun #define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
25*4882a593Smuzhiyun #define BIT_USE_NDPA_PARAMETER BIT(30)
26*4882a593Smuzhiyun #define BIT_MU_P1_WAIT_STATE_EN BIT(16)
27*4882a593Smuzhiyun #define BIT_EN_MU_MIMO BIT(7)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define R_MU_RL 0xf
30*4882a593Smuzhiyun #define BIT_SHIFT_R_MU_RL 12
31*4882a593Smuzhiyun #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4
32*4882a593Smuzhiyun #define BIT_SHIFT_CSI_RATE 24
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define BIT_MASK_R_MU_RL (R_MU_RL << BIT_SHIFT_R_MU_RL)
35*4882a593Smuzhiyun #define BIT_MASK_R_MU_TABLE_VALID 0x3f
36*4882a593Smuzhiyun #define BIT_MASK_CSI_RATE_VAL 0x3F
37*4882a593Smuzhiyun #define BIT_MASK_CSI_RATE (BIT_MASK_CSI_RATE_VAL << BIT_SHIFT_CSI_RATE)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define BIT_RXFLTMAP0_ACTIONNOACK BIT(14)
40*4882a593Smuzhiyun #define BIT_RXFLTMAP1_BF (BIT(4) | BIT(5))
41*4882a593Smuzhiyun #define BIT_RXFLTMAP1_BF_REPORT_POLL BIT(4)
42*4882a593Smuzhiyun #define BIT_RXFLTMAP4_BF_REPORT_POLL BIT(4)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define RTW_NDP_RX_STANDBY_TIME 0x70
45*4882a593Smuzhiyun #define RTW_SND_CTRL_REMOVE 0xD8
46*4882a593Smuzhiyun #define RTW_SND_CTRL_SOUNDING 0xDB
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun enum csi_seg_len {
49*4882a593Smuzhiyun HAL_CSI_SEG_4K = 0,
50*4882a593Smuzhiyun HAL_CSI_SEG_8K = 1,
51*4882a593Smuzhiyun HAL_CSI_SEG_11K = 2,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct cfg_mumimo_para {
55*4882a593Smuzhiyun u8 sounding_sts[6];
56*4882a593Smuzhiyun u16 grouping_bitmap;
57*4882a593Smuzhiyun u8 mu_tx_en;
58*4882a593Smuzhiyun u32 given_gid_tab[2];
59*4882a593Smuzhiyun u32 given_user_pos[4];
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct mu_bfer_init_para {
63*4882a593Smuzhiyun u16 paid;
64*4882a593Smuzhiyun u16 csi_para;
65*4882a593Smuzhiyun u16 my_aid;
66*4882a593Smuzhiyun enum csi_seg_len csi_length_sel;
67*4882a593Smuzhiyun u8 bfer_address[ETH_ALEN];
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
71*4882a593Smuzhiyun struct ieee80211_bss_conf *bss_conf);
72*4882a593Smuzhiyun void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
73*4882a593Smuzhiyun struct ieee80211_bss_conf *bss_conf);
74*4882a593Smuzhiyun void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
75*4882a593Smuzhiyun struct mu_bfer_init_para *param);
76*4882a593Smuzhiyun void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
77*4882a593Smuzhiyun enum rtw_trx_desc_rate rate);
78*4882a593Smuzhiyun void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param);
79*4882a593Smuzhiyun void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev);
80*4882a593Smuzhiyun void rtw_bf_del_sounding(struct rtw_dev *rtwdev);
81*4882a593Smuzhiyun void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
82*4882a593Smuzhiyun struct rtw_bfee *bfee);
83*4882a593Smuzhiyun void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
84*4882a593Smuzhiyun struct rtw_bfee *bfee);
85*4882a593Smuzhiyun void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
86*4882a593Smuzhiyun void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
87*4882a593Smuzhiyun void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
88*4882a593Smuzhiyun struct ieee80211_bss_conf *conf);
89*4882a593Smuzhiyun void rtw_bf_phy_init(struct rtw_dev *rtwdev);
90*4882a593Smuzhiyun void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
91*4882a593Smuzhiyun u8 fixrate_en, u8 *new_rate);
rtw_chip_config_bfee(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)92*4882a593Smuzhiyun static inline void rtw_chip_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
93*4882a593Smuzhiyun struct rtw_bfee *bfee, bool enable)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun if (rtwdev->chip->ops->config_bfee)
96*4882a593Smuzhiyun rtwdev->chip->ops->config_bfee(rtwdev, vif, bfee, enable);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
rtw_chip_set_gid_table(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)99*4882a593Smuzhiyun static inline void rtw_chip_set_gid_table(struct rtw_dev *rtwdev,
100*4882a593Smuzhiyun struct ieee80211_vif *vif,
101*4882a593Smuzhiyun struct ieee80211_bss_conf *conf)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun if (rtwdev->chip->ops->set_gid_table)
104*4882a593Smuzhiyun rtwdev->chip->ops->set_gid_table(rtwdev, vif, conf);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
rtw_chip_cfg_csi_rate(struct rtw_dev * rtwdev,u8 rssi,u8 cur_rate,u8 fixrate_en,u8 * new_rate)107*4882a593Smuzhiyun static inline void rtw_chip_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
108*4882a593Smuzhiyun u8 fixrate_en, u8 *new_rate)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun if (rtwdev->chip->ops->cfg_csi_rate)
111*4882a593Smuzhiyun rtwdev->chip->ops->cfg_csi_rate(rtwdev, rssi, cur_rate,
112*4882a593Smuzhiyun fixrate_en, new_rate);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun #endif
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