xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright(c) 2009-2010  Realtek Corporation.*/
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #ifndef __RTL8821AE_DEF_H__
5*4882a593Smuzhiyun #define __RTL8821AE_DEF_H__
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /*--------------------------Define -------------------------------------------*/
8*4882a593Smuzhiyun #define	USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN	1
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* BIT 7 HT Rate*/
11*4882a593Smuzhiyun /*TxHT = 0*/
12*4882a593Smuzhiyun #define	MGN_1M				0x02
13*4882a593Smuzhiyun #define	MGN_2M				0x04
14*4882a593Smuzhiyun #define	MGN_5_5M			0x0b
15*4882a593Smuzhiyun #define	MGN_11M				0x16
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define	MGN_6M				0x0c
18*4882a593Smuzhiyun #define	MGN_9M				0x12
19*4882a593Smuzhiyun #define	MGN_12M				0x18
20*4882a593Smuzhiyun #define	MGN_18M				0x24
21*4882a593Smuzhiyun #define	MGN_24M				0x30
22*4882a593Smuzhiyun #define	MGN_36M				0x48
23*4882a593Smuzhiyun #define	MGN_48M				0x60
24*4882a593Smuzhiyun #define	MGN_54M				0x6c
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /* TxHT = 1 */
27*4882a593Smuzhiyun #define	MGN_MCS0			0x80
28*4882a593Smuzhiyun #define	MGN_MCS1			0x81
29*4882a593Smuzhiyun #define	MGN_MCS2			0x82
30*4882a593Smuzhiyun #define	MGN_MCS3			0x83
31*4882a593Smuzhiyun #define	MGN_MCS4			0x84
32*4882a593Smuzhiyun #define	MGN_MCS5			0x85
33*4882a593Smuzhiyun #define	MGN_MCS6			0x86
34*4882a593Smuzhiyun #define	MGN_MCS7			0x87
35*4882a593Smuzhiyun #define	MGN_MCS8			0x88
36*4882a593Smuzhiyun #define	MGN_MCS9			0x89
37*4882a593Smuzhiyun #define	MGN_MCS10			0x8a
38*4882a593Smuzhiyun #define	MGN_MCS11			0x8b
39*4882a593Smuzhiyun #define	MGN_MCS12			0x8c
40*4882a593Smuzhiyun #define	MGN_MCS13			0x8d
41*4882a593Smuzhiyun #define	MGN_MCS14			0x8e
42*4882a593Smuzhiyun #define	MGN_MCS15			0x8f
43*4882a593Smuzhiyun /* VHT rate */
44*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS0		0x90
45*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS1		0x91
46*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS2		0x92
47*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS3		0x93
48*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS4		0x94
49*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS5		0x95
50*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS6		0x96
51*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS7		0x97
52*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS8		0x98
53*4882a593Smuzhiyun #define	MGN_VHT1SS_MCS9		0x99
54*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS0		0x9a
55*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS1		0x9b
56*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS2		0x9c
57*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS3		0x9d
58*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS4		0x9e
59*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS5		0x9f
60*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS6		0xa0
61*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS7		0xa1
62*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS8		0xa2
63*4882a593Smuzhiyun #define	MGN_VHT2SS_MCS9		0xa3
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS0		0xa4
66*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS1		0xa5
67*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS2		0xa6
68*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS3		0xa7
69*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS4		0xa8
70*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS5		0xa9
71*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS6		0xaa
72*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS7		0xab
73*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS8		0xac
74*4882a593Smuzhiyun #define	MGN_VHT3SS_MCS9		0xad
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define	MGN_MCS0_SG			0xc0
77*4882a593Smuzhiyun #define	MGN_MCS1_SG			0xc1
78*4882a593Smuzhiyun #define	MGN_MCS2_SG			0xc2
79*4882a593Smuzhiyun #define	MGN_MCS3_SG			0xc3
80*4882a593Smuzhiyun #define	MGN_MCS4_SG			0xc4
81*4882a593Smuzhiyun #define	MGN_MCS5_SG			0xc5
82*4882a593Smuzhiyun #define	MGN_MCS6_SG			0xc6
83*4882a593Smuzhiyun #define	MGN_MCS7_SG			0xc7
84*4882a593Smuzhiyun #define	MGN_MCS8_SG			0xc8
85*4882a593Smuzhiyun #define	MGN_MCS9_SG			0xc9
86*4882a593Smuzhiyun #define	MGN_MCS10_SG		0xca
87*4882a593Smuzhiyun #define	MGN_MCS11_SG		0xcb
88*4882a593Smuzhiyun #define	MGN_MCS12_SG		0xcc
89*4882a593Smuzhiyun #define	MGN_MCS13_SG		0xcd
90*4882a593Smuzhiyun #define	MGN_MCS14_SG		0xce
91*4882a593Smuzhiyun #define	MGN_MCS15_SG		0xcf
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define	MGN_UNKNOWN			0xff
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /* 30 ms */
96*4882a593Smuzhiyun #define	WIFI_NAV_UPPER_US				30000
97*4882a593Smuzhiyun #define HAL_92C_NAV_UPPER_UNIT			128
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE				0x3E80
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_DONT_CARE		0
102*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_LOWER			1
103*4882a593Smuzhiyun #define HAL_PRIME_CHNL_OFFSET_UPPER			2
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define RX_MPDU_QUEUE						0
106*4882a593Smuzhiyun #define RX_CMD_QUEUE						1
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8812	0x3E80
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22)&0x3)
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define CHIP_8812				BIT(2)
113*4882a593Smuzhiyun #define CHIP_8821				(BIT(0)|BIT(2))
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #define CHIP_8821A				(BIT(0)|BIT(2))
116*4882a593Smuzhiyun #define NORMAL_CHIP				BIT(3)
117*4882a593Smuzhiyun #define RF_TYPE_1T1R				(~(BIT(4)|BIT(5)|BIT(6)))
118*4882a593Smuzhiyun #define RF_TYPE_1T2R				BIT(4)
119*4882a593Smuzhiyun #define RF_TYPE_2T2R				BIT(5)
120*4882a593Smuzhiyun #define CHIP_VENDOR_UMC				BIT(7)
121*4882a593Smuzhiyun #define B_CUT_VERSION				BIT(12)
122*4882a593Smuzhiyun #define C_CUT_VERSION				BIT(13)
123*4882a593Smuzhiyun #define D_CUT_VERSION				((BIT(12)|BIT(13)))
124*4882a593Smuzhiyun #define E_CUT_VERSION				BIT(14)
125*4882a593Smuzhiyun #define	RF_RL_ID			(BIT(31)|BIT(30)|BIT(29)|BIT(28))
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun enum version_8821ae {
128*4882a593Smuzhiyun 	VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
129*4882a593Smuzhiyun 	VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
130*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
131*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
132*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
133*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
134*4882a593Smuzhiyun 	VERSION_TEST_CHIP_8821 = 0x0005,
135*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
136*4882a593Smuzhiyun 	VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
137*4882a593Smuzhiyun 	VERSION_UNKNOWN = 0xFF,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun enum vht_data_sc {
141*4882a593Smuzhiyun 	VHT_DATA_SC_DONOT_CARE = 0,
142*4882a593Smuzhiyun 	VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
143*4882a593Smuzhiyun 	VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
144*4882a593Smuzhiyun 	VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
145*4882a593Smuzhiyun 	VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
146*4882a593Smuzhiyun 	VHT_DATA_SC_20_RECV1 = 5,
147*4882a593Smuzhiyun 	VHT_DATA_SC_20_RECV2 = 6,
148*4882a593Smuzhiyun 	VHT_DATA_SC_20_RECV3 = 7,
149*4882a593Smuzhiyun 	VHT_DATA_SC_20_RECV4 = 8,
150*4882a593Smuzhiyun 	VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
151*4882a593Smuzhiyun 	VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /* MASK */
155*4882a593Smuzhiyun #define IC_TYPE_MASK			(BIT(0)|BIT(1)|BIT(2))
156*4882a593Smuzhiyun #define CHIP_TYPE_MASK			BIT(3)
157*4882a593Smuzhiyun #define RF_TYPE_MASK			(BIT(4)|BIT(5)|BIT(6))
158*4882a593Smuzhiyun #define MANUFACTUER_MASK		BIT(7)
159*4882a593Smuzhiyun #define ROM_VERSION_MASK		(BIT(11)|BIT(10)|BIT(9)|BIT(8))
160*4882a593Smuzhiyun #define CUT_VERSION_MASK		(BIT(15)|BIT(14)|BIT(13)|BIT(12))
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /* Get element */
163*4882a593Smuzhiyun #define GET_CVID_IC_TYPE(version)	((version) & IC_TYPE_MASK)
164*4882a593Smuzhiyun #define GET_CVID_CHIP_TYPE(version)	((version) & CHIP_TYPE_MASK)
165*4882a593Smuzhiyun #define GET_CVID_RF_TYPE(version)	((version) & RF_TYPE_MASK)
166*4882a593Smuzhiyun #define GET_CVID_MANUFACTUER(version)	((version) & MANUFACTUER_MASK)
167*4882a593Smuzhiyun #define GET_CVID_ROM_VERSION(version)	((version) & ROM_VERSION_MASK)
168*4882a593Smuzhiyun #define GET_CVID_CUT_VERSION(version)	((version) & CUT_VERSION_MASK)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun #define IS_1T1R(version)	((GET_CVID_RF_TYPE(version)) ? false : true)
171*4882a593Smuzhiyun #define IS_1T2R(version)	((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
172*4882a593Smuzhiyun 							? true : false)
173*4882a593Smuzhiyun #define IS_2T2R(version)	((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
174*4882a593Smuzhiyun 							? true : false)
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun #define IS_8812_SERIES(version)	((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
177*4882a593Smuzhiyun 								true : false)
178*4882a593Smuzhiyun #define IS_8821_SERIES(version)	((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
179*4882a593Smuzhiyun 								true : false)
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #define IS_VENDOR_8812A_TEST_CHIP(version)	((IS_8812_SERIES(version)) ? \
182*4882a593Smuzhiyun 					((IS_NORMAL_CHIP(version)) ? \
183*4882a593Smuzhiyun 						false : true) : false)
184*4882a593Smuzhiyun #define IS_VENDOR_8812A_MP_CHIP(version)	((IS_8812_SERIES(version)) ? \
185*4882a593Smuzhiyun 					((IS_NORMAL_CHIP(version)) ? \
186*4882a593Smuzhiyun 						true : false) : false)
187*4882a593Smuzhiyun #define IS_VENDOR_8812A_C_CUT(version)		((IS_8812_SERIES(version)) ? \
188*4882a593Smuzhiyun 					((GET_CVID_CUT_VERSION(version) == \
189*4882a593Smuzhiyun 					C_CUT_VERSION) ? \
190*4882a593Smuzhiyun 					true : false) : false)
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #define IS_VENDOR_8821A_TEST_CHIP(version)	((IS_8821_SERIES(version)) ? \
193*4882a593Smuzhiyun 					((IS_NORMAL_CHIP(version)) ? \
194*4882a593Smuzhiyun 					false : true) : false)
195*4882a593Smuzhiyun #define IS_VENDOR_8821A_MP_CHIP(version)	((IS_8821_SERIES(version)) ? \
196*4882a593Smuzhiyun 					((IS_NORMAL_CHIP(version)) ? \
197*4882a593Smuzhiyun 						true : false) : false)
198*4882a593Smuzhiyun #define IS_VENDOR_8821A_B_CUT(version)		((IS_8821_SERIES(version)) ? \
199*4882a593Smuzhiyun 					((GET_CVID_CUT_VERSION(version) == \
200*4882a593Smuzhiyun 					B_CUT_VERSION) ? \
201*4882a593Smuzhiyun 					true : false) : false)
202*4882a593Smuzhiyun enum board_type {
203*4882a593Smuzhiyun 	ODM_BOARD_DEFAULT = 0,	  /* The DEFAULT case. */
204*4882a593Smuzhiyun 	ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
205*4882a593Smuzhiyun 	ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
206*4882a593Smuzhiyun 	ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
207*4882a593Smuzhiyun 	ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
208*4882a593Smuzhiyun 	ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
209*4882a593Smuzhiyun 	ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
210*4882a593Smuzhiyun 	ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
211*4882a593Smuzhiyun 	ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun enum rf_optype {
215*4882a593Smuzhiyun 	RF_OP_BY_SW_3WIRE = 0,
216*4882a593Smuzhiyun 	RF_OP_BY_FW,
217*4882a593Smuzhiyun 	RF_OP_MAX
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun enum rf_power_state {
221*4882a593Smuzhiyun 	RF_ON,
222*4882a593Smuzhiyun 	RF_OFF,
223*4882a593Smuzhiyun 	RF_SLEEP,
224*4882a593Smuzhiyun 	RF_SHUT_DOWN,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun enum power_save_mode {
228*4882a593Smuzhiyun 	POWER_SAVE_MODE_ACTIVE,
229*4882a593Smuzhiyun 	POWER_SAVE_MODE_SAVE,
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun enum power_polocy_config {
233*4882a593Smuzhiyun 	POWERCFG_MAX_POWER_SAVINGS,
234*4882a593Smuzhiyun 	POWERCFG_GLOBAL_POWER_SAVINGS,
235*4882a593Smuzhiyun 	POWERCFG_LOCAL_POWER_SAVINGS,
236*4882a593Smuzhiyun 	POWERCFG_LENOVO,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun enum interface_select_pci {
240*4882a593Smuzhiyun 	INTF_SEL1_MINICARD = 0,
241*4882a593Smuzhiyun 	INTF_SEL0_PCIE = 1,
242*4882a593Smuzhiyun 	INTF_SEL2_RSV = 2,
243*4882a593Smuzhiyun 	INTF_SEL3_RSV = 3,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun enum rtl_desc_qsel {
247*4882a593Smuzhiyun 	QSLT_BK = 0x2,
248*4882a593Smuzhiyun 	QSLT_BE = 0x0,
249*4882a593Smuzhiyun 	QSLT_VI = 0x5,
250*4882a593Smuzhiyun 	QSLT_VO = 0x7,
251*4882a593Smuzhiyun 	QSLT_BEACON = 0x10,
252*4882a593Smuzhiyun 	QSLT_HIGH = 0x11,
253*4882a593Smuzhiyun 	QSLT_MGNT = 0x12,
254*4882a593Smuzhiyun 	QSLT_CMD = 0x13,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun struct phy_sts_cck_8821ae_t {
258*4882a593Smuzhiyun 	u8 adc_pwdb_X[4];
259*4882a593Smuzhiyun 	u8 sq_rpt;
260*4882a593Smuzhiyun 	u8 cck_agc_rpt;
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun struct h2c_cmd_8821ae {
264*4882a593Smuzhiyun 	u8 element_id;
265*4882a593Smuzhiyun 	u32 cmd_len;
266*4882a593Smuzhiyun 	u8 *p_cmdbuffer;
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #endif
270